Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	66200488	15355	0	0
claim_transition_if_regwen_rd_A	66200488	1180	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66200488	15355	0	0
T97	194074	1	0	0
T98	0	18	0	0
T99	0	5	0	0
T101	126729	0	0	0
T120	39060	0	0	0
T156	0	3	0	0
T157	0	26	0	0
T158	0	6	0	0
T159	0	15	0	0
T160	0	6	0	0
T161	0	1	0	0
T162	0	19	0	0
T163	28498	0	0	0
T164	5325	0	0	0
T165	45331	0	0	0
T166	26606	0	0	0
T167	3859	0	0	0
T168	59220	0	0	0
T169	20158	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66200488	1180	0	0
T99	520012	9	0	0
T121	0	7	0	0
T122	0	102	0	0
T124	0	92	0	0
T126	0	47	0	0
T160	0	5	0	0
T161	0	9	0	0
T170	0	2	0	0
T171	0	5	0	0
T172	0	3	0	0
T173	1407	0	0	0
T174	40505	0	0	0
T175	10171	0	0	0
T176	26783	0	0	0
T177	68724	0	0	0
T178	21177	0	0	0
T179	10428	0	0	0
T180	32670	0	0	0
T181	37356	0	0	0