| T389 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3585543 |
|
|
Oct 03 11:39:25 AM UTC 24 |
Oct 03 11:39:37 AM UTC 24 |
210424986 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.4001926028 |
|
|
Oct 03 11:39:36 AM UTC 24 |
Oct 03 11:39:38 AM UTC 24 |
22978013 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.1765523462 |
|
|
Oct 03 11:39:27 AM UTC 24 |
Oct 03 11:39:39 AM UTC 24 |
6267099450 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.4276451683 |
|
|
Oct 03 11:39:32 AM UTC 24 |
Oct 03 11:39:41 AM UTC 24 |
398811867 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.628561063 |
|
|
Oct 03 11:39:39 AM UTC 24 |
Oct 03 11:39:42 AM UTC 24 |
14227812 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3939093329 |
|
|
Oct 03 11:38:30 AM UTC 24 |
Oct 03 11:39:42 AM UTC 24 |
2042841534 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.18721471 |
|
|
Oct 03 11:39:14 AM UTC 24 |
Oct 03 11:39:42 AM UTC 24 |
1562454867 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.2556369725 |
|
|
Oct 03 11:39:29 AM UTC 24 |
Oct 03 11:39:43 AM UTC 24 |
290817691 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1775772310 |
|
|
Oct 03 11:39:38 AM UTC 24 |
Oct 03 11:39:43 AM UTC 24 |
108684053 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3257883821 |
|
|
Oct 03 11:38:57 AM UTC 24 |
Oct 03 11:39:44 AM UTC 24 |
12673154840 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.2904310041 |
|
|
Oct 03 11:39:27 AM UTC 24 |
Oct 03 11:39:44 AM UTC 24 |
453343124 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.2531916997 |
|
|
Oct 03 11:39:34 AM UTC 24 |
Oct 03 11:39:45 AM UTC 24 |
1108655619 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.286960333 |
|
|
Oct 03 11:39:43 AM UTC 24 |
Oct 03 11:39:47 AM UTC 24 |
40642746 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2163100282 |
|
|
Oct 03 11:39:20 AM UTC 24 |
Oct 03 11:39:48 AM UTC 24 |
610515534 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2010075652 |
|
|
Oct 03 11:39:24 AM UTC 24 |
Oct 03 11:39:48 AM UTC 24 |
916391931 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.2802668552 |
|
|
Oct 03 11:39:46 AM UTC 24 |
Oct 03 11:39:50 AM UTC 24 |
69358486 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.934247844 |
|
|
Oct 03 11:39:33 AM UTC 24 |
Oct 03 11:39:50 AM UTC 24 |
437074772 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.202338225 |
|
|
Oct 03 11:38:50 AM UTC 24 |
Oct 03 11:39:51 AM UTC 24 |
7347892679 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.422905868 |
|
|
Oct 03 11:39:17 AM UTC 24 |
Oct 03 11:39:51 AM UTC 24 |
1126894502 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.3923746391 |
|
|
Oct 03 11:40:17 AM UTC 24 |
Oct 03 11:40:20 AM UTC 24 |
23288397 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3814136500 |
|
|
Oct 03 11:39:48 AM UTC 24 |
Oct 03 11:39:52 AM UTC 24 |
165448414 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.2533346445 |
|
|
Oct 03 11:39:34 AM UTC 24 |
Oct 03 11:39:52 AM UTC 24 |
1442650960 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1249774800 |
|
|
Oct 03 11:39:43 AM UTC 24 |
Oct 03 11:39:52 AM UTC 24 |
193042537 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.3258430202 |
|
|
Oct 03 11:40:14 AM UTC 24 |
Oct 03 11:40:27 AM UTC 24 |
322459553 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.1241010211 |
|
|
Oct 03 11:39:41 AM UTC 24 |
Oct 03 11:39:52 AM UTC 24 |
1191310213 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.1818734128 |
|
|
Oct 03 11:39:44 AM UTC 24 |
Oct 03 11:39:54 AM UTC 24 |
1131754247 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.4218765612 |
|
|
Oct 03 11:39:53 AM UTC 24 |
Oct 03 11:39:55 AM UTC 24 |
12681655 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2696479075 |
|
|
Oct 03 11:39:44 AM UTC 24 |
Oct 03 11:39:56 AM UTC 24 |
803006186 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1362210359 |
|
|
Oct 03 11:39:53 AM UTC 24 |
Oct 03 11:39:56 AM UTC 24 |
14476451 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.2968410079 |
|
|
Oct 03 11:39:53 AM UTC 24 |
Oct 03 11:39:56 AM UTC 24 |
101741837 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.3255518709 |
|
|
Oct 03 11:39:31 AM UTC 24 |
Oct 03 11:40:21 AM UTC 24 |
3217027441 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4179325758 |
|
|
Oct 03 11:37:03 AM UTC 24 |
Oct 03 11:39:57 AM UTC 24 |
3998965020 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.1006981538 |
|
|
Oct 03 11:40:19 AM UTC 24 |
Oct 03 11:40:24 AM UTC 24 |
39986506 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.4219280851 |
|
|
Oct 03 11:39:53 AM UTC 24 |
Oct 03 11:39:59 AM UTC 24 |
80074029 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.1397235835 |
|
|
Oct 03 11:39:48 AM UTC 24 |
Oct 03 11:40:00 AM UTC 24 |
646457492 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.3169357300 |
|
|
Oct 03 11:39:58 AM UTC 24 |
Oct 03 11:40:03 AM UTC 24 |
217730619 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3653966021 |
|
|
Oct 03 11:39:49 AM UTC 24 |
Oct 03 11:40:04 AM UTC 24 |
371640678 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3203625676 |
|
|
Oct 03 11:39:49 AM UTC 24 |
Oct 03 11:40:05 AM UTC 24 |
386360210 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.4188617978 |
|
|
Oct 03 11:39:53 AM UTC 24 |
Oct 03 11:40:06 AM UTC 24 |
80628331 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2335066004 |
|
|
Oct 03 11:39:55 AM UTC 24 |
Oct 03 11:40:08 AM UTC 24 |
359952977 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.291485509 |
|
|
Oct 03 11:39:57 AM UTC 24 |
Oct 03 11:40:08 AM UTC 24 |
299499179 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.819172273 |
|
|
Oct 03 11:39:05 AM UTC 24 |
Oct 03 11:40:09 AM UTC 24 |
2155877301 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.2475037971 |
|
|
Oct 03 11:39:46 AM UTC 24 |
Oct 03 11:40:09 AM UTC 24 |
10981353929 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.499771862 |
|
|
Oct 03 11:40:06 AM UTC 24 |
Oct 03 11:40:10 AM UTC 24 |
63633101 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.2775622529 |
|
|
Oct 03 11:39:39 AM UTC 24 |
Oct 03 11:40:10 AM UTC 24 |
1009585635 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.802593955 |
|
|
Oct 03 11:39:57 AM UTC 24 |
Oct 03 11:40:10 AM UTC 24 |
1486683542 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.2348458742 |
|
|
Oct 03 11:39:04 AM UTC 24 |
Oct 03 11:40:11 AM UTC 24 |
6267576747 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.1261992645 |
|
|
Oct 03 11:40:07 AM UTC 24 |
Oct 03 11:40:11 AM UTC 24 |
35915580 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1976859566 |
|
|
Oct 03 11:39:58 AM UTC 24 |
Oct 03 11:40:12 AM UTC 24 |
584456940 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.2253158920 |
|
|
Oct 03 11:38:44 AM UTC 24 |
Oct 03 11:40:12 AM UTC 24 |
11007986414 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3925209158 |
|
|
Oct 03 11:40:10 AM UTC 24 |
Oct 03 11:40:12 AM UTC 24 |
95387478 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.3101533191 |
|
|
Oct 03 11:40:00 AM UTC 24 |
Oct 03 11:40:12 AM UTC 24 |
1437660743 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.1360032444 |
|
|
Oct 03 11:40:01 AM UTC 24 |
Oct 03 11:40:12 AM UTC 24 |
663422828 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.793985348 |
|
|
Oct 03 11:39:53 AM UTC 24 |
Oct 03 11:40:13 AM UTC 24 |
1854978655 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.133839036 |
|
|
Oct 03 11:40:10 AM UTC 24 |
Oct 03 11:40:13 AM UTC 24 |
22404305 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.2354105136 |
|
|
Oct 03 11:40:00 AM UTC 24 |
Oct 03 11:40:13 AM UTC 24 |
2559303150 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.327779391 |
|
|
Oct 03 11:39:27 AM UTC 24 |
Oct 03 11:40:14 AM UTC 24 |
3470310618 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.2835536574 |
|
|
Oct 03 11:40:11 AM UTC 24 |
Oct 03 11:40:16 AM UTC 24 |
154116083 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.4111029146 |
|
|
Oct 03 11:39:46 AM UTC 24 |
Oct 03 11:40:17 AM UTC 24 |
974167246 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.705373156 |
|
|
Oct 03 11:40:10 AM UTC 24 |
Oct 03 11:40:18 AM UTC 24 |
160169175 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2529550706 |
|
|
Oct 03 11:40:16 AM UTC 24 |
Oct 03 11:40:18 AM UTC 24 |
101410116 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3681481730 |
|
|
Oct 03 11:39:53 AM UTC 24 |
Oct 03 11:40:18 AM UTC 24 |
156050504 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.1429874462 |
|
|
Oct 03 11:40:11 AM UTC 24 |
Oct 03 11:40:19 AM UTC 24 |
186160075 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.2571255756 |
|
|
Oct 03 11:36:44 AM UTC 24 |
Oct 03 11:40:20 AM UTC 24 |
5531910597 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2090617079 |
|
|
Oct 03 11:40:18 AM UTC 24 |
Oct 03 11:40:20 AM UTC 24 |
14235838 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.2153077574 |
|
|
Oct 03 11:40:14 AM UTC 24 |
Oct 03 11:40:26 AM UTC 24 |
405081566 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.962292688 |
|
|
Oct 03 11:40:19 AM UTC 24 |
Oct 03 11:40:26 AM UTC 24 |
102754326 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.1865129954 |
|
|
Oct 03 11:40:12 AM UTC 24 |
Oct 03 11:40:27 AM UTC 24 |
372027625 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3416035094 |
|
|
Oct 03 11:40:14 AM UTC 24 |
Oct 03 11:40:28 AM UTC 24 |
2863646977 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.1277406170 |
|
|
Oct 03 11:40:14 AM UTC 24 |
Oct 03 11:40:28 AM UTC 24 |
882475721 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.967900803 |
|
|
Oct 03 11:40:23 AM UTC 24 |
Oct 03 11:40:28 AM UTC 24 |
359661490 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3959394980 |
|
|
Oct 03 11:40:21 AM UTC 24 |
Oct 03 11:40:29 AM UTC 24 |
343909065 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.72378888 |
|
|
Oct 03 11:40:11 AM UTC 24 |
Oct 03 11:40:31 AM UTC 24 |
1436832510 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.3598793712 |
|
|
Oct 03 11:40:29 AM UTC 24 |
Oct 03 11:40:33 AM UTC 24 |
22455326 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1262891339 |
|
|
Oct 03 11:38:44 AM UTC 24 |
Oct 03 11:40:33 AM UTC 24 |
15823454742 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1640224764 |
|
|
Oct 03 11:40:30 AM UTC 24 |
Oct 03 11:40:34 AM UTC 24 |
26925457 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.85816883 |
|
|
Oct 03 11:40:32 AM UTC 24 |
Oct 03 11:40:35 AM UTC 24 |
14686035 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.3990856279 |
|
|
Oct 03 11:40:27 AM UTC 24 |
Oct 03 11:40:35 AM UTC 24 |
1735412222 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.3608998665 |
|
|
Oct 03 11:40:21 AM UTC 24 |
Oct 03 11:40:36 AM UTC 24 |
2598378790 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.724625503 |
|
|
Oct 03 11:40:21 AM UTC 24 |
Oct 03 11:40:37 AM UTC 24 |
304639145 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3764662983 |
|
|
Oct 03 11:40:28 AM UTC 24 |
Oct 03 11:40:38 AM UTC 24 |
185938508 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2536447213 |
|
|
Oct 03 11:41:10 AM UTC 24 |
Oct 03 11:41:22 AM UTC 24 |
236555639 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2433366183 |
|
|
Oct 03 11:40:10 AM UTC 24 |
Oct 03 11:40:38 AM UTC 24 |
1089335588 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.2595054270 |
|
|
Oct 03 11:40:22 AM UTC 24 |
Oct 03 11:40:38 AM UTC 24 |
874207841 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.2175669691 |
|
|
Oct 03 11:40:35 AM UTC 24 |
Oct 03 11:40:39 AM UTC 24 |
124529990 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.652688139 |
|
|
Oct 03 11:40:27 AM UTC 24 |
Oct 03 11:40:40 AM UTC 24 |
400021698 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.618384887 |
|
|
Oct 03 11:40:28 AM UTC 24 |
Oct 03 11:40:42 AM UTC 24 |
5392362459 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.2523022291 |
|
|
Oct 03 11:40:34 AM UTC 24 |
Oct 03 11:40:45 AM UTC 24 |
378093132 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3766648724 |
|
|
Oct 03 11:40:19 AM UTC 24 |
Oct 03 11:40:45 AM UTC 24 |
303509219 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.713050030 |
|
|
Oct 03 11:40:36 AM UTC 24 |
Oct 03 11:40:46 AM UTC 24 |
238355102 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.3353228622 |
|
|
Oct 03 11:40:39 AM UTC 24 |
Oct 03 11:40:47 AM UTC 24 |
1906259941 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.235127933 |
|
|
Oct 03 11:39:17 AM UTC 24 |
Oct 03 11:40:48 AM UTC 24 |
8052398207 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.260146420 |
|
|
Oct 03 11:40:45 AM UTC 24 |
Oct 03 11:40:48 AM UTC 24 |
37376358 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2752156778 |
|
|
Oct 03 11:40:46 AM UTC 24 |
Oct 03 11:40:49 AM UTC 24 |
12365757 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.1056776236 |
|
|
Oct 03 11:40:36 AM UTC 24 |
Oct 03 11:40:50 AM UTC 24 |
419789139 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1927066435 |
|
|
Oct 03 11:40:46 AM UTC 24 |
Oct 03 11:40:50 AM UTC 24 |
182564787 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.224889592 |
|
|
Oct 03 11:37:32 AM UTC 24 |
Oct 03 11:41:23 AM UTC 24 |
21676941356 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.1508740128 |
|
|
Oct 03 11:40:39 AM UTC 24 |
Oct 03 11:40:50 AM UTC 24 |
1899601129 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.3679392276 |
|
|
Oct 03 11:39:44 AM UTC 24 |
Oct 03 11:40:53 AM UTC 24 |
24224232050 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.872948398 |
|
|
Oct 03 11:40:25 AM UTC 24 |
Oct 03 11:40:53 AM UTC 24 |
1214868183 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.110591220 |
|
|
Oct 03 11:40:40 AM UTC 24 |
Oct 03 11:40:53 AM UTC 24 |
298063774 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.4039727518 |
|
|
Oct 03 11:40:43 AM UTC 24 |
Oct 03 11:40:53 AM UTC 24 |
1401997487 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.3424293752 |
|
|
Oct 03 11:40:49 AM UTC 24 |
Oct 03 11:40:53 AM UTC 24 |
37028959 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.1743471047 |
|
|
Oct 03 11:40:39 AM UTC 24 |
Oct 03 11:40:54 AM UTC 24 |
2847473875 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3023050100 |
|
|
Oct 03 11:41:21 AM UTC 24 |
Oct 03 11:41:24 AM UTC 24 |
49572117 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1974748427 |
|
|
Oct 03 11:40:49 AM UTC 24 |
Oct 03 11:40:55 AM UTC 24 |
91704094 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.4135897355 |
|
|
Oct 03 11:40:36 AM UTC 24 |
Oct 03 11:40:55 AM UTC 24 |
789345977 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.3275111044 |
|
|
Oct 03 11:39:57 AM UTC 24 |
Oct 03 11:40:55 AM UTC 24 |
3453544686 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.3481729358 |
|
|
Oct 03 11:40:14 AM UTC 24 |
Oct 03 11:40:56 AM UTC 24 |
5101597448 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.144952023 |
|
|
Oct 03 11:40:14 AM UTC 24 |
Oct 03 11:40:57 AM UTC 24 |
6305295094 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2588436375 |
|
|
Oct 03 11:40:57 AM UTC 24 |
Oct 03 11:40:59 AM UTC 24 |
14603198 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.458313536 |
|
|
Oct 03 11:40:12 AM UTC 24 |
Oct 03 11:40:59 AM UTC 24 |
4547896583 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.785904541 |
|
|
Oct 03 11:40:57 AM UTC 24 |
Oct 03 11:40:59 AM UTC 24 |
17267079 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3223665191 |
|
|
Oct 03 11:40:50 AM UTC 24 |
Oct 03 11:41:00 AM UTC 24 |
354196543 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.2220991457 |
|
|
Oct 03 11:40:51 AM UTC 24 |
Oct 03 11:41:01 AM UTC 24 |
1626908133 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3889212743 |
|
|
Oct 03 11:40:39 AM UTC 24 |
Oct 03 11:41:01 AM UTC 24 |
525905591 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.2026640558 |
|
|
Oct 03 11:38:53 AM UTC 24 |
Oct 03 11:41:02 AM UTC 24 |
9644318823 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.4231116194 |
|
|
Oct 03 11:40:57 AM UTC 24 |
Oct 03 11:41:02 AM UTC 24 |
48178845 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2001213756 |
|
|
Oct 03 11:40:54 AM UTC 24 |
Oct 03 11:41:03 AM UTC 24 |
264310219 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.1675171708 |
|
|
Oct 03 11:41:00 AM UTC 24 |
Oct 03 11:41:04 AM UTC 24 |
171937115 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.1388769096 |
|
|
Oct 03 11:40:39 AM UTC 24 |
Oct 03 11:41:05 AM UTC 24 |
1498592373 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.2393744744 |
|
|
Oct 03 11:41:00 AM UTC 24 |
Oct 03 11:41:08 AM UTC 24 |
490118266 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2543846816 |
|
|
Oct 03 11:40:34 AM UTC 24 |
Oct 03 11:41:08 AM UTC 24 |
351810080 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3161304287 |
|
|
Oct 03 11:40:51 AM UTC 24 |
Oct 03 11:41:08 AM UTC 24 |
730052878 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.411010508 |
|
|
Oct 03 11:41:03 AM UTC 24 |
Oct 03 11:41:09 AM UTC 24 |
361481226 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1906488864 |
|
|
Oct 03 11:40:54 AM UTC 24 |
Oct 03 11:41:09 AM UTC 24 |
1038603117 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.3689024672 |
|
|
Oct 03 11:41:05 AM UTC 24 |
Oct 03 11:41:09 AM UTC 24 |
309931575 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2704846404 |
|
|
Oct 03 11:39:19 AM UTC 24 |
Oct 03 11:41:10 AM UTC 24 |
44175183275 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.468788060 |
|
|
Oct 03 11:41:01 AM UTC 24 |
Oct 03 11:41:11 AM UTC 24 |
309502870 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.2626360096 |
|
|
Oct 03 11:40:55 AM UTC 24 |
Oct 03 11:41:11 AM UTC 24 |
666777122 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2808024946 |
|
|
Oct 03 11:40:54 AM UTC 24 |
Oct 03 11:41:11 AM UTC 24 |
537121269 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1823527618 |
|
|
Oct 03 11:41:10 AM UTC 24 |
Oct 03 11:41:12 AM UTC 24 |
28979879 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.3038156151 |
|
|
Oct 03 11:40:54 AM UTC 24 |
Oct 03 11:41:12 AM UTC 24 |
3049491305 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.3260266376 |
|
|
Oct 03 11:41:10 AM UTC 24 |
Oct 03 11:41:13 AM UTC 24 |
20778053 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1331583205 |
|
|
Oct 03 11:41:11 AM UTC 24 |
Oct 03 11:41:13 AM UTC 24 |
14871644 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.3057637567 |
|
|
Oct 03 11:41:01 AM UTC 24 |
Oct 03 11:41:14 AM UTC 24 |
639132891 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.2137727984 |
|
|
Oct 03 11:39:09 AM UTC 24 |
Oct 03 11:41:14 AM UTC 24 |
15091995085 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.4272991506 |
|
|
Oct 03 11:41:00 AM UTC 24 |
Oct 03 11:41:15 AM UTC 24 |
1342776307 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.2342514124 |
|
|
Oct 03 11:41:13 AM UTC 24 |
Oct 03 11:41:17 AM UTC 24 |
342470776 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4234419638 |
|
|
Oct 03 11:41:03 AM UTC 24 |
Oct 03 11:41:19 AM UTC 24 |
1975687684 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.1038797010 |
|
|
Oct 03 11:41:18 AM UTC 24 |
Oct 03 11:41:20 AM UTC 24 |
24420923 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.374889073 |
|
|
Oct 03 11:41:08 AM UTC 24 |
Oct 03 11:41:22 AM UTC 24 |
1197556510 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.1586628288 |
|
|
Oct 03 11:41:12 AM UTC 24 |
Oct 03 11:41:22 AM UTC 24 |
203737564 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.2133552421 |
|
|
Oct 03 11:41:14 AM UTC 24 |
Oct 03 11:41:22 AM UTC 24 |
918119725 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.2815964105 |
|
|
Oct 03 11:40:47 AM UTC 24 |
Oct 03 11:41:24 AM UTC 24 |
767981518 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.2599106137 |
|
|
Oct 03 11:41:20 AM UTC 24 |
Oct 03 11:41:25 AM UTC 24 |
104701609 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1478238421 |
|
|
Oct 03 11:41:15 AM UTC 24 |
Oct 03 11:41:26 AM UTC 24 |
886769404 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2271731999 |
|
|
Oct 03 11:41:06 AM UTC 24 |
Oct 03 11:41:27 AM UTC 24 |
2041701923 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.6947204 |
|
|
Oct 03 11:41:14 AM UTC 24 |
Oct 03 11:41:27 AM UTC 24 |
534985698 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1965583132 |
|
|
Oct 03 11:40:21 AM UTC 24 |
Oct 03 11:41:29 AM UTC 24 |
2668171397 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2677985048 |
|
|
Oct 03 11:41:23 AM UTC 24 |
Oct 03 11:41:29 AM UTC 24 |
83788847 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2733844009 |
|
|
Oct 03 11:41:25 AM UTC 24 |
Oct 03 11:41:31 AM UTC 24 |
152250881 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3429814175 |
|
|
Oct 03 11:41:16 AM UTC 24 |
Oct 03 11:41:32 AM UTC 24 |
961260111 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.3215258975 |
|
|
Oct 03 11:41:13 AM UTC 24 |
Oct 03 11:41:32 AM UTC 24 |
1640726510 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2231020293 |
|
|
Oct 03 11:41:30 AM UTC 24 |
Oct 03 11:41:32 AM UTC 24 |
83339897 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3455015385 |
|
|
Oct 03 11:41:22 AM UTC 24 |
Oct 03 11:41:33 AM UTC 24 |
167685008 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.1262583695 |
|
|
Oct 03 11:41:30 AM UTC 24 |
Oct 03 11:41:33 AM UTC 24 |
47268414 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.3248616838 |
|
|
Oct 03 11:40:58 AM UTC 24 |
Oct 03 11:41:34 AM UTC 24 |
255918458 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2763040155 |
|
|
Oct 03 11:41:23 AM UTC 24 |
Oct 03 11:41:35 AM UTC 24 |
302518657 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4029260876 |
|
|
Oct 03 11:41:32 AM UTC 24 |
Oct 03 11:41:35 AM UTC 24 |
43357208 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.679591777 |
|
|
Oct 03 11:41:16 AM UTC 24 |
Oct 03 11:41:36 AM UTC 24 |
352990598 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.113271688 |
|
|
Oct 03 11:40:51 AM UTC 24 |
Oct 03 11:41:38 AM UTC 24 |
5199366776 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.374747508 |
|
|
Oct 03 11:42:10 AM UTC 24 |
Oct 03 11:42:26 AM UTC 24 |
311347652 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2308815667 |
|
|
Oct 03 11:41:34 AM UTC 24 |
Oct 03 11:41:39 AM UTC 24 |
38040619 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.3467679251 |
|
|
Oct 03 11:41:26 AM UTC 24 |
Oct 03 11:41:40 AM UTC 24 |
281963732 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.580042988 |
|
|
Oct 03 11:41:40 AM UTC 24 |
Oct 03 11:41:42 AM UTC 24 |
14501722 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.2812592021 |
|
|
Oct 03 11:41:25 AM UTC 24 |
Oct 03 11:41:42 AM UTC 24 |
667994340 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.4096684304 |
|
|
Oct 03 11:41:25 AM UTC 24 |
Oct 03 11:41:43 AM UTC 24 |
1488855929 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.2530194145 |
|
|
Oct 03 11:41:34 AM UTC 24 |
Oct 03 11:41:43 AM UTC 24 |
313903408 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2208739464 |
|
|
Oct 03 11:40:51 AM UTC 24 |
Oct 03 11:41:44 AM UTC 24 |
1457291913 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1677239364 |
|
|
Oct 03 11:41:43 AM UTC 24 |
Oct 03 11:41:45 AM UTC 24 |
40506744 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3765385282 |
|
|
Oct 03 11:40:54 AM UTC 24 |
Oct 03 11:41:46 AM UTC 24 |
2612537028 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.3040297059 |
|
|
Oct 03 11:41:41 AM UTC 24 |
Oct 03 11:41:47 AM UTC 24 |
198185158 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.225433034 |
|
|
Oct 03 11:41:27 AM UTC 24 |
Oct 03 11:41:47 AM UTC 24 |
463454311 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.2387868903 |
|
|
Oct 03 11:41:34 AM UTC 24 |
Oct 03 11:41:47 AM UTC 24 |
241639558 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3715012167 |
|
|
Oct 03 11:41:22 AM UTC 24 |
Oct 03 11:41:48 AM UTC 24 |
307632778 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.2403970731 |
|
|
Oct 03 11:41:44 AM UTC 24 |
Oct 03 11:41:49 AM UTC 24 |
128276933 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.920635679 |
|
|
Oct 03 11:41:36 AM UTC 24 |
Oct 03 11:41:49 AM UTC 24 |
299244886 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.115453845 |
|
|
Oct 03 11:41:44 AM UTC 24 |
Oct 03 11:41:49 AM UTC 24 |
54585562 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.3141364463 |
|
|
Oct 03 11:41:36 AM UTC 24 |
Oct 03 11:41:51 AM UTC 24 |
2081764659 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.4173495804 |
|
|
Oct 03 11:41:34 AM UTC 24 |
Oct 03 11:41:53 AM UTC 24 |
295095912 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.4174863600 |
|
|
Oct 03 11:41:51 AM UTC 24 |
Oct 03 11:41:53 AM UTC 24 |
193850558 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.3307559371 |
|
|
Oct 03 11:42:11 AM UTC 24 |
Oct 03 11:42:27 AM UTC 24 |
414360532 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.164353901 |
|
|
Oct 03 11:41:11 AM UTC 24 |
Oct 03 11:41:54 AM UTC 24 |
522154187 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.3991308827 |
|
|
Oct 03 11:41:37 AM UTC 24 |
Oct 03 11:41:54 AM UTC 24 |
339488497 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2346241061 |
|
|
Oct 03 11:41:52 AM UTC 24 |
Oct 03 11:41:54 AM UTC 24 |
45124174 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3591087266 |
|
|
Oct 03 11:41:51 AM UTC 24 |
Oct 03 11:41:54 AM UTC 24 |
152587940 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.241930116 |
|
|
Oct 03 11:39:58 AM UTC 24 |
Oct 03 11:41:56 AM UTC 24 |
4215917611 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.1407905967 |
|
|
Oct 03 11:41:47 AM UTC 24 |
Oct 03 11:41:57 AM UTC 24 |
357800253 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3459214976 |
|
|
Oct 03 11:41:46 AM UTC 24 |
Oct 03 11:41:59 AM UTC 24 |
268970884 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.4268595519 |
|
|
Oct 03 11:41:55 AM UTC 24 |
Oct 03 11:41:59 AM UTC 24 |
85714039 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.507374512 |
|
|
Oct 03 11:41:33 AM UTC 24 |
Oct 03 11:42:00 AM UTC 24 |
270501624 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.692646584 |
|
|
Oct 03 11:41:48 AM UTC 24 |
Oct 03 11:42:03 AM UTC 24 |
409410053 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.2204491352 |
|
|
Oct 03 11:41:47 AM UTC 24 |
Oct 03 11:42:03 AM UTC 24 |
347509563 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.262682909 |
|
|
Oct 03 11:41:48 AM UTC 24 |
Oct 03 11:42:04 AM UTC 24 |
1630785927 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2344647109 |
|
|
Oct 03 11:41:48 AM UTC 24 |
Oct 03 11:42:05 AM UTC 24 |
382035585 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.827045977 |
|
|
Oct 03 11:41:36 AM UTC 24 |
Oct 03 11:42:06 AM UTC 24 |
704575364 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.2804294053 |
|
|
Oct 03 11:42:04 AM UTC 24 |
Oct 03 11:42:07 AM UTC 24 |
56771494 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.2376945750 |
|
|
Oct 03 11:41:54 AM UTC 24 |
Oct 03 11:42:07 AM UTC 24 |
161639541 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.3497900248 |
|
|
Oct 03 11:41:04 AM UTC 24 |
Oct 03 11:42:07 AM UTC 24 |
7217422646 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.389095532 |
|
|
Oct 03 11:41:55 AM UTC 24 |
Oct 03 11:42:08 AM UTC 24 |
1088720172 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.250901739 |
|
|
Oct 03 11:42:06 AM UTC 24 |
Oct 03 11:42:08 AM UTC 24 |
19363400 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.600174736 |
|
|
Oct 03 11:41:56 AM UTC 24 |
Oct 03 11:42:09 AM UTC 24 |
5731138373 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.1103524904 |
|
|
Oct 03 11:42:05 AM UTC 24 |
Oct 03 11:42:10 AM UTC 24 |
133153562 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.1679450035 |
|
|
Oct 03 11:42:08 AM UTC 24 |
Oct 03 11:42:12 AM UTC 24 |
23907398 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3706424116 |
|
|
Oct 03 11:41:57 AM UTC 24 |
Oct 03 11:42:12 AM UTC 24 |
1378743443 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3723881737 |
|
|
Oct 03 11:41:58 AM UTC 24 |
Oct 03 11:42:12 AM UTC 24 |
1471130430 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.2524577867 |
|
|
Oct 03 11:42:00 AM UTC 24 |
Oct 03 11:42:14 AM UTC 24 |
992431608 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3121302752 |
|
|
Oct 03 11:42:07 AM UTC 24 |
Oct 03 11:42:16 AM UTC 24 |
506663217 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1640270928 |
|
|
Oct 03 11:42:13 AM UTC 24 |
Oct 03 11:42:16 AM UTC 24 |
20563020 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3213380876 |
|
|
Oct 03 11:42:13 AM UTC 24 |
Oct 03 11:42:17 AM UTC 24 |
186406840 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1465789335 |
|
|
Oct 03 11:42:14 AM UTC 24 |
Oct 03 11:42:17 AM UTC 24 |
14714438 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.3852025440 |
|
|
Oct 03 11:41:54 AM UTC 24 |
Oct 03 11:42:17 AM UTC 24 |
1797630833 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.877569546 |
|
|
Oct 03 11:41:01 AM UTC 24 |
Oct 03 11:42:18 AM UTC 24 |
6021815933 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.273133103 |
|
|
Oct 03 11:40:38 AM UTC 24 |
Oct 03 11:42:18 AM UTC 24 |
3197081655 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.3018150908 |
|
|
Oct 03 11:42:11 AM UTC 24 |
Oct 03 11:42:19 AM UTC 24 |
310623777 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.2180268238 |
|
|
Oct 03 11:42:10 AM UTC 24 |
Oct 03 11:42:20 AM UTC 24 |
838931926 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.3113212951 |
|
|
Oct 03 11:41:43 AM UTC 24 |
Oct 03 11:42:20 AM UTC 24 |
505977854 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3875794601 |
|
|
Oct 03 11:40:29 AM UTC 24 |
Oct 03 11:42:20 AM UTC 24 |
16647582485 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.2236239816 |
|
|
Oct 03 11:42:18 AM UTC 24 |
Oct 03 11:42:21 AM UTC 24 |
20542950 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.1102335676 |
|
|
Oct 03 11:42:08 AM UTC 24 |
Oct 03 11:42:22 AM UTC 24 |
228142635 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2131482880 |
|
|
Oct 03 11:42:22 AM UTC 24 |
Oct 03 11:42:25 AM UTC 24 |
28098979 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.102053873 |
|
|
Oct 03 11:41:55 AM UTC 24 |
Oct 03 11:42:25 AM UTC 24 |
685470719 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.2477552608 |
|
|
Oct 03 11:42:08 AM UTC 24 |
Oct 03 11:42:25 AM UTC 24 |
332131559 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2943719686 |
|
|
Oct 03 11:42:24 AM UTC 24 |
Oct 03 11:42:26 AM UTC 24 |
16979628 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1196802141 |
|
|
Oct 03 11:42:19 AM UTC 24 |
Oct 03 11:42:28 AM UTC 24 |
2046438887 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1054668608 |
|
|
Oct 03 11:41:40 AM UTC 24 |
Oct 03 11:42:27 AM UTC 24 |
5613679231 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.3083030997 |
|
|
Oct 03 11:42:18 AM UTC 24 |
Oct 03 11:42:28 AM UTC 24 |
635526330 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2260744242 |
|
|
Oct 03 11:42:06 AM UTC 24 |
Oct 03 11:42:29 AM UTC 24 |
188986787 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.965745470 |
|
|
Oct 03 11:42:17 AM UTC 24 |
Oct 03 11:42:30 AM UTC 24 |
102879688 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.482465545 |
|
|
Oct 03 11:40:55 AM UTC 24 |
Oct 03 11:42:30 AM UTC 24 |
2051992642 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.704490636 |
|
|
Oct 03 11:42:21 AM UTC 24 |
Oct 03 11:42:32 AM UTC 24 |
628973504 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3313244851 |
|
|
Oct 03 11:42:24 AM UTC 24 |
Oct 03 11:42:32 AM UTC 24 |
538914531 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.1728591470 |
|
|
Oct 03 11:42:27 AM UTC 24 |
Oct 03 11:42:32 AM UTC 24 |
71228794 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.447963578 |
|
|
Oct 03 11:42:32 AM UTC 24 |
Oct 03 11:42:34 AM UTC 24 |
39965991 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.1006010872 |
|
|
Oct 03 11:42:21 AM UTC 24 |
Oct 03 11:42:34 AM UTC 24 |
490382864 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1225210221 |
|
|
Oct 03 11:42:18 AM UTC 24 |
Oct 03 11:42:35 AM UTC 24 |
300524182 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.1527127601 |
|
|
Oct 03 11:42:33 AM UTC 24 |
Oct 03 11:42:35 AM UTC 24 |
18619907 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1142010948 |
|
|
Oct 03 11:42:33 AM UTC 24 |
Oct 03 11:42:35 AM UTC 24 |
13231411 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.1901904202 |
|
|
Oct 03 11:42:19 AM UTC 24 |
Oct 03 11:42:37 AM UTC 24 |
2225900625 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.674896009 |
|
|
Oct 03 11:42:35 AM UTC 24 |
Oct 03 11:42:39 AM UTC 24 |
250827108 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.3167496316 |
|
|
Oct 03 11:42:29 AM UTC 24 |
Oct 03 11:42:40 AM UTC 24 |
986820801 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.3048167472 |
|
|
Oct 03 11:42:27 AM UTC 24 |
Oct 03 11:42:40 AM UTC 24 |
335427184 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1460887476 |
|
|
Oct 03 11:42:29 AM UTC 24 |
Oct 03 11:42:41 AM UTC 24 |
1297266441 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.971321543 |
|
|
Oct 03 11:38:57 AM UTC 24 |
Oct 03 11:42:43 AM UTC 24 |
17568239895 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1366586194 |
|
|
Oct 03 11:37:16 AM UTC 24 |
Oct 03 11:42:44 AM UTC 24 |
13717641113 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.522088124 |
|
|
Oct 03 11:42:29 AM UTC 24 |
Oct 03 11:42:44 AM UTC 24 |
243538244 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2006389756 |
|
|
Oct 03 11:42:27 AM UTC 24 |
Oct 03 11:42:44 AM UTC 24 |
557374452 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.3225927219 |
|
|
Oct 03 11:40:44 AM UTC 24 |
Oct 03 11:42:44 AM UTC 24 |
24875151805 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.2021932241 |
|
|
Oct 03 11:42:00 AM UTC 24 |
Oct 03 11:42:45 AM UTC 24 |
1054369316 ps |