| T198 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.3200649675 |
|
|
Oct 03 11:42:35 AM UTC 24 |
Oct 03 11:42:46 AM UTC 24 |
467137208 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.465265133 |
|
|
Oct 03 11:42:17 AM UTC 24 |
Oct 03 11:42:46 AM UTC 24 |
739012315 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2687279985 |
|
|
Oct 03 11:41:17 AM UTC 24 |
Oct 03 11:42:46 AM UTC 24 |
3665668829 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.3748765528 |
|
|
Oct 03 11:42:44 AM UTC 24 |
Oct 03 11:42:46 AM UTC 24 |
277019623 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3134316118 |
|
|
Oct 03 11:42:36 AM UTC 24 |
Oct 03 11:42:47 AM UTC 24 |
460527097 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3634521583 |
|
|
Oct 03 11:42:45 AM UTC 24 |
Oct 03 11:42:47 AM UTC 24 |
29930217 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1069152494 |
|
|
Oct 03 11:42:29 AM UTC 24 |
Oct 03 11:42:49 AM UTC 24 |
1199008524 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.1617046949 |
|
|
Oct 03 11:42:45 AM UTC 24 |
Oct 03 11:42:50 AM UTC 24 |
35957934 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2301521487 |
|
|
Oct 03 11:42:47 AM UTC 24 |
Oct 03 11:42:50 AM UTC 24 |
19282411 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2704692025 |
|
|
Oct 03 11:37:47 AM UTC 24 |
Oct 03 11:42:51 AM UTC 24 |
13227205532 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.3508360029 |
|
|
Oct 03 11:43:10 AM UTC 24 |
Oct 03 11:43:17 AM UTC 24 |
379519134 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.3785035160 |
|
|
Oct 03 11:43:05 AM UTC 24 |
Oct 03 11:43:18 AM UTC 24 |
1152641722 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1324461175 |
|
|
Oct 03 11:42:36 AM UTC 24 |
Oct 03 11:42:53 AM UTC 24 |
1502695697 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.719590309 |
|
|
Oct 03 11:42:40 AM UTC 24 |
Oct 03 11:42:53 AM UTC 24 |
302021038 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.1408796796 |
|
|
Oct 03 11:42:51 AM UTC 24 |
Oct 03 11:42:53 AM UTC 24 |
27591540 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.262619910 |
|
|
Oct 03 11:42:26 AM UTC 24 |
Oct 03 11:42:54 AM UTC 24 |
973105987 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.431165202 |
|
|
Oct 03 11:42:27 AM UTC 24 |
Oct 03 11:42:54 AM UTC 24 |
3735275265 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.1336077664 |
|
|
Oct 03 11:42:52 AM UTC 24 |
Oct 03 11:42:55 AM UTC 24 |
119405594 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3793578373 |
|
|
Oct 03 11:42:53 AM UTC 24 |
Oct 03 11:42:56 AM UTC 24 |
153106373 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.4132451860 |
|
|
Oct 03 11:43:12 AM UTC 24 |
Oct 03 11:43:18 AM UTC 24 |
405694997 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.551487721 |
|
|
Oct 03 11:41:16 AM UTC 24 |
Oct 03 11:42:56 AM UTC 24 |
17800407798 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.3659180859 |
|
|
Oct 03 11:42:36 AM UTC 24 |
Oct 03 11:42:56 AM UTC 24 |
508660192 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1082359579 |
|
|
Oct 03 11:42:46 AM UTC 24 |
Oct 03 11:42:56 AM UTC 24 |
329383235 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.2900038361 |
|
|
Oct 03 11:42:55 AM UTC 24 |
Oct 03 11:42:58 AM UTC 24 |
97543639 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3904533434 |
|
|
Oct 03 11:42:48 AM UTC 24 |
Oct 03 11:42:59 AM UTC 24 |
951102022 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1250396103 |
|
|
Oct 03 11:42:47 AM UTC 24 |
Oct 03 11:42:59 AM UTC 24 |
1079021701 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.1139796691 |
|
|
Oct 03 11:42:38 AM UTC 24 |
Oct 03 11:42:59 AM UTC 24 |
4592775851 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.4263742465 |
|
|
Oct 03 11:42:41 AM UTC 24 |
Oct 03 11:43:00 AM UTC 24 |
1469761437 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.1583974314 |
|
|
Oct 03 11:42:33 AM UTC 24 |
Oct 03 11:43:01 AM UTC 24 |
2380986234 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.2668251206 |
|
|
Oct 03 11:42:48 AM UTC 24 |
Oct 03 11:43:02 AM UTC 24 |
220248434 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.3831302789 |
|
|
Oct 03 11:42:54 AM UTC 24 |
Oct 03 11:43:02 AM UTC 24 |
98712082 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.172778864 |
|
|
Oct 03 11:43:00 AM UTC 24 |
Oct 03 11:43:02 AM UTC 24 |
28910103 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2045926655 |
|
|
Oct 03 11:42:31 AM UTC 24 |
Oct 03 11:43:03 AM UTC 24 |
2384559476 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.2416167174 |
|
|
Oct 03 11:42:48 AM UTC 24 |
Oct 03 11:43:03 AM UTC 24 |
293585231 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.8352110 |
|
|
Oct 03 11:42:45 AM UTC 24 |
Oct 03 11:43:03 AM UTC 24 |
733641681 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.618601031 |
|
|
Oct 03 11:42:56 AM UTC 24 |
Oct 03 11:43:04 AM UTC 24 |
1407371049 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.3890166326 |
|
|
Oct 03 11:42:48 AM UTC 24 |
Oct 03 11:43:04 AM UTC 24 |
985865655 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.4216317894 |
|
|
Oct 03 11:43:01 AM UTC 24 |
Oct 03 11:43:04 AM UTC 24 |
25235014 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.4152689349 |
|
|
Oct 03 11:41:29 AM UTC 24 |
Oct 03 11:43:05 AM UTC 24 |
4388119373 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.3411680091 |
|
|
Oct 03 11:43:00 AM UTC 24 |
Oct 03 11:43:05 AM UTC 24 |
58775142 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.3897326023 |
|
|
Oct 03 11:39:50 AM UTC 24 |
Oct 03 11:43:07 AM UTC 24 |
5128671776 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.3177223805 |
|
|
Oct 03 11:43:02 AM UTC 24 |
Oct 03 11:43:07 AM UTC 24 |
253977831 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1193511315 |
|
|
Oct 03 11:43:04 AM UTC 24 |
Oct 03 11:43:09 AM UTC 24 |
696509997 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.1442561161 |
|
|
Oct 03 11:43:07 AM UTC 24 |
Oct 03 11:43:09 AM UTC 24 |
24076572 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2617592049 |
|
|
Oct 03 11:42:56 AM UTC 24 |
Oct 03 11:43:10 AM UTC 24 |
1444847722 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.2069320027 |
|
|
Oct 03 11:42:56 AM UTC 24 |
Oct 03 11:43:10 AM UTC 24 |
240527702 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.560125796 |
|
|
Oct 03 11:43:04 AM UTC 24 |
Oct 03 11:43:10 AM UTC 24 |
377041928 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.755354759 |
|
|
Oct 03 11:42:57 AM UTC 24 |
Oct 03 11:43:10 AM UTC 24 |
545087232 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2013872535 |
|
|
Oct 03 11:43:08 AM UTC 24 |
Oct 03 11:43:11 AM UTC 24 |
48842342 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3877015795 |
|
|
Oct 03 11:43:07 AM UTC 24 |
Oct 03 11:43:11 AM UTC 24 |
140996584 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3675099696 |
|
|
Oct 03 11:42:47 AM UTC 24 |
Oct 03 11:43:13 AM UTC 24 |
677890723 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.2590627005 |
|
|
Oct 03 11:42:57 AM UTC 24 |
Oct 03 11:43:15 AM UTC 24 |
1159197797 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.1376852673 |
|
|
Oct 03 11:42:53 AM UTC 24 |
Oct 03 11:43:16 AM UTC 24 |
855089416 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3298933217 |
|
|
Oct 03 11:42:57 AM UTC 24 |
Oct 03 11:43:17 AM UTC 24 |
324938646 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.4131309086 |
|
|
Oct 03 11:43:10 AM UTC 24 |
Oct 03 11:43:18 AM UTC 24 |
138689190 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.3385498590 |
|
|
Oct 03 11:43:17 AM UTC 24 |
Oct 03 11:43:19 AM UTC 24 |
15943719 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.762781856 |
|
|
Oct 03 11:43:05 AM UTC 24 |
Oct 03 11:43:19 AM UTC 24 |
278179423 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.82880002 |
|
|
Oct 03 11:43:05 AM UTC 24 |
Oct 03 11:43:20 AM UTC 24 |
1916352021 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.3110632849 |
|
|
Oct 03 11:43:04 AM UTC 24 |
Oct 03 11:43:21 AM UTC 24 |
823259127 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3461258346 |
|
|
Oct 03 11:43:18 AM UTC 24 |
Oct 03 11:43:21 AM UTC 24 |
12499375 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.99355757 |
|
|
Oct 03 11:43:18 AM UTC 24 |
Oct 03 11:43:22 AM UTC 24 |
103760493 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3517295699 |
|
|
Oct 03 11:43:12 AM UTC 24 |
Oct 03 11:43:23 AM UTC 24 |
385794456 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.3784384425 |
|
|
Oct 03 11:43:19 AM UTC 24 |
Oct 03 11:43:24 AM UTC 24 |
134380729 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.901757419 |
|
|
Oct 03 11:43:12 AM UTC 24 |
Oct 03 11:43:25 AM UTC 24 |
251655753 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.553093847 |
|
|
Oct 03 11:43:21 AM UTC 24 |
Oct 03 11:43:25 AM UTC 24 |
83074322 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1103601328 |
|
|
Oct 03 11:43:04 AM UTC 24 |
Oct 03 11:43:26 AM UTC 24 |
390299845 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.995202878 |
|
|
Oct 03 11:43:24 AM UTC 24 |
Oct 03 11:43:27 AM UTC 24 |
37690099 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.2365323504 |
|
|
Oct 03 11:43:08 AM UTC 24 |
Oct 03 11:43:27 AM UTC 24 |
276592735 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.1328173347 |
|
|
Oct 03 11:43:26 AM UTC 24 |
Oct 03 11:43:28 AM UTC 24 |
20207594 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2188476978 |
|
|
Oct 03 11:43:19 AM UTC 24 |
Oct 03 11:43:28 AM UTC 24 |
64761449 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.4146803947 |
|
|
Oct 03 11:43:26 AM UTC 24 |
Oct 03 11:43:28 AM UTC 24 |
34842489 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.2809450465 |
|
|
Oct 03 11:41:38 AM UTC 24 |
Oct 03 11:43:30 AM UTC 24 |
17866956331 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_errors.2902322719 |
|
|
Oct 03 11:43:10 AM UTC 24 |
Oct 03 11:43:30 AM UTC 24 |
2888633819 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2351043263 |
|
|
Oct 03 11:43:19 AM UTC 24 |
Oct 03 11:43:31 AM UTC 24 |
726193680 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.293974231 |
|
|
Oct 03 11:43:21 AM UTC 24 |
Oct 03 11:43:32 AM UTC 24 |
533893866 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3245280113 |
|
|
Oct 03 11:43:28 AM UTC 24 |
Oct 03 11:43:33 AM UTC 24 |
282557848 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.2424732064 |
|
|
Oct 03 11:42:11 AM UTC 24 |
Oct 03 11:43:33 AM UTC 24 |
7713046681 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.3968240380 |
|
|
Oct 03 11:43:29 AM UTC 24 |
Oct 03 11:43:33 AM UTC 24 |
189566655 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.2292994134 |
|
|
Oct 03 11:44:04 AM UTC 24 |
Oct 03 11:44:07 AM UTC 24 |
71283673 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1196968888 |
|
|
Oct 03 11:43:22 AM UTC 24 |
Oct 03 11:43:34 AM UTC 24 |
2801089774 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3097835699 |
|
|
Oct 03 11:43:12 AM UTC 24 |
Oct 03 11:43:34 AM UTC 24 |
1658234722 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.340720114 |
|
|
Oct 03 11:43:01 AM UTC 24 |
Oct 03 11:43:36 AM UTC 24 |
1761396150 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1806149217 |
|
|
Oct 03 11:43:34 AM UTC 24 |
Oct 03 11:43:36 AM UTC 24 |
38946905 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2993051531 |
|
|
Oct 03 11:43:34 AM UTC 24 |
Oct 03 11:43:37 AM UTC 24 |
30392010 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3841459975 |
|
|
Oct 03 11:43:34 AM UTC 24 |
Oct 03 11:43:37 AM UTC 24 |
78192228 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.2527124462 |
|
|
Oct 03 11:40:04 AM UTC 24 |
Oct 03 11:43:38 AM UTC 24 |
84570420318 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2188896918 |
|
|
Oct 03 11:43:29 AM UTC 24 |
Oct 03 11:43:39 AM UTC 24 |
709612147 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.626036315 |
|
|
Oct 03 11:43:27 AM UTC 24 |
Oct 03 11:43:40 AM UTC 24 |
46187694 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2373290178 |
|
|
Oct 03 11:43:28 AM UTC 24 |
Oct 03 11:43:40 AM UTC 24 |
1264099415 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.3232446562 |
|
|
Oct 03 11:43:12 AM UTC 24 |
Oct 03 11:43:41 AM UTC 24 |
2866331501 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2024102379 |
|
|
Oct 03 11:43:22 AM UTC 24 |
Oct 03 11:43:41 AM UTC 24 |
1319043673 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2430717233 |
|
|
Oct 03 11:43:36 AM UTC 24 |
Oct 03 11:43:42 AM UTC 24 |
360191241 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.935102751 |
|
|
Oct 03 11:43:41 AM UTC 24 |
Oct 03 11:43:44 AM UTC 24 |
75701038 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.527364005 |
|
|
Oct 03 11:43:41 AM UTC 24 |
Oct 03 11:43:44 AM UTC 24 |
28915069 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2160402082 |
|
|
Oct 03 11:43:43 AM UTC 24 |
Oct 03 11:43:45 AM UTC 24 |
45973798 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.3371230439 |
|
|
Oct 03 11:43:32 AM UTC 24 |
Oct 03 11:43:45 AM UTC 24 |
1620242661 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3710542267 |
|
|
Oct 03 11:43:22 AM UTC 24 |
Oct 03 11:43:45 AM UTC 24 |
4535836984 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2519260957 |
|
|
Oct 03 11:41:49 AM UTC 24 |
Oct 03 11:43:46 AM UTC 24 |
11003132380 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.33545164 |
|
|
Oct 03 11:43:35 AM UTC 24 |
Oct 03 11:43:46 AM UTC 24 |
101194050 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.4040433103 |
|
|
Oct 03 11:42:30 AM UTC 24 |
Oct 03 11:43:47 AM UTC 24 |
44911758568 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.940954456 |
|
|
Oct 03 11:44:05 AM UTC 24 |
Oct 03 11:44:07 AM UTC 24 |
14608976 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.1704848882 |
|
|
Oct 03 11:43:32 AM UTC 24 |
Oct 03 11:43:48 AM UTC 24 |
1198841777 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3638636354 |
|
|
Oct 03 11:43:19 AM UTC 24 |
Oct 03 11:43:48 AM UTC 24 |
216425414 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2010728732 |
|
|
Oct 03 11:43:37 AM UTC 24 |
Oct 03 11:43:48 AM UTC 24 |
1104607206 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.1476613363 |
|
|
Oct 03 11:43:45 AM UTC 24 |
Oct 03 11:43:50 AM UTC 24 |
169644929 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.549811950 |
|
|
Oct 03 11:38:30 AM UTC 24 |
Oct 03 11:43:50 AM UTC 24 |
9402405670 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.1458669137 |
|
|
Oct 03 11:43:40 AM UTC 24 |
Oct 03 11:43:52 AM UTC 24 |
771248977 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.3088602839 |
|
|
Oct 03 11:43:50 AM UTC 24 |
Oct 03 11:43:52 AM UTC 24 |
58176047 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.580365030 |
|
|
Oct 03 11:43:38 AM UTC 24 |
Oct 03 11:43:52 AM UTC 24 |
1344714507 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3418655942 |
|
|
Oct 03 11:43:50 AM UTC 24 |
Oct 03 11:43:52 AM UTC 24 |
29089426 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.4079771667 |
|
|
Oct 03 11:43:29 AM UTC 24 |
Oct 03 11:43:53 AM UTC 24 |
1725384940 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.614162482 |
|
|
Oct 03 11:43:44 AM UTC 24 |
Oct 03 11:43:54 AM UTC 24 |
310016137 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2475306737 |
|
|
Oct 03 11:43:50 AM UTC 24 |
Oct 03 11:43:54 AM UTC 24 |
164424319 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.787581787 |
|
|
Oct 03 11:43:38 AM UTC 24 |
Oct 03 11:43:55 AM UTC 24 |
639128021 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.1310844335 |
|
|
Oct 03 11:43:46 AM UTC 24 |
Oct 03 11:43:56 AM UTC 24 |
579169365 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.3747590747 |
|
|
Oct 03 11:43:52 AM UTC 24 |
Oct 03 11:43:56 AM UTC 24 |
54680749 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3682783953 |
|
|
Oct 03 11:43:34 AM UTC 24 |
Oct 03 11:43:56 AM UTC 24 |
557656828 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1974839445 |
|
|
Oct 03 11:43:46 AM UTC 24 |
Oct 03 11:43:57 AM UTC 24 |
413265722 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3682751062 |
|
|
Oct 03 11:43:37 AM UTC 24 |
Oct 03 11:43:58 AM UTC 24 |
3325291444 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.969908887 |
|
|
Oct 03 11:43:54 AM UTC 24 |
Oct 03 11:43:58 AM UTC 24 |
1065376729 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.842850094 |
|
|
Oct 03 11:43:53 AM UTC 24 |
Oct 03 11:43:58 AM UTC 24 |
66181115 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1261550893 |
|
|
Oct 03 11:43:36 AM UTC 24 |
Oct 03 11:43:58 AM UTC 24 |
6353487439 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3964878874 |
|
|
Oct 03 11:43:45 AM UTC 24 |
Oct 03 11:43:59 AM UTC 24 |
459716154 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.4219142505 |
|
|
Oct 03 11:43:27 AM UTC 24 |
Oct 03 11:44:00 AM UTC 24 |
1230873799 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.1023342432 |
|
|
Oct 03 11:43:58 AM UTC 24 |
Oct 03 11:44:01 AM UTC 24 |
263070428 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3094309140 |
|
|
Oct 03 11:43:59 AM UTC 24 |
Oct 03 11:44:01 AM UTC 24 |
26228144 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.4114732949 |
|
|
Oct 03 11:43:59 AM UTC 24 |
Oct 03 11:44:05 AM UTC 24 |
81999824 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.2958951952 |
|
|
Oct 03 11:43:54 AM UTC 24 |
Oct 03 11:44:06 AM UTC 24 |
886956663 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.957182330 |
|
|
Oct 03 11:43:48 AM UTC 24 |
Oct 03 11:44:02 AM UTC 24 |
318709308 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3278688110 |
|
|
Oct 03 11:41:29 AM UTC 24 |
Oct 03 11:44:09 AM UTC 24 |
36061182569 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.4251188815 |
|
|
Oct 03 11:43:17 AM UTC 24 |
Oct 03 11:44:03 AM UTC 24 |
941637828 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.129797616 |
|
|
Oct 03 11:43:46 AM UTC 24 |
Oct 03 11:44:03 AM UTC 24 |
309239779 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.1896166310 |
|
|
Oct 03 11:44:01 AM UTC 24 |
Oct 03 11:44:04 AM UTC 24 |
16411331 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.546371447 |
|
|
Oct 03 11:43:48 AM UTC 24 |
Oct 03 11:44:05 AM UTC 24 |
386205444 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.1043728874 |
|
|
Oct 03 11:43:59 AM UTC 24 |
Oct 03 11:44:05 AM UTC 24 |
81314538 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3028544284 |
|
|
Oct 03 11:43:56 AM UTC 24 |
Oct 03 11:44:10 AM UTC 24 |
1416008724 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.846450417 |
|
|
Oct 03 11:44:05 AM UTC 24 |
Oct 03 11:44:11 AM UTC 24 |
199253713 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.987845538 |
|
|
Oct 03 11:41:10 AM UTC 24 |
Oct 03 11:44:11 AM UTC 24 |
15135019116 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.2365932436 |
|
|
Oct 03 11:43:56 AM UTC 24 |
Oct 03 11:44:12 AM UTC 24 |
422977448 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.3533008816 |
|
|
Oct 03 11:44:06 AM UTC 24 |
Oct 03 11:44:12 AM UTC 24 |
95235741 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.190010352 |
|
|
Oct 03 11:43:54 AM UTC 24 |
Oct 03 11:44:13 AM UTC 24 |
989008634 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.2631479656 |
|
|
Oct 03 11:44:07 AM UTC 24 |
Oct 03 11:44:14 AM UTC 24 |
446151947 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.744900653 |
|
|
Oct 03 11:43:56 AM UTC 24 |
Oct 03 11:44:14 AM UTC 24 |
386770077 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.463306144 |
|
|
Oct 03 11:44:12 AM UTC 24 |
Oct 03 11:44:14 AM UTC 24 |
12629476 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.3717592190 |
|
|
Oct 03 11:44:01 AM UTC 24 |
Oct 03 11:44:15 AM UTC 24 |
672890044 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1686779734 |
|
|
Oct 03 11:44:03 AM UTC 24 |
Oct 03 11:44:15 AM UTC 24 |
237269974 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1726425150 |
|
|
Oct 03 11:44:06 AM UTC 24 |
Oct 03 11:44:16 AM UTC 24 |
442325419 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3396440641 |
|
|
Oct 03 11:44:14 AM UTC 24 |
Oct 03 11:44:16 AM UTC 24 |
20999352 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.1277473581 |
|
|
Oct 03 11:43:43 AM UTC 24 |
Oct 03 11:44:17 AM UTC 24 |
343118576 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1804045479 |
|
|
Oct 03 11:44:14 AM UTC 24 |
Oct 03 11:44:18 AM UTC 24 |
31377322 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.852108928 |
|
|
Oct 03 11:44:01 AM UTC 24 |
Oct 03 11:44:18 AM UTC 24 |
1493891287 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.1976072730 |
|
|
Oct 03 11:44:03 AM UTC 24 |
Oct 03 11:44:19 AM UTC 24 |
1653338567 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2731172159 |
|
|
Oct 03 11:44:15 AM UTC 24 |
Oct 03 11:44:20 AM UTC 24 |
154193923 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2421357612 |
|
|
Oct 03 11:44:03 AM UTC 24 |
Oct 03 11:44:21 AM UTC 24 |
701590372 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1241212970 |
|
|
Oct 03 11:44:20 AM UTC 24 |
Oct 03 11:44:22 AM UTC 24 |
43033152 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2285328639 |
|
|
Oct 03 11:44:06 AM UTC 24 |
Oct 03 11:44:23 AM UTC 24 |
2839863379 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2501892937 |
|
|
Oct 03 11:44:02 AM UTC 24 |
Oct 03 11:44:23 AM UTC 24 |
778342987 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1751414154 |
|
|
Oct 03 11:44:21 AM UTC 24 |
Oct 03 11:44:24 AM UTC 24 |
37645065 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2819372979 |
|
|
Oct 03 11:42:50 AM UTC 24 |
Oct 03 11:44:24 AM UTC 24 |
5335710421 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1792707250 |
|
|
Oct 03 11:44:22 AM UTC 24 |
Oct 03 11:44:24 AM UTC 24 |
44232543 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.3492116056 |
|
|
Oct 03 11:44:11 AM UTC 24 |
Oct 03 11:44:25 AM UTC 24 |
541338584 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.464086400 |
|
|
Oct 03 11:44:07 AM UTC 24 |
Oct 03 11:44:26 AM UTC 24 |
322149199 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.4079653110 |
|
|
Oct 03 11:44:06 AM UTC 24 |
Oct 03 11:44:26 AM UTC 24 |
1676177395 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.667407665 |
|
|
Oct 03 11:44:08 AM UTC 24 |
Oct 03 11:44:27 AM UTC 24 |
5991242769 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.3772493710 |
|
|
Oct 03 11:44:19 AM UTC 24 |
Oct 03 11:44:28 AM UTC 24 |
559667706 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2227269225 |
|
|
Oct 03 11:44:15 AM UTC 24 |
Oct 03 11:44:29 AM UTC 24 |
244077206 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.4272730171 |
|
|
Oct 03 11:43:52 AM UTC 24 |
Oct 03 11:44:29 AM UTC 24 |
1303469935 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.820025315 |
|
|
Oct 03 11:44:24 AM UTC 24 |
Oct 03 11:44:29 AM UTC 24 |
56470094 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.2281945224 |
|
|
Oct 03 11:43:59 AM UTC 24 |
Oct 03 11:44:29 AM UTC 24 |
273992843 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.105977180 |
|
|
Oct 03 11:44:16 AM UTC 24 |
Oct 03 11:44:30 AM UTC 24 |
1344777632 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3276581810 |
|
|
Oct 03 11:43:23 AM UTC 24 |
Oct 03 11:44:31 AM UTC 24 |
2094171719 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.696106790 |
|
|
Oct 03 11:44:28 AM UTC 24 |
Oct 03 11:44:31 AM UTC 24 |
36842184 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.4075708930 |
|
|
Oct 03 11:44:25 AM UTC 24 |
Oct 03 11:44:31 AM UTC 24 |
283025476 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.3980119322 |
|
|
Oct 03 11:44:15 AM UTC 24 |
Oct 03 11:44:31 AM UTC 24 |
1262825857 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.205772381 |
|
|
Oct 03 11:44:30 AM UTC 24 |
Oct 03 11:44:32 AM UTC 24 |
47213211 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.1379633805 |
|
|
Oct 03 11:44:17 AM UTC 24 |
Oct 03 11:44:32 AM UTC 24 |
1467122368 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.449125233 |
|
|
Oct 03 11:44:29 AM UTC 24 |
Oct 03 11:44:32 AM UTC 24 |
18987778 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.168322480 |
|
|
Oct 03 11:44:05 AM UTC 24 |
Oct 03 11:44:33 AM UTC 24 |
327969472 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.3700073023 |
|
|
Oct 03 11:44:17 AM UTC 24 |
Oct 03 11:44:35 AM UTC 24 |
228302674 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.760172689 |
|
|
Oct 03 11:44:16 AM UTC 24 |
Oct 03 11:44:36 AM UTC 24 |
1217983672 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.197855651 |
|
|
Oct 03 11:43:56 AM UTC 24 |
Oct 03 11:44:36 AM UTC 24 |
3613209172 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.334100634 |
|
|
Oct 03 11:44:31 AM UTC 24 |
Oct 03 11:44:37 AM UTC 24 |
332093217 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3553005838 |
|
|
Oct 03 11:44:36 AM UTC 24 |
Oct 03 11:44:38 AM UTC 24 |
30067974 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2982783129 |
|
|
Oct 03 11:44:25 AM UTC 24 |
Oct 03 11:44:39 AM UTC 24 |
603736328 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3446635804 |
|
|
Oct 03 11:44:38 AM UTC 24 |
Oct 03 11:44:40 AM UTC 24 |
23804107 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3107034048 |
|
|
Oct 03 11:44:25 AM UTC 24 |
Oct 03 11:44:40 AM UTC 24 |
1524000729 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1535707626 |
|
|
Oct 03 11:44:14 AM UTC 24 |
Oct 03 11:44:40 AM UTC 24 |
394740089 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2662473201 |
|
|
Oct 03 11:44:31 AM UTC 24 |
Oct 03 11:44:41 AM UTC 24 |
137373582 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.2819478778 |
|
|
Oct 03 11:44:25 AM UTC 24 |
Oct 03 11:44:41 AM UTC 24 |
398402793 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.3852262877 |
|
|
Oct 03 11:44:38 AM UTC 24 |
Oct 03 11:44:42 AM UTC 24 |
196259210 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.739861016 |
|
|
Oct 03 11:44:27 AM UTC 24 |
Oct 03 11:44:43 AM UTC 24 |
289751775 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.4190509336 |
|
|
Oct 03 11:44:32 AM UTC 24 |
Oct 03 11:44:43 AM UTC 24 |
2289682261 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2407935694 |
|
|
Oct 03 11:44:27 AM UTC 24 |
Oct 03 11:44:44 AM UTC 24 |
299682999 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3885910655 |
|
|
Oct 03 11:44:33 AM UTC 24 |
Oct 03 11:44:44 AM UTC 24 |
1402661473 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2597460320 |
|
|
Oct 03 11:44:40 AM UTC 24 |
Oct 03 11:44:45 AM UTC 24 |
101626015 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3965111554 |
|
|
Oct 03 11:44:40 AM UTC 24 |
Oct 03 11:44:45 AM UTC 24 |
67818992 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.482477517 |
|
|
Oct 03 11:44:25 AM UTC 24 |
Oct 03 11:44:46 AM UTC 24 |
404524873 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.2059179693 |
|
|
Oct 03 11:44:33 AM UTC 24 |
Oct 03 11:44:48 AM UTC 24 |
1191583792 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.246091372 |
|
|
Oct 03 11:44:44 AM UTC 24 |
Oct 03 11:44:57 AM UTC 24 |
486022855 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.1680291881 |
|
|
Oct 03 11:44:32 AM UTC 24 |
Oct 03 11:44:48 AM UTC 24 |
1860464015 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.1569447513 |
|
|
Oct 03 11:44:45 AM UTC 24 |
Oct 03 11:44:48 AM UTC 24 |
23997420 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.715560375 |
|
|
Oct 03 11:44:52 AM UTC 24 |
Oct 03 11:44:55 AM UTC 24 |
16398760 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.1778262035 |
|
|
Oct 03 11:44:24 AM UTC 24 |
Oct 03 11:44:49 AM UTC 24 |
895171654 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3942945564 |
|
|
Oct 03 11:44:32 AM UTC 24 |
Oct 03 11:44:49 AM UTC 24 |
2685421486 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.4093642409 |
|
|
Oct 03 11:43:14 AM UTC 24 |
Oct 03 11:44:49 AM UTC 24 |
31221913107 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1889808536 |
|
|
Oct 03 11:44:46 AM UTC 24 |
Oct 03 11:44:49 AM UTC 24 |
13976769 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.1867780376 |
|
|
Oct 03 11:44:41 AM UTC 24 |
Oct 03 11:44:50 AM UTC 24 |
2566211214 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.4087142910 |
|
|
Oct 03 11:44:45 AM UTC 24 |
Oct 03 11:44:51 AM UTC 24 |
131325668 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1999393801 |
|
|
Oct 03 11:44:42 AM UTC 24 |
Oct 03 11:44:51 AM UTC 24 |
949994996 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1877783702 |
|
|
Oct 03 11:44:32 AM UTC 24 |
Oct 03 11:44:51 AM UTC 24 |
391959916 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.1186117129 |
|
|
Oct 03 11:44:47 AM UTC 24 |
Oct 03 11:44:51 AM UTC 24 |
290075673 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1907455494 |
|
|
Oct 03 11:44:41 AM UTC 24 |
Oct 03 11:44:52 AM UTC 24 |
2181859640 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1409296601 |
|
|
Oct 03 11:44:52 AM UTC 24 |
Oct 03 11:44:58 AM UTC 24 |
129217599 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.2880781765 |
|
|
Oct 03 11:44:49 AM UTC 24 |
Oct 03 11:44:52 AM UTC 24 |
90447840 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.2207933653 |
|
|
Oct 03 11:44:34 AM UTC 24 |
Oct 03 11:44:53 AM UTC 24 |
2843588951 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2875431169 |
|
|
Oct 03 11:39:35 AM UTC 24 |
Oct 03 11:44:53 AM UTC 24 |
24488753073 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.1166916950 |
|
|
Oct 03 11:44:52 AM UTC 24 |
Oct 03 11:44:55 AM UTC 24 |
20423429 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1947851630 |
|
|
Oct 03 11:44:54 AM UTC 24 |
Oct 03 11:44:58 AM UTC 24 |
288374931 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.2468179242 |
|
|
Oct 03 11:39:22 AM UTC 24 |
Oct 03 11:46:17 AM UTC 24 |
12669509389 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1444542454 |
|
|
Oct 03 11:45:22 AM UTC 24 |
Oct 03 11:47:01 AM UTC 24 |
2266965779 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3014631393 |
|
|
Oct 03 11:44:42 AM UTC 24 |
Oct 03 11:44:59 AM UTC 24 |
531370172 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3606336194 |
|
|
Oct 03 11:44:55 AM UTC 24 |
Oct 03 11:45:01 AM UTC 24 |
701600502 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.150575686 |
|
|
Oct 03 11:44:53 AM UTC 24 |
Oct 03 11:45:01 AM UTC 24 |
173554178 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.1784085010 |
|
|
Oct 03 11:44:59 AM UTC 24 |
Oct 03 11:45:02 AM UTC 24 |
57384971 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2384740240 |
|
|
Oct 03 11:44:51 AM UTC 24 |
Oct 03 11:45:02 AM UTC 24 |
300877901 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1648074043 |
|
|
Oct 03 11:44:41 AM UTC 24 |
Oct 03 11:45:02 AM UTC 24 |
1203861845 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2657791054 |
|
|
Oct 03 11:44:51 AM UTC 24 |
Oct 03 11:45:02 AM UTC 24 |
1130479510 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.797702200 |
|
|
Oct 03 11:44:31 AM UTC 24 |
Oct 03 11:45:04 AM UTC 24 |
1138232322 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.4294713967 |
|
|
Oct 03 11:43:40 AM UTC 24 |
Oct 03 11:45:05 AM UTC 24 |
3840831387 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.1256146919 |
|
|
Oct 03 11:44:55 AM UTC 24 |
Oct 03 11:45:05 AM UTC 24 |
3783437479 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.246135897 |
|
|
Oct 03 11:45:03 AM UTC 24 |
Oct 03 11:45:05 AM UTC 24 |
26194206 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.607900485 |
|
|
Oct 03 11:45:01 AM UTC 24 |
Oct 03 11:45:05 AM UTC 24 |
77870452 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.18905384 |
|
|
Oct 03 11:44:44 AM UTC 24 |
Oct 03 11:46:46 AM UTC 24 |
20772219927 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.497738367 |
|
|
Oct 03 11:44:38 AM UTC 24 |
Oct 03 11:45:06 AM UTC 24 |
737261422 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.729135657 |
|
|
Oct 03 11:45:03 AM UTC 24 |
Oct 03 11:45:06 AM UTC 24 |
20760585 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2698151280 |
|
|
Oct 03 11:45:03 AM UTC 24 |
Oct 03 11:45:08 AM UTC 24 |
86256696 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.4175278777 |
|
|
Oct 03 11:44:51 AM UTC 24 |
Oct 03 11:45:08 AM UTC 24 |
1849791083 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.2681485503 |
|
|
Oct 03 11:44:58 AM UTC 24 |
Oct 03 11:45:09 AM UTC 24 |
210526491 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.1498463216 |
|
|
Oct 03 11:44:54 AM UTC 24 |
Oct 03 11:45:09 AM UTC 24 |
352154374 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.4084244154 |
|
|
Oct 03 11:45:07 AM UTC 24 |
Oct 03 11:45:09 AM UTC 24 |
33425709 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.3601343656 |
|
|
Oct 03 11:44:51 AM UTC 24 |
Oct 03 11:45:10 AM UTC 24 |
2883244989 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1928529568 |
|
|
Oct 03 11:45:09 AM UTC 24 |
Oct 03 11:45:11 AM UTC 24 |
32707956 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.4157846624 |
|
|
Oct 03 11:44:12 AM UTC 24 |
Oct 03 11:47:14 AM UTC 24 |
13981195834 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.4061391794 |
|
|
Oct 03 11:44:57 AM UTC 24 |
Oct 03 11:45:12 AM UTC 24 |
343186206 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3684455194 |
|
|
Oct 03 11:44:49 AM UTC 24 |
Oct 03 11:45:13 AM UTC 24 |
685178520 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.3157544791 |
|
|
Oct 03 11:45:08 AM UTC 24 |
Oct 03 11:45:13 AM UTC 24 |
329517361 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1820388546 |
|
|
Oct 03 11:45:05 AM UTC 24 |
Oct 03 11:45:14 AM UTC 24 |
900758714 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.4269100846 |
|
|
Oct 03 11:44:46 AM UTC 24 |
Oct 03 11:45:14 AM UTC 24 |
374290840 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.1108209686 |
|
|
Oct 03 11:45:11 AM UTC 24 |
Oct 03 11:45:16 AM UTC 24 |
59796735 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2566009925 |
|
|
Oct 03 11:45:03 AM UTC 24 |
Oct 03 11:45:16 AM UTC 24 |
1312647064 ps |