Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	922628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1106360

1

T1

12

T2

57

T4

134

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1744738	1			T1	5		T2	63		T3	2
values[0x0]	141738	1			T1	8		T2	13		T3	1
values[0x1]	142512	1			T1	7		T2	12		T4	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	730558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1298430

1

T1

13

T2

65

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6582	1			T2	1		T13	2		T14	9
valid_sources[0x01]	6477	1			T2	1		T4	1		T12	2
valid_sources[0x02]	6564	1			T1	1		T13	7		T14	25
valid_sources[0x03]	6332	1			T13	7		T14	7		T15	6
valid_sources[0x04]	6396	1			T13	8		T14	3		T24	4
valid_sources[0x05]	16873	1			T2	1		T4	1		T12	2
valid_sources[0x06]	7235	1			T12	45		T13	4		T14	26
valid_sources[0x07]	6949	1			T6	1		T11	2		T12	18
valid_sources[0x08]	8974	1			T13	6		T14	6		T15	2
valid_sources[0x09]	6219	1			T4	5		T12	2		T13	6
valid_sources[0x0a]	6835	1			T2	1		T13	7		T14	11
valid_sources[0x0b]	6401	1			T1	2		T13	6		T14	6
valid_sources[0x0c]	8192	1			T12	1		T13	7		T14	16
valid_sources[0x0d]	7620	1			T13	5		T14	19		T15	9
valid_sources[0x0e]	6413	1			T13	4		T14	14		T15	2
valid_sources[0x0f]	7422	1			T6	2		T13	11		T14	19
valid_sources[0x10]	7449	1			T2	2		T13	8		T14	22
valid_sources[0x11]	6278	1			T4	3		T12	3		T13	5
valid_sources[0x12]	6620	1			T4	2		T6	1		T11	3
valid_sources[0x13]	10761	1			T4	2		T13	11		T14	7
valid_sources[0x14]	7805	1			T2	2		T4	4		T12	1
valid_sources[0x15]	9383	1			T4	1		T12	9		T13	5
valid_sources[0x16]	7339	1			T6	1		T11	3		T12	6
valid_sources[0x17]	12840	1			T4	4		T12	9		T13	3
valid_sources[0x18]	6025	1			T13	4		T14	7		T24	4
valid_sources[0x19]	6542	1			T12	12		T13	4		T14	12
valid_sources[0x1a]	7606	1			T11	7		T13	6		T14	7
valid_sources[0x1b]	6490	1			T13	3		T14	2		T15	10
valid_sources[0x1c]	6239	1			T13	8		T14	6		T15	2
valid_sources[0x1d]	7932	1			T2	1		T12	1		T13	3
valid_sources[0x1e]	6238	1			T2	1		T12	9		T13	4
valid_sources[0x1f]	6408	1			T4	5		T6	1		T12	25
valid_sources[0x20]	13891	1			T13	12		T15	1		T16	3
valid_sources[0x21]	7205	1			T13	6		T14	34		T15	5
valid_sources[0x22]	6273	1			T4	1		T12	16		T13	4
valid_sources[0x23]	6724	1			T2	1		T4	2		T12	3
valid_sources[0x24]	41353	1			T4	2		T11	9		T13	6
valid_sources[0x25]	9063	1			T12	5		T13	5		T14	5
valid_sources[0x26]	8965	1			T1	1		T4	2		T12	5
valid_sources[0x27]	6357	1			T13	9		T14	32		T24	1
valid_sources[0x28]	7718	1			T1	1		T4	2		T12	15
valid_sources[0x29]	9560	1			T13	3		T14	6		T15	6
valid_sources[0x2a]	6781	1			T4	2		T12	5		T13	8
valid_sources[0x2b]	6529	1			T12	15		T13	8		T14	1
valid_sources[0x2c]	6399	1			T13	13		T14	16		T24	1
valid_sources[0x2d]	6645	1			T2	1		T12	3		T13	6
valid_sources[0x2e]	6520	1			T4	2		T12	5		T13	3
valid_sources[0x2f]	8370	1			T4	1		T13	4		T14	20
valid_sources[0x30]	9584	1			T12	2		T13	7		T14	15
valid_sources[0x31]	6605	1			T12	21		T13	7		T14	20
valid_sources[0x32]	6253	1			T13	9		T14	17		T24	1
valid_sources[0x33]	6678	1			T4	1		T11	2		T12	11
valid_sources[0x34]	11259	1			T13	9		T14	35		T15	12
valid_sources[0x35]	9682	1			T2	1		T13	3		T14	23
valid_sources[0x36]	6561	1			T13	4		T14	20		T15	5
valid_sources[0x37]	6437	1			T13	11		T14	14		T24	1
valid_sources[0x38]	6379	1			T4	3		T12	2		T13	6
valid_sources[0x39]	6084	1			T12	2		T13	5		T14	9
valid_sources[0x3a]	9090	1			T12	13		T13	3		T14	37
valid_sources[0x3b]	6533	1			T2	2		T4	1		T11	1
valid_sources[0x3c]	6727	1			T4	4		T13	5		T14	8
valid_sources[0x3d]	7871	1			T11	13		T12	4		T13	2
valid_sources[0x3e]	6726	1			T4	1		T13	7		T14	15
valid_sources[0x3f]	6087	1			T4	3		T13	6		T14	9
valid_sources[0x40]	55355	1			T4	1		T13	10		T14	7
valid_sources[0x41]	6136	1			T12	5		T13	4		T14	5
valid_sources[0x42]	6717	1			T12	18		T13	9		T14	10
valid_sources[0x43]	6513	1			T2	1		T12	11		T13	7
valid_sources[0x44]	6362	1			T2	3		T4	4		T13	6
valid_sources[0x45]	8378	1			T4	2		T13	6		T14	9
valid_sources[0x46]	6076	1			T11	2		T12	3		T13	6
valid_sources[0x47]	6578	1			T4	1		T13	10		T14	8
valid_sources[0x48]	6172	1			T13	6		T14	19		T15	3
valid_sources[0x49]	12551	1			T4	3		T13	4		T14	5
valid_sources[0x4a]	6427	1			T2	1		T4	1		T12	2
valid_sources[0x4b]	6094	1			T11	2		T13	8		T14	9
valid_sources[0x4c]	6904	1			T3	1		T12	4		T13	3
valid_sources[0x4d]	7528	1			T13	8		T14	23		T25	1
valid_sources[0x4e]	6023	1			T4	1		T13	8		T14	5
valid_sources[0x4f]	6631	1			T2	3		T4	1		T12	3
valid_sources[0x50]	8240	1			T13	5		T14	49		T15	5
valid_sources[0x51]	6357	1			T12	2		T13	6		T14	30
valid_sources[0x52]	6353	1			T4	4		T12	2		T13	6
valid_sources[0x53]	6683	1			T1	1		T2	5		T4	1
valid_sources[0x54]	8621	1			T4	3		T13	2		T14	10
valid_sources[0x55]	6331	1			T4	1		T13	5		T14	15
valid_sources[0x56]	6154	1			T13	6		T14	13		T25	1
valid_sources[0x57]	6511	1			T12	14		T13	3		T14	13
valid_sources[0x58]	6208	1			T1	1		T13	5		T14	7
valid_sources[0x59]	6410	1			T4	7		T12	49		T13	3
valid_sources[0x5a]	8226	1			T1	1		T13	9		T14	29
valid_sources[0x5b]	6396	1			T13	6		T25	1		T15	4
valid_sources[0x5c]	6647	1			T4	1		T13	3		T14	6
valid_sources[0x5d]	6512	1			T6	1		T12	6		T13	5
valid_sources[0x5e]	6519	1			T4	8		T11	1		T12	21
valid_sources[0x5f]	6264	1			T11	3		T13	4		T14	4
valid_sources[0x60]	6448	1			T4	3		T12	31		T13	12
valid_sources[0x61]	7521	1			T6	1		T13	3		T14	15
valid_sources[0x62]	6732	1			T2	4		T4	3		T13	5
valid_sources[0x63]	6253	1			T13	2		T14	7		T15	7
valid_sources[0x64]	6510	1			T12	5		T13	5		T14	14
valid_sources[0x65]	6506	1			T12	13		T13	5		T14	16
valid_sources[0x66]	6449	1			T4	1		T12	11		T13	5
valid_sources[0x67]	7673	1			T12	12		T13	6		T14	2
valid_sources[0x68]	6609	1			T13	4		T14	5		T15	6
valid_sources[0x69]	6517	1			T12	2		T13	7		T14	17
valid_sources[0x6a]	7924	1			T12	5		T13	5		T14	5
valid_sources[0x6b]	6641	1			T4	2		T6	1		T13	3
valid_sources[0x6c]	6948	1			T6	1		T11	1		T12	8
valid_sources[0x6d]	6459	1			T4	6		T12	30		T13	12
valid_sources[0x6e]	6404	1			T12	22		T13	5		T14	8
valid_sources[0x6f]	8003	1			T4	1		T12	9		T13	5
valid_sources[0x70]	6649	1			T13	4		T14	31		T24	2
valid_sources[0x71]	7762	1			T1	1		T2	2		T12	1
valid_sources[0x72]	5960	1			T1	3		T11	2		T13	5
valid_sources[0x73]	7017	1			T2	2		T3	1		T4	1
valid_sources[0x74]	6258	1			T4	5		T13	8		T14	16
valid_sources[0x75]	8818	1			T2	1		T3	1		T4	2
valid_sources[0x76]	6597	1			T13	8		T14	6		T15	4
valid_sources[0x77]	6302	1			T13	1		T14	18		T24	2
valid_sources[0x78]	6481	1			T2	2		T6	1		T12	23
valid_sources[0x79]	8376	1			T12	20		T13	3		T14	13
valid_sources[0x7a]	8577	1			T2	2		T12	3		T13	7
valid_sources[0x7b]	6472	1			T11	3		T12	6		T13	7
valid_sources[0x7c]	6406	1			T4	1		T6	1		T12	6
valid_sources[0x7d]	7775	1			T11	11		T13	10		T14	22
valid_sources[0x7e]	6992	1			T12	37		T13	6		T14	5
valid_sources[0x7f]	10419	1			T13	5		T14	16		T15	2
valid_sources[0x80]	7631	1			T2	3		T13	6		T14	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

861744

1

T1

1

T2

36

T4

115

values[0x0]

all_enables

biggest_size

122938

1

T1

4

T2

12

T4

7

values[0x1]

all_enables

biggest_size

121678

1

T1

7

T2

9

T4

12