Unified Coverage Report :: Module :: prim_generic_clock_inv

Module : prim_generic_clock_inv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67			66.67

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_inv_0/rtl/prim_generic_clock_inv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic	66.67			66.67

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.73			72.73

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67			66.67				i_tck_inv

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_scan.i_dft_tck_mux	75.00			75.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_generic_clock_inv

	Total	Covered	Percent
Totals	3	2	66.67
Total Bits	6	4	66.67
Total Bits 0->1	3	2	66.67
Total Bits 1->0	3	2	66.67

Ports	3	2	66.67
Port Bits	6	4	66.67
Port Bits 0->1	3	2	66.67
Port Bits 1->0	3	2	66.67

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	INPUT
scanmode_i	No	No		No		INPUT
clk_no	Yes	Yes	T6,T5,T7	Yes	T6,T5,T7	OUTPUT