Module Definition
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Module : prim_lc_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sender_0.1/rtl/prim_lc_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req 100.00 100.00
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.69 98.41 91.67 100.00 u_lc_ctrl_signal_decode


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.34 98.87 94.19 100.00 98.63 100.00 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.34 98.87 94.19 100.00 98.63 100.00 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.34 98.87 94.19 100.00 98.63 100.00 u_lc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_raw_test_rma
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_dft_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_nvm_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_hw_debug_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_cpu_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_creator_seed_sw_rw_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_owner_seed_sw_rw_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_rd_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_iso_part_sw_wr_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_seed_hw_rd_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_keymgr_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode.u_prim_lc_sender_escalate_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_clk_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_flash_rma_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sender_check_byp_en
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN6611100.00

31 logic [lc_ctrl_pkg::TxWidth-1:0] lc_en, lc_en_out; 32 1/1 assign lc_en = lc_ctrl_pkg::TxWidth'(lc_en_i); Tests: T1 T2 T3  33 34 if (AsyncOn) begin : gen_flops 35 prim_sec_anchor_flop #( 36 .Width(lc_ctrl_pkg::TxWidth), 37 .ResetValue(lc_ctrl_pkg::TxWidth'(ResetValue)) 38 ) u_prim_flop ( 39 .clk_i, 40 .rst_ni, 41 .d_i ( lc_en ), 42 .q_o ( lc_en_out ) 43 ); 44 end else begin : gen_no_flops 45 for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits 46 prim_sec_anchor_buf u_prim_buf ( 47 .in_i(lc_en[k]), 48 .out_o(lc_en_out[k]) 49 ); 50 end 51 52 // This unused companion logic helps remove lint errors 53 // for modules where clock and reset are used for assertions only 54 // or nothing at all. 55 // This logic will be removed for sythesis since it is unloaded. 56 lc_ctrl_pkg::lc_tx_t unused_logic; 57 always_ff @(posedge clk_i or negedge rst_ni) begin 58 if (!rst_ni) begin 59 unused_logic <= lc_ctrl_pkg::Off; 60 end else begin 61 unused_logic <= lc_en_i; 62 end 63 end 64 end 65 66 1/1 assign lc_en_o = lc_ctrl_pkg::lc_tx_t'(lc_en_out); Tests: T1 T2 T3 
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