Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133022867

1

T1

836

T2

1268

T3

4489

auto[1]

1612476

1

T4

198

T5

297

T12

5320

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133019954

1

T1

836

T2

1268

T3

4489

auto[1]

1615389

1

T4

99

T5

198

T12

6638

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	9266374	1			T1	92		T2	124		T3	1117
auto[IdleSt]	24738199	1			T1	50		T2	1144		T3	1702
auto[ClkMuxSt]	41806	1			T3	12		T4	3		T5	6
auto[CntIncrSt]	41475	1			T3	12		T4	3		T5	6
auto[CntProgSt]	1748458	1			T3	24		T4	814		T5	56
auto[TransCheckSt]	32207	1			T3	12		T5	6		T12	37
auto[TokenHashSt]	58365641	1			T3	553		T5	526		T12	5646
auto[FlashRmaSt]	41011	1			T3	32		T5	6		T12	34
auto[TokenCheck0St]	15051	1			T3	12		T5	6		T12	16
auto[TokenCheck1St]	11341	1			T3	12		T5	6		T12	16
auto[TransProgSt]	521855	1			T3	24		T5	61		T12	43
auto[PostTransSt]	15228468	1			T1	694		T3	977		T4	215
auto[ScrapSt]	354278	1			T12	4		T23	969		T19	379
auto[EscalateSt]	8531307	1			T4	407		T5	1229		T12	9091
auto[InvalidSt]	15695410	1			T5	847		T20	13757		T43	547

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2462	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	15695410	1			T5	847		T20	13757		T43	547
EscalateSt	8531307	1			T4	407		T5	1229		T12	9091
ScrapSt	354278	1			T12	4		T23	969		T19	379
PostTransSt	15228468	1			T1	694		T3	977		T4	215
TransProgSt	521855	1			T3	24		T5	61		T12	43
TokenCheck1St	11341	1			T3	12		T5	6		T12	16
TokenCheck0St	15051	1			T3	12		T5	6		T12	16
FlashRmaSt	41011	1			T3	32		T5	6		T12	34
TokenHashSt	58365641	1			T3	553		T5	526		T12	5646
TransCheckSt	32207	1			T3	12		T5	6		T12	37
CntProgSt	1748458	1			T3	24		T4	814		T5	56
CntIncrSt	41475	1			T3	12		T4	3		T5	6
ClkMuxSt	41806	1			T3	12		T4	3		T5	6
IdleSt	24738199	1			T1	50		T2	1144		T3	1702
ResetSt	9266374	1			T1	92		T2	124		T3	1117
arcs[ResetSt=>IdleSt]	64735	1			T1	1		T2	1		T3	12
arcs[IdleSt=>ScrapSt]	342	1			T12	1		T23	1		T19	1
arcs[IdleSt=>ClkMuxSt]	41502	1			T3	12		T4	3		T5	6
arcs[ClkMuxSt=>CntIncrSt]	41475	1			T3	12		T4	3		T5	6
arcs[CntIncrSt=>PostTransSt]	2341	1			T16	10		T38	10		T41	20
arcs[CntIncrSt=>CntProgSt]	39081	1			T3	12		T4	3		T5	6
arcs[CntProgSt=>PostTransSt]	5738	1			T4	3		T16	8		T17	7
arcs[CntProgSt=>TransCheckSt]	32207	1			T3	12		T5	6		T12	37
arcs[TransCheckSt=>PostTransSt]	4134	1			T16	11		T32	35		T38	14
arcs[TransCheckSt=>TokenHashSt]	27981	1			T3	12		T5	6		T12	35
arcs[TokenHashSt=>PostTransSt]	12088	1			T16	25		T32	12		T33	90
arcs[TokenHashSt=>FlashRmaSt]	15087	1			T3	12		T5	6		T12	17
arcs[FlashRmaSt=>TokenCheck0St]	15051	1			T3	12		T5	6		T12	16
arcs[TokenCheck0St=>PostTransSt]	3636	1			T16	11		T32	12		T38	9
arcs[TokenCheck0St=>TokenCheck1St]	11341	1			T3	12		T5	6		T12	16
arcs[TokenCheck1St=>PostTransSt]	701	1			T32	9		T42	2		T46	14
arcs[TransProgSt=>PostTransSt]	9778	1			T3	12		T5	6		T12	4
arcs[IdleSt=>EscalateSt]	131	1			T64	1		T67	6		T65	6
arcs[ClkMuxSt=>EscalateSt]	27	1			T64	1		T65	2		T66	1
arcs[CntIncrSt=>EscalateSt]	53	1			T64	2		T39	2		T67	1
arcs[CntProgSt=>EscalateSt]	1136	1			T12	10		T64	23		T39	8
arcs[TransCheckSt=>EscalateSt]	92	1			T12	2		T39	4		T67	2
arcs[TokenHashSt=>EscalateSt]	806	1			T12	18		T64	2		T39	35
arcs[FlashRmaSt=>EscalateSt]	36	1			T12	1		T64	2		T39	1
arcs[TokenCheck0St=>EscalateSt]	74	1			T64	1		T39	2		T70	2
arcs[TokenCheck1St=>EscalateSt]	36	1			T12	1		T71	1		T72	2
arcs[TransProgSt=>EscalateSt]	826	1			T12	11		T64	13		T39	10
arcs[PostTransSt=>EscalateSt]	6044	1			T4	3		T12	4		T16	8
arcs[InvalidSt=>EscalateSt]	17796	1			T5	5		T20	5		T43	8

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	9266205	1			T1	92		T2	124		T3	1117
auto[0]	auto[IdleSt]	24738113	1			T1	50		T2	1144		T3	1702
auto[0]	auto[ClkMuxSt]	41788	1			T3	12		T4	3		T5	6
auto[0]	auto[CntIncrSt]	41443	1			T3	12		T4	3		T5	6
auto[0]	auto[CntProgSt]	1747711	1			T3	24		T4	814		T5	56
auto[0]	auto[TransCheckSt]	32145	1			T3	12		T5	6		T12	35
auto[0]	auto[TokenHashSt]	58365129	1			T3	553		T5	526		T12	5639
auto[0]	auto[FlashRmaSt]	40985	1			T3	32		T5	6		T12	33
auto[0]	auto[TokenCheck0St]	15000	1			T3	12		T5	6		T12	16
auto[0]	auto[TokenCheck1St]	11316	1			T3	12		T5	6		T12	16
auto[0]	auto[TransProgSt]	521306	1			T3	24		T5	61		T12	36
auto[0]	auto[PostTransSt]	15225369	1			T1	694		T3	977		T4	213
auto[0]	auto[ScrapSt]	354241	1			T12	3		T23	969		T19	379
auto[0]	auto[EscalateSt]	6933099	1			T4	211		T5	935		T12	3803
auto[0]	auto[InvalidSt]	15686555	1			T5	844		T20	13754		T43	541
auto[1]	auto[ResetSt]	169	1			T12	4		T64	4		T39	5
auto[1]	auto[IdleSt]	86	1			T64	1		T67	4		T65	6
auto[1]	auto[ClkMuxSt]	18	1			T64	1		T65	1		T240	1
auto[1]	auto[CntIncrSt]	32	1			T67	1		T70	1		T71	1
auto[1]	auto[CntProgSt]	747	1			T12	8		T64	17		T39	2
auto[1]	auto[TransCheckSt]	62	1			T12	2		T39	3		T67	1
auto[1]	auto[TokenHashSt]	512	1			T12	7		T64	2		T39	16
auto[1]	auto[FlashRmaSt]	26	1			T12	1		T64	2		T70	2
auto[1]	auto[TokenCheck0St]	51	1			T64	1		T39	2		T70	2
auto[1]	auto[TokenCheck1St]	25	1			T71	1		T72	1		T241	1
auto[1]	auto[TransProgSt]	549	1			T12	7		T64	7		T39	5
auto[1]	auto[PostTransSt]	3099	1			T4	2		T12	2		T16	6
auto[1]	auto[ScrapSt]	37	1			T12	1		T39	2		T65	2
auto[1]	auto[EscalateSt]	1598208	1			T4	196		T5	294		T12	5288
auto[1]	auto[InvalidSt]	8855	1			T5	3		T20	3		T43	6

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	9266204	1			T1	92		T2	124		T3	1117
auto[0]	auto[IdleSt]	24738123	1			T1	50		T2	1144		T3	1702
auto[0]	auto[ClkMuxSt]	41792	1			T3	12		T4	3		T5	6
auto[0]	auto[CntIncrSt]	41438	1			T3	12		T4	3		T5	6
auto[0]	auto[CntProgSt]	1747676	1			T3	24		T4	814		T5	56
auto[0]	auto[TransCheckSt]	32149	1			T3	12		T5	6		T12	36
auto[0]	auto[TokenHashSt]	58365110	1			T3	553		T5	526		T12	5633
auto[0]	auto[FlashRmaSt]	40994	1			T3	32		T5	6		T12	34
auto[0]	auto[TokenCheck0St]	15006	1			T3	12		T5	6		T12	16
auto[0]	auto[TokenCheck1St]	11315	1			T3	12		T5	6		T12	15
auto[0]	auto[TransProgSt]	521326	1			T3	24		T5	61		T12	36
auto[0]	auto[PostTransSt]	15225426	1			T1	694		T3	977		T4	214
auto[0]	auto[ScrapSt]	354233	1			T12	4		T23	969		T19	379
auto[0]	auto[EscalateSt]	6930231	1			T4	309		T5	1033		T12	2491
auto[0]	auto[InvalidSt]	15686469	1			T5	845		T20	13755		T43	545
auto[1]	auto[ResetSt]	170	1			T12	6		T64	4		T39	2
auto[1]	auto[IdleSt]	76	1			T64	1		T67	3		T65	1
auto[1]	auto[ClkMuxSt]	14	1			T65	1		T66	1		T242	1
auto[1]	auto[CntIncrSt]	37	1			T64	2		T39	2		T72	1
auto[1]	auto[CntProgSt]	782	1			T12	8		T64	15		T39	7
auto[1]	auto[TransCheckSt]	58	1			T12	1		T39	1		T67	2
auto[1]	auto[TokenHashSt]	531	1			T12	13		T64	2		T39	29
auto[1]	auto[FlashRmaSt]	17	1			T39	1		T67	1		T70	1
auto[1]	auto[TokenCheck0St]	45	1			T39	2		T70	1		T65	1
auto[1]	auto[TokenCheck1St]	26	1			T12	1		T71	1		T72	2
auto[1]	auto[TransProgSt]	529	1			T12	7		T64	10		T39	9
auto[1]	auto[PostTransSt]	3042	1			T4	1		T12	2		T16	2
auto[1]	auto[ScrapSt]	45	1			T64	1		T39	3		T65	2
auto[1]	auto[EscalateSt]	1601076	1			T4	98		T5	196		T12	6600
auto[1]	auto[InvalidSt]	8941	1			T5	2		T20	2		T43	2