Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59089696

1

T1

1059

T2

2661

T3

1066

auto[1]

1174858

1

T4

686

T5

297

T11

98

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59130042

1

T1

1059

T2

2661

T3

1066

auto[1]

1134512

1

T4

785

T5

396

T11

392

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5279705	1			T1	150		T2	1225		T3	110
auto[IdleSt]	15551986	1			T1	52		T2	366		T3	956
auto[ClkMuxSt]	28213	1			T1	1		T2	15		T4	15
auto[CntIncrSt]	27986	1			T1	1		T2	14		T4	15
auto[CntProgSt]	1241747	1			T1	33		T2	28		T4	30
auto[TransCheckSt]	22342	1			T1	1		T2	14		T11	4
auto[TokenHashSt]	16994929	1			T1	17		T2	290		T11	509
auto[FlashRmaSt]	29101	1			T1	1		T2	31		T11	4
auto[TokenCheck0St]	10107	1			T1	1		T2	14		T11	4
auto[TokenCheck1St]	7348	1			T1	1		T2	14		T11	4
auto[TransProgSt]	313813	1			T1	20		T2	28		T11	8
auto[PostTransSt]	8844963	1			T1	781		T2	622		T12	1034
auto[ScrapSt]	268874	1			T41	16		T45	517		T46	42
auto[EscalateSt]	4658704	1			T4	6071		T5	868		T11	6593
auto[InvalidSt]	6983332	1			T11	5944		T16	285		T36	843

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1404	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6983332	1			T11	5944		T16	285		T36	843
EscalateSt	4658704	1			T4	6071		T5	868		T11	6593
ScrapSt	268874	1			T41	16		T45	517		T46	42
PostTransSt	8844963	1			T1	781		T2	622		T12	1034
TransProgSt	313813	1			T1	20		T2	28		T11	8
TokenCheck1St	7348	1			T1	1		T2	14		T11	4
TokenCheck0St	10107	1			T1	1		T2	14		T11	4
FlashRmaSt	29101	1			T1	1		T2	31		T11	4
TokenHashSt	16994929	1			T1	17		T2	290		T11	509
TransCheckSt	22342	1			T1	1		T2	14		T11	4
CntProgSt	1241747	1			T1	33		T2	28		T4	30
CntIncrSt	27986	1			T1	1		T2	14		T4	15
ClkMuxSt	28213	1			T1	1		T2	15		T4	15
IdleSt	15551986	1			T1	52		T2	366		T3	956
ResetSt	5279705	1			T1	150		T2	1225		T3	110
arcs[ResetSt=>IdleSt]	41987	1			T1	1		T2	14		T3	1
arcs[IdleSt=>ScrapSt]	237	1			T41	1		T45	1		T46	1
arcs[IdleSt=>ClkMuxSt]	28024	1			T1	1		T2	14		T4	15
arcs[ClkMuxSt=>CntIncrSt]	27986	1			T1	1		T2	14		T4	15
arcs[CntIncrSt=>PostTransSt]	1121	1			T21	7		T43	11		T44	12
arcs[CntIncrSt=>CntProgSt]	26800	1			T1	1		T2	14		T4	15
arcs[CntProgSt=>PostTransSt]	3406	1			T4	15		T5	7		T14	3
arcs[CntProgSt=>TransCheckSt]	22342	1			T1	1		T2	14		T11	4
arcs[TransCheckSt=>PostTransSt]	3057	1			T39	45		T34	33		T21	6
arcs[TransCheckSt=>TokenHashSt]	19168	1			T1	1		T2	14		T11	4
arcs[TokenHashSt=>PostTransSt]	8235	1			T33	5		T39	11		T40	72
arcs[TokenHashSt=>FlashRmaSt]	10149	1			T1	1		T2	14		T11	4
arcs[FlashRmaSt=>TokenCheck0St]	10107	1			T1	1		T2	14		T11	4
arcs[TokenCheck0St=>PostTransSt]	2689	1			T33	8		T39	20		T34	15
arcs[TokenCheck0St=>TokenCheck1St]	7348	1			T1	1		T2	14		T11	4
arcs[TokenCheck1St=>PostTransSt]	592	1			T39	10		T34	9		T48	10
arcs[TransProgSt=>PostTransSt]	5869	1			T1	1		T2	14		T11	4
arcs[IdleSt=>EscalateSt]	188	1			T18	4		T65	3		T62	5
arcs[ClkMuxSt=>EscalateSt]	38	1			T62	1		T63	1		T64	3
arcs[CntIncrSt=>EscalateSt]	65	1			T65	5		T62	2		T66	3
arcs[CntProgSt=>EscalateSt]	1052	1			T18	27		T65	24		T62	22
arcs[TransCheckSt=>EscalateSt]	117	1			T18	1		T62	2		T66	4
arcs[TokenHashSt=>EscalateSt]	784	1			T18	7		T65	8		T62	15
arcs[FlashRmaSt=>EscalateSt]	42	1			T18	1		T65	1		T62	1
arcs[TokenCheck0St=>EscalateSt]	70	1			T18	3		T65	1		T49	1
arcs[TokenCheck1St=>EscalateSt]	25	1			T18	1		T62	1		T66	1
arcs[TransProgSt=>EscalateSt]	862	1			T18	14		T65	30		T62	28
arcs[PostTransSt=>EscalateSt]	3720	1			T4	15		T5	7		T14	3
arcs[InvalidSt=>EscalateSt]	10220	1			T11	5		T16	4		T36	4

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5279517	1			T1	150		T2	1225		T3	110
auto[0]	auto[IdleSt]	15551861	1			T1	52		T2	366		T3	956
auto[0]	auto[ClkMuxSt]	28193	1			T1	1		T2	15		T4	15
auto[0]	auto[CntIncrSt]	27942	1			T1	1		T2	14		T4	15
auto[0]	auto[CntProgSt]	1241046	1			T1	33		T2	28		T4	30
auto[0]	auto[TransCheckSt]	22276	1			T1	1		T2	14		T11	4
auto[0]	auto[TokenHashSt]	16994388	1			T1	17		T2	290		T11	509
auto[0]	auto[FlashRmaSt]	29072	1			T1	1		T2	31		T11	4
auto[0]	auto[TokenCheck0St]	10060	1			T1	1		T2	14		T11	4
auto[0]	auto[TokenCheck1St]	7336	1			T1	1		T2	14		T11	4
auto[0]	auto[TransProgSt]	313238	1			T1	20		T2	28		T11	8
auto[0]	auto[PostTransSt]	8843005	1			T1	781		T2	622		T12	1034
auto[0]	auto[ScrapSt]	268839	1			T41	16		T45	517		T46	42
auto[0]	auto[EscalateSt]	3493408	1			T4	5392		T5	574		T11	6496
auto[0]	auto[InvalidSt]	6978111	1			T11	5943		T16	281		T36	840
auto[1]	auto[ResetSt]	188	1			T18	2		T65	5		T62	3
auto[1]	auto[IdleSt]	125	1			T18	4		T65	3		T62	5
auto[1]	auto[ClkMuxSt]	20	1			T64	2		T176	1		T225	1
auto[1]	auto[CntIncrSt]	44	1			T65	3		T62	2		T66	1
auto[1]	auto[CntProgSt]	701	1			T18	19		T65	13		T62	15
auto[1]	auto[TransCheckSt]	66	1			T18	1		T62	1		T66	3
auto[1]	auto[TokenHashSt]	541	1			T18	6		T65	7		T62	11
auto[1]	auto[FlashRmaSt]	29	1			T62	1		T226	1		T169	1
auto[1]	auto[TokenCheck0St]	47	1			T18	2		T66	1		T63	1
auto[1]	auto[TokenCheck1St]	12	1			T18	1		T62	1		T169	1
auto[1]	auto[TransProgSt]	575	1			T18	9		T65	20		T62	18
auto[1]	auto[PostTransSt]	1958	1			T4	7		T5	3		T14	2
auto[1]	auto[ScrapSt]	35	1			T62	1		T63	1		T169	1
auto[1]	auto[EscalateSt]	1165296	1			T4	679		T5	294		T11	97
auto[1]	auto[InvalidSt]	5221	1			T11	1		T16	4		T36	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5279540	1			T1	150		T2	1225		T3	110
auto[0]	auto[IdleSt]	15551866	1			T1	52		T2	366		T3	956
auto[0]	auto[ClkMuxSt]	28184	1			T1	1		T2	15		T4	15
auto[0]	auto[CntIncrSt]	27943	1			T1	1		T2	14		T4	15
auto[0]	auto[CntProgSt]	1241062	1			T1	33		T2	28		T4	30
auto[0]	auto[TransCheckSt]	22265	1			T1	1		T2	14		T11	4
auto[0]	auto[TokenHashSt]	16994412	1			T1	17		T2	290		T11	509
auto[0]	auto[FlashRmaSt]	29081	1			T1	1		T2	31		T11	4
auto[0]	auto[TokenCheck0St]	10056	1			T1	1		T2	14		T11	4
auto[0]	auto[TokenCheck1St]	7333	1			T1	1		T2	14		T11	4
auto[0]	auto[TransProgSt]	313236	1			T1	20		T2	28		T11	8
auto[0]	auto[PostTransSt]	8843100	1			T1	781		T2	622		T12	1034
auto[0]	auto[ScrapSt]	268835	1			T41	16		T45	517		T46	42
auto[0]	auto[EscalateSt]	3533392	1			T4	5294		T5	476		T11	6205
auto[0]	auto[InvalidSt]	6978333	1			T11	5940		T16	285		T36	842
auto[1]	auto[ResetSt]	165	1			T18	4		T65	2		T62	2
auto[1]	auto[IdleSt]	120	1			T18	1		T65	1		T62	4
auto[1]	auto[ClkMuxSt]	29	1			T62	1		T63	1		T64	2
auto[1]	auto[CntIncrSt]	43	1			T65	3		T62	1		T66	3
auto[1]	auto[CntProgSt]	685	1			T18	19		T65	16		T62	15
auto[1]	auto[TransCheckSt]	77	1			T62	2		T66	3		T169	4
auto[1]	auto[TokenHashSt]	517	1			T18	4		T65	5		T62	7
auto[1]	auto[FlashRmaSt]	20	1			T18	1		T65	1		T66	1
auto[1]	auto[TokenCheck0St]	51	1			T18	3		T65	1		T49	1
auto[1]	auto[TokenCheck1St]	15	1			T66	1		T64	1		T227	1
auto[1]	auto[TransProgSt]	577	1			T18	8		T65	19		T62	19
auto[1]	auto[PostTransSt]	1863	1			T4	8		T5	4		T14	1
auto[1]	auto[ScrapSt]	39	1			T62	1		T66	1		T226	2
auto[1]	auto[EscalateSt]	1125312	1			T4	777		T5	392		T11	388
auto[1]	auto[InvalidSt]	4999	1			T11	4		T36	1		T33	7