Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.92 97.97 95.41 93.40 97.67 98.53 99.00 96.47


Total tests in report: 997
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.50 58.50 79.62 79.62 44.64 44.64 55.29 55.29 34.88 34.88 72.63 72.63 91.54 91.54 30.92 30.92 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1032931917
70.41 11.90 87.08 7.45 73.72 29.07 71.38 16.09 48.84 13.95 80.63 8.00 93.03 1.49 38.16 7.24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3258023353
78.89 8.48 94.93 7.86 79.75 6.03 80.87 9.49 53.49 4.65 91.37 10.74 94.03 1.00 57.77 19.61 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3280506783
84.08 5.19 95.13 0.20 80.20 0.45 80.87 0.00 81.40 27.91 92.63 1.26 94.53 0.50 63.78 6.01 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3192349678
86.01 1.93 95.34 0.20 80.65 0.45 81.73 0.86 83.72 2.33 93.47 0.84 94.53 0.00 72.61 8.83 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.651008628
87.50 1.49 95.54 0.20 81.10 0.45 85.97 4.24 83.72 0.00 93.89 0.42 94.53 0.00 77.74 5.12 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2004446377
88.89 1.39 96.15 0.61 83.08 1.98 87.07 1.09 88.37 4.65 94.95 1.05 94.53 0.00 78.09 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3692423737
90.08 1.19 96.20 0.05 85.06 1.98 87.11 0.04 88.37 0.00 95.16 0.21 95.77 1.24 82.86 4.77 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2301656183
91.17 1.10 96.71 0.51 88.03 2.97 87.40 0.29 88.37 0.00 95.58 0.42 96.27 0.50 85.87 3.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3698048820
92.05 0.88 96.76 0.05 88.30 0.27 88.82 1.42 88.37 0.00 96.63 1.05 96.27 0.00 89.22 3.36 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1190031341
92.89 0.84 96.76 0.00 89.38 1.08 89.78 0.96 90.70 2.33 96.63 0.00 96.52 0.25 90.46 1.24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1812621842
93.68 0.79 96.86 0.10 90.10 0.72 90.28 0.51 93.02 2.33 97.05 0.42 96.77 0.25 91.70 1.24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2368711956
94.15 0.47 96.86 0.00 90.10 0.00 90.52 0.23 95.35 2.33 97.05 0.00 96.77 0.00 92.40 0.71 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.1047172992
94.59 0.44 97.01 0.15 91.18 1.08 90.52 0.00 95.35 0.00 97.47 0.42 96.77 0.00 93.82 1.41 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1300158312
94.92 0.33 97.01 0.00 91.18 0.00 90.52 0.00 97.67 2.33 97.47 0.00 96.77 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.591655958
95.13 0.21 97.01 0.00 91.18 0.00 90.52 0.00 97.67 0.00 97.47 0.00 98.26 1.49 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3369646630
95.34 0.21 97.06 0.05 92.17 0.99 90.52 0.00 97.67 0.00 97.89 0.42 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2723782206
95.55 0.20 97.42 0.35 93.07 0.90 90.69 0.17 97.67 0.00 97.89 0.00 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1572807061
95.74 0.19 97.42 0.00 93.07 0.00 91.50 0.81 97.67 0.00 97.89 0.00 98.26 0.00 94.35 0.53 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3952639047
95.88 0.14 97.42 0.00 93.07 0.00 92.48 0.98 97.67 0.00 97.89 0.00 98.26 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4238111426
95.99 0.11 97.47 0.05 93.07 0.00 92.55 0.07 97.67 0.00 98.11 0.21 98.51 0.25 94.52 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2630526866
96.08 0.10 97.57 0.10 93.07 0.00 92.56 0.01 97.67 0.00 98.32 0.21 98.51 0.00 94.88 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3379447131
96.17 0.08 97.57 0.00 93.07 0.00 93.15 0.59 97.67 0.00 98.32 0.00 98.51 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.426550242
96.23 0.06 97.57 0.00 93.52 0.45 93.15 0.00 97.67 0.00 98.32 0.00 98.51 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.241733907
96.29 0.06 97.97 0.41 93.52 0.00 93.18 0.03 97.67 0.00 98.32 0.00 98.51 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2764777333
96.34 0.05 97.97 0.00 93.88 0.36 93.18 0.00 97.67 0.00 98.32 0.00 98.51 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.1890922906
96.39 0.05 97.97 0.00 93.88 0.00 93.18 0.00 97.67 0.00 98.32 0.00 98.51 0.00 95.23 0.35 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.523036855
96.44 0.04 97.97 0.00 93.97 0.09 93.18 0.00 97.67 0.00 98.53 0.21 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1390258263
96.48 0.04 97.97 0.00 94.24 0.27 93.18 0.00 97.67 0.00 98.53 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.503992005
96.51 0.04 97.97 0.00 94.51 0.27 93.18 0.00 97.67 0.00 98.53 0.00 98.51 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2235281739
96.55 0.04 97.97 0.00 94.60 0.09 93.18 0.00 97.67 0.00 98.53 0.00 98.51 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3216675369
96.59 0.04 97.97 0.00 94.60 0.00 93.18 0.00 97.67 0.00 98.53 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2682747528
96.62 0.04 97.97 0.00 94.60 0.00 93.18 0.00 97.67 0.00 98.53 0.00 99.00 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1062457689
96.66 0.03 97.97 0.00 94.60 0.00 93.40 0.22 97.67 0.00 98.53 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1642648179
96.68 0.03 97.97 0.00 94.78 0.18 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.785015339
96.71 0.03 97.97 0.00 94.96 0.18 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3374177470
96.73 0.03 97.97 0.00 95.14 0.18 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1492117452
96.76 0.03 97.97 0.00 95.14 0.00 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3789494506
96.78 0.03 97.97 0.00 95.14 0.00 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3667000288
96.81 0.03 97.97 0.00 95.14 0.00 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2665285348
96.83 0.03 97.97 0.00 95.14 0.00 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.613983696
96.86 0.03 97.97 0.00 95.14 0.00 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.385475964
96.88 0.03 97.97 0.00 95.14 0.00 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 96.47 0.18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3403092200
96.90 0.01 97.97 0.00 95.23 0.09 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.896906494
96.91 0.01 97.97 0.00 95.32 0.09 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3486582509
96.92 0.01 97.97 0.00 95.41 0.09 93.40 0.00 97.67 0.00 98.53 0.00 99.00 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3328241325

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1654288526
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3695706707
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4015874595
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.333181600
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3151988643
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1855114915
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3798050665
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2178946347
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2309139333
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3591507009
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4162826219
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4159311762
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.765389789
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4193172752
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1556365340
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.533929923
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2656115981
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3784096829
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1291558791
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2470379261
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3606407818
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2668481674
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.434725233
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2051120247
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.221495478
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3699249943
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2035007246
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2738222373
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.383914427
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2498841942
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2969165643
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1580283526
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1370251342
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4224834796
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1607462788
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3727626987
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3233537393
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2955266529
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1168962684
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2187446988
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.565581322
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.278323625
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.711744608
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3204115795
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.365186882
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.3296622844
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2541239861
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2428683529
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3358200410
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.118626547
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1730384943
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.213701648
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.228276221
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.2945032857
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3206564663
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.684668925
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.393292709
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.841943109
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1040765653
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1758776193
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.491094377
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1630442041
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3290750042
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3329338161
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.4130031029
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1481103668
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1422451435
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.4094244636
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.4089930118
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.1149847915
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3127017379
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3489027230
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1697012663
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.424450792
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1292038067
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3770605412
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2051977721
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.574707937
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1202018090
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2442849702
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.4154170447
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3444161735
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3944218872
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.1413406794
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/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.363547650
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.779761883
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.899839071
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1944988488
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2764015471
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2850595392
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1792175901
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.421264653
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.1204303862
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.801757806
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.1840242711
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.741275325
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1987502628



Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2699247762 Oct 15 11:29:49 AM UTC 24 Oct 15 11:29:52 AM UTC 24 44238200 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1032931917 Oct 15 11:29:49 AM UTC 24 Oct 15 11:29:53 AM UTC 24 115746837 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3665946679 Oct 15 11:29:56 AM UTC 24 Oct 15 11:29:58 AM UTC 24 11242962 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3692423737 Oct 15 11:29:56 AM UTC 24 Oct 15 11:29:58 AM UTC 24 26014002 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1572807061 Oct 15 11:29:56 AM UTC 24 Oct 15 11:29:58 AM UTC 24 40691696 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4221998438 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:00 AM UTC 24 1556123947 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.787307207 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:00 AM UTC 24 133214727 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.126558378 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:00 AM UTC 24 36831624 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3698048820 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:01 AM UTC 24 353156144 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2389992302 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:01 AM UTC 24 646244909 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.667335586 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:01 AM UTC 24 249917214 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.690568485 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:03 AM UTC 24 164176214 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3789494506 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:03 AM UTC 24 39326637 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3379447131 Oct 15 11:29:49 AM UTC 24 Oct 15 11:30:03 AM UTC 24 597259679 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.1190031341 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:03 AM UTC 24 245959024 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3646003586 Oct 15 11:30:06 AM UTC 24 Oct 15 11:30:24 AM UTC 24 1596862012 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.1047172992 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:04 AM UTC 24 1275692114 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1727783586 Oct 15 11:30:02 AM UTC 24 Oct 15 11:30:05 AM UTC 24 13710238 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.430666018 Oct 15 11:30:02 AM UTC 24 Oct 15 11:30:05 AM UTC 24 37040814 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3013484964 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:06 AM UTC 24 1048792112 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.3667000288 Oct 15 11:29:49 AM UTC 24 Oct 15 11:30:06 AM UTC 24 594408175 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2630526866 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:06 AM UTC 24 710289110 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1662818203 Oct 15 11:30:02 AM UTC 24 Oct 15 11:30:06 AM UTC 24 64955134 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3280506783 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:06 AM UTC 24 937216569 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4238111426 Oct 15 11:29:49 AM UTC 24 Oct 15 11:30:07 AM UTC 24 150749935 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.651008628 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:08 AM UTC 24 270185491 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.2665285348 Oct 15 11:30:06 AM UTC 24 Oct 15 11:30:08 AM UTC 24 15721637 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.3296881892 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:08 AM UTC 24 200451504 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3601462127 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:08 AM UTC 24 1279989693 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3538730499 Oct 15 11:30:26 AM UTC 24 Oct 15 11:30:34 AM UTC 24 2528969062 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.1680071931 Oct 15 11:29:59 AM UTC 24 Oct 15 11:30:09 AM UTC 24 3755174858 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.839480541 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:10 AM UTC 24 283229057 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2764777333 Oct 15 11:30:10 AM UTC 24 Oct 15 11:30:34 AM UTC 24 592390797 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.3258023353 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:10 AM UTC 24 5053705278 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.4234063171 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:11 AM UTC 24 620169358 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.1087891129 Oct 15 11:30:07 AM UTC 24 Oct 15 11:30:11 AM UTC 24 200389077 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.3672291897 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:11 AM UTC 24 545607387 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1036003340 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:11 AM UTC 24 313168785 ps
T231 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2719098779 Oct 15 11:30:05 AM UTC 24 Oct 15 11:30:11 AM UTC 24 78466289 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1522777650 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:12 AM UTC 24 374125864 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.966210570 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:12 AM UTC 24 1781275293 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.2472416702 Oct 15 11:30:11 AM UTC 24 Oct 15 11:30:14 AM UTC 24 28671820 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2112542994 Oct 15 11:30:03 AM UTC 24 Oct 15 11:30:14 AM UTC 24 246985900 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.3261529367 Oct 15 11:30:07 AM UTC 24 Oct 15 11:30:15 AM UTC 24 1633461741 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1534313721 Oct 15 11:29:59 AM UTC 24 Oct 15 11:30:15 AM UTC 24 1604600908 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1602436177 Oct 15 11:29:59 AM UTC 24 Oct 15 11:30:15 AM UTC 24 458548856 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.3001938140 Oct 15 11:30:09 AM UTC 24 Oct 15 11:30:15 AM UTC 24 5283708395 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.429245581 Oct 15 11:30:13 AM UTC 24 Oct 15 11:30:16 AM UTC 24 45762640 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.153058293 Oct 15 11:30:13 AM UTC 24 Oct 15 11:30:16 AM UTC 24 104020459 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.226183375 Oct 15 11:29:58 AM UTC 24 Oct 15 11:30:17 AM UTC 24 721140526 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3192349678 Oct 15 11:30:05 AM UTC 24 Oct 15 11:30:17 AM UTC 24 341479949 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1874264527 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:17 AM UTC 24 120159062 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.613983696 Oct 15 11:30:15 AM UTC 24 Oct 15 11:30:17 AM UTC 24 17736189 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.1045886528 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:18 AM UTC 24 1368366127 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1048547162 Oct 15 11:30:13 AM UTC 24 Oct 15 11:30:19 AM UTC 24 79141544 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.3237976767 Oct 15 11:30:10 AM UTC 24 Oct 15 11:30:19 AM UTC 24 254550929 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3036425334 Oct 15 11:30:17 AM UTC 24 Oct 15 11:30:20 AM UTC 24 85054194 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2725818486 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:21 AM UTC 24 4875044180 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.4258811179 Oct 15 11:30:10 AM UTC 24 Oct 15 11:30:21 AM UTC 24 211888901 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2670604878 Oct 15 11:30:18 AM UTC 24 Oct 15 11:30:22 AM UTC 24 206228750 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.2358199688 Oct 15 11:30:07 AM UTC 24 Oct 15 11:30:22 AM UTC 24 3656983901 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.408678558 Oct 15 11:30:18 AM UTC 24 Oct 15 11:30:23 AM UTC 24 1192764218 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1156991657 Oct 15 11:30:05 AM UTC 24 Oct 15 11:30:23 AM UTC 24 370526129 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1381205780 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:23 AM UTC 24 661610130 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.2310365153 Oct 15 11:30:13 AM UTC 24 Oct 15 11:30:23 AM UTC 24 75160579 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.426746321 Oct 15 11:30:15 AM UTC 24 Oct 15 11:30:24 AM UTC 24 1169977528 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.873473437 Oct 15 11:30:22 AM UTC 24 Oct 15 11:30:24 AM UTC 24 51846403 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.1997844137 Oct 15 11:30:08 AM UTC 24 Oct 15 11:30:24 AM UTC 24 1410669815 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.426550242 Oct 15 11:30:03 AM UTC 24 Oct 15 11:30:33 AM UTC 24 494088058 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2659588080 Oct 15 11:30:14 AM UTC 24 Oct 15 11:30:25 AM UTC 24 1153468809 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3064470031 Oct 15 11:30:23 AM UTC 24 Oct 15 11:30:25 AM UTC 24 15267107 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1497070321 Oct 15 11:30:13 AM UTC 24 Oct 15 11:30:26 AM UTC 24 293767946 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2704964684 Oct 15 11:30:27 AM UTC 24 Oct 15 11:30:34 AM UTC 24 792967423 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3863772251 Oct 15 11:30:23 AM UTC 24 Oct 15 11:30:27 AM UTC 24 517436827 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.385475964 Oct 15 11:30:26 AM UTC 24 Oct 15 11:30:28 AM UTC 24 13054311 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.3325250083 Oct 15 11:30:18 AM UTC 24 Oct 15 11:30:28 AM UTC 24 995924792 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.4177225069 Oct 15 11:30:24 AM UTC 24 Oct 15 11:30:28 AM UTC 24 767396284 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3471058560 Oct 15 11:30:17 AM UTC 24 Oct 15 11:30:32 AM UTC 24 588283597 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.3901237894 Oct 15 11:30:01 AM UTC 24 Oct 15 11:30:37 AM UTC 24 473496030 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2269013566 Oct 15 11:30:19 AM UTC 24 Oct 15 11:30:35 AM UTC 24 894953271 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1851151958 Oct 15 11:30:24 AM UTC 24 Oct 15 11:30:37 AM UTC 24 559118044 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.1890241141 Oct 15 11:29:56 AM UTC 24 Oct 15 11:30:37 AM UTC 24 3424576347 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.789255734 Oct 15 11:30:24 AM UTC 24 Oct 15 11:30:37 AM UTC 24 6859383285 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.72349398 Oct 15 11:30:28 AM UTC 24 Oct 15 11:30:39 AM UTC 24 246789109 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2596063157 Oct 15 11:30:36 AM UTC 24 Oct 15 11:30:39 AM UTC 24 61705831 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.3684180637 Oct 15 11:30:17 AM UTC 24 Oct 15 11:30:39 AM UTC 24 1198916746 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1642997534 Oct 15 11:30:24 AM UTC 24 Oct 15 11:30:39 AM UTC 24 2403991876 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3288742453 Oct 15 11:30:26 AM UTC 24 Oct 15 11:30:40 AM UTC 24 1871739878 ps
T247 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.769785737 Oct 15 11:30:29 AM UTC 24 Oct 15 11:30:40 AM UTC 24 3687194526 ps
T248 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1090445750 Oct 15 11:30:19 AM UTC 24 Oct 15 11:30:41 AM UTC 24 487887609 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2541239861 Oct 15 11:30:38 AM UTC 24 Oct 15 11:30:41 AM UTC 24 128010176 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1959056867 Oct 15 11:30:13 AM UTC 24 Oct 15 11:30:41 AM UTC 24 1248863897 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.4198728863 Oct 15 11:30:24 AM UTC 24 Oct 15 11:30:41 AM UTC 24 429354358 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.365186882 Oct 15 11:30:38 AM UTC 24 Oct 15 11:30:42 AM UTC 24 60433365 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.1029677604 Oct 15 11:30:29 AM UTC 24 Oct 15 11:30:43 AM UTC 24 471729338 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3128243450 Oct 15 11:30:41 AM UTC 24 Oct 15 11:30:43 AM UTC 24 51742062 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2051940893 Oct 15 11:30:09 AM UTC 24 Oct 15 11:30:44 AM UTC 24 14184122829 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.393292709 Oct 15 11:31:06 AM UTC 24 Oct 15 11:31:15 AM UTC 24 1175876606 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.2004446377 Oct 15 11:29:56 AM UTC 24 Oct 15 11:31:17 AM UTC 24 3440069561 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.151995281 Oct 15 11:30:40 AM UTC 24 Oct 15 11:30:44 AM UTC 24 118730719 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.4145977930 Oct 15 11:30:22 AM UTC 24 Oct 15 11:30:45 AM UTC 24 804400593 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1121008701 Oct 15 11:29:50 AM UTC 24 Oct 15 11:30:45 AM UTC 24 12893111704 ps
T254 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2053395930 Oct 15 11:30:24 AM UTC 24 Oct 15 11:30:46 AM UTC 24 997519924 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1214974312 Oct 15 11:30:34 AM UTC 24 Oct 15 11:30:47 AM UTC 24 1257203273 ps
T256 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.2582794744 Oct 15 11:30:44 AM UTC 24 Oct 15 11:30:47 AM UTC 24 71154445 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2359698781 Oct 15 11:30:34 AM UTC 24 Oct 15 11:30:48 AM UTC 24 589856557 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.756315422 Oct 15 11:30:18 AM UTC 24 Oct 15 11:31:17 AM UTC 24 5792624647 ps
T258 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1838190464 Oct 15 11:30:42 AM UTC 24 Oct 15 11:30:48 AM UTC 24 131238278 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2368711956 Oct 15 11:30:11 AM UTC 24 Oct 15 11:30:49 AM UTC 24 4292206500 ps
T259 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.108613302 Oct 15 11:30:41 AM UTC 24 Oct 15 11:30:49 AM UTC 24 953418137 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2488752402 Oct 15 11:30:48 AM UTC 24 Oct 15 11:30:50 AM UTC 24 14507540 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.4080985769 Oct 15 11:30:18 AM UTC 24 Oct 15 11:30:50 AM UTC 24 1061619720 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3196637979 Oct 15 11:30:29 AM UTC 24 Oct 15 11:30:50 AM UTC 24 2193940102 ps
T262 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1730384943 Oct 15 11:30:48 AM UTC 24 Oct 15 11:30:51 AM UTC 24 122444790 ps
T263 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.684668925 Oct 15 11:30:49 AM UTC 24 Oct 15 11:30:51 AM UTC 24 11392265 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2897924455 Oct 15 11:30:40 AM UTC 24 Oct 15 11:30:51 AM UTC 24 392707316 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.3569573545 Oct 15 11:30:39 AM UTC 24 Oct 15 11:30:52 AM UTC 24 75692060 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3076115183 Oct 15 11:30:44 AM UTC 24 Oct 15 11:30:53 AM UTC 24 644269990 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3403092200 Oct 15 11:30:51 AM UTC 24 Oct 15 11:30:54 AM UTC 24 79353938 ps
T265 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.2040260080 Oct 15 11:30:40 AM UTC 24 Oct 15 11:30:54 AM UTC 24 316798376 ps
T266 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.372183909 Oct 15 11:30:50 AM UTC 24 Oct 15 11:30:54 AM UTC 24 115638286 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3520900608 Oct 15 11:30:41 AM UTC 24 Oct 15 11:30:55 AM UTC 24 496431502 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.1108957460 Oct 15 11:30:36 AM UTC 24 Oct 15 11:30:56 AM UTC 24 255582095 ps
T267 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.852641494 Oct 15 11:30:45 AM UTC 24 Oct 15 11:30:57 AM UTC 24 189050297 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3952639047 Oct 15 11:30:11 AM UTC 24 Oct 15 11:30:58 AM UTC 24 1463261091 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.228276221 Oct 15 11:30:50 AM UTC 24 Oct 15 11:30:59 AM UTC 24 82962159 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1625754696 Oct 15 11:30:44 AM UTC 24 Oct 15 11:30:59 AM UTC 24 2023333344 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2117294500 Oct 15 11:30:07 AM UTC 24 Oct 15 11:30:59 AM UTC 24 3177492434 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.3662096351 Oct 15 11:30:07 AM UTC 24 Oct 15 11:30:59 AM UTC 24 12041132741 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1841917340 Oct 15 11:30:45 AM UTC 24 Oct 15 11:31:01 AM UTC 24 335765953 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.607116132 Oct 15 11:30:55 AM UTC 24 Oct 15 11:31:02 AM UTC 24 406024119 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.3024062385 Oct 15 11:31:00 AM UTC 24 Oct 15 11:31:02 AM UTC 24 118129313 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2273156125 Oct 15 11:30:55 AM UTC 24 Oct 15 11:31:03 AM UTC 24 525447527 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.118626547 Oct 15 11:30:51 AM UTC 24 Oct 15 11:31:03 AM UTC 24 488888449 ps
T268 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3992027363 Oct 15 11:31:02 AM UTC 24 Oct 15 11:31:05 AM UTC 24 13930732 ps
T269 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2905483519 Oct 15 11:30:58 AM UTC 24 Oct 15 11:31:05 AM UTC 24 226687471 ps
T270 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1630442041 Oct 15 11:31:01 AM UTC 24 Oct 15 11:31:05 AM UTC 24 62005216 ps
T271 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3097213578 Oct 15 11:30:46 AM UTC 24 Oct 15 11:31:05 AM UTC 24 286830648 ps
T272 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3379744007 Oct 15 11:30:51 AM UTC 24 Oct 15 11:31:06 AM UTC 24 3296573601 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2422753248 Oct 15 11:30:55 AM UTC 24 Oct 15 11:31:06 AM UTC 24 483996460 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2817902370 Oct 15 11:30:53 AM UTC 24 Oct 15 11:31:06 AM UTC 24 1139029537 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1642648179 Oct 15 11:30:38 AM UTC 24 Oct 15 11:31:08 AM UTC 24 1729548386 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2695610142 Oct 15 11:30:01 AM UTC 24 Oct 15 11:31:08 AM UTC 24 1373050790 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1707358223 Oct 15 11:30:42 AM UTC 24 Oct 15 11:31:08 AM UTC 24 4551735702 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.3329338161 Oct 15 11:31:03 AM UTC 24 Oct 15 11:31:09 AM UTC 24 88812705 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1700770390 Oct 15 11:31:04 AM UTC 24 Oct 15 11:31:09 AM UTC 24 94538959 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1633323619 Oct 15 11:31:06 AM UTC 24 Oct 15 11:31:09 AM UTC 24 17632863 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3621773072 Oct 15 11:31:06 AM UTC 24 Oct 15 11:31:09 AM UTC 24 294851438 ps
T279 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.1382189997 Oct 15 11:30:54 AM UTC 24 Oct 15 11:31:10 AM UTC 24 7473246648 ps
T280 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2428683529 Oct 15 11:30:57 AM UTC 24 Oct 15 11:31:10 AM UTC 24 999562220 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3358200410 Oct 15 11:31:00 AM UTC 24 Oct 15 11:31:10 AM UTC 24 184062617 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.213701648 Oct 15 11:30:49 AM UTC 24 Oct 15 11:31:11 AM UTC 24 746683941 ps
T283 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.4217446888 Oct 15 11:30:51 AM UTC 24 Oct 15 11:31:11 AM UTC 24 275032550 ps
T284 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.2558712313 Oct 15 11:31:07 AM UTC 24 Oct 15 11:31:12 AM UTC 24 82086310 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.2642967209 Oct 15 11:31:12 AM UTC 24 Oct 15 11:31:15 AM UTC 24 62525691 ps
T286 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3617028810 Oct 15 11:31:12 AM UTC 24 Oct 15 11:31:15 AM UTC 24 216717010 ps
T287 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.2638731022 Oct 15 11:31:05 AM UTC 24 Oct 15 11:31:16 AM UTC 24 287970440 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1771530591 Oct 15 11:31:09 AM UTC 24 Oct 15 11:31:19 AM UTC 24 621933915 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2760966626 Oct 15 11:30:17 AM UTC 24 Oct 15 11:31:18 AM UTC 24 3387118237 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.491094377 Oct 15 11:31:06 AM UTC 24 Oct 15 11:31:19 AM UTC 24 615131606 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.3944218872 Oct 15 11:31:12 AM UTC 24 Oct 15 11:31:20 AM UTC 24 770712794 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2051977721 Oct 15 11:31:16 AM UTC 24 Oct 15 11:31:22 AM UTC 24 1540768799 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1422451435 Oct 15 11:31:18 AM UTC 24 Oct 15 11:31:22 AM UTC 24 11212801 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3206564663 Oct 15 11:31:00 AM UTC 24 Oct 15 11:31:22 AM UTC 24 2481679996 ps
T172 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.1758776193 Oct 15 11:31:10 AM UTC 24 Oct 15 11:31:23 AM UTC 24 1253724382 ps
T173 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.1413406794 Oct 15 11:31:13 AM UTC 24 Oct 15 11:31:24 AM UTC 24 42942672 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.2313639722 Oct 15 11:31:09 AM UTC 24 Oct 15 11:31:25 AM UTC 24 2488307548 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.4094244636 Oct 15 11:31:16 AM UTC 24 Oct 15 11:31:25 AM UTC 24 630048556 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3290750042 Oct 15 11:31:02 AM UTC 24 Oct 15 11:31:27 AM UTC 24 1097875295 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3444161735 Oct 15 11:31:17 AM UTC 24 Oct 15 11:31:29 AM UTC 24 491225605 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.424450792 Oct 15 11:31:18 AM UTC 24 Oct 15 11:31:29 AM UTC 24 1392298131 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.272232823 Oct 15 11:30:56 AM UTC 24 Oct 15 11:31:30 AM UTC 24 2498490642 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.3203789329 Oct 15 11:31:06 AM UTC 24 Oct 15 11:31:30 AM UTC 24 662401198 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1040765653 Oct 15 11:31:10 AM UTC 24 Oct 15 11:31:30 AM UTC 24 678031204 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.384277839 Oct 15 11:30:42 AM UTC 24 Oct 15 11:31:31 AM UTC 24 2895642133 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.1315246843 Oct 15 11:30:27 AM UTC 24 Oct 15 11:31:32 AM UTC 24 2293348808 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.574707937 Oct 15 11:31:17 AM UTC 24 Oct 15 11:31:32 AM UTC 24 403921421 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1481103668 Oct 15 11:31:30 AM UTC 24 Oct 15 11:31:32 AM UTC 24 17805310 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.4154170447 Oct 15 11:31:25 AM UTC 24 Oct 15 11:31:33 AM UTC 24 230113433 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1987502628 Oct 15 11:31:31 AM UTC 24 Oct 15 11:31:34 AM UTC 24 58088484 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1697012663 Oct 15 11:31:23 AM UTC 24 Oct 15 11:31:35 AM UTC 24 774982412 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.492344161 Oct 15 11:30:26 AM UTC 24 Oct 15 11:31:35 AM UTC 24 15194693542 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.421264653 Oct 15 11:31:30 AM UTC 24 Oct 15 11:31:35 AM UTC 24 294840456 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3265032720 Oct 15 11:30:43 AM UTC 24 Oct 15 11:31:36 AM UTC 24 1747197420 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.2266101275 Oct 15 11:31:34 AM UTC 24 Oct 15 11:31:36 AM UTC 24 35141660 ps
T304 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1515393261 Oct 15 11:31:10 AM UTC 24 Oct 15 11:31:37 AM UTC 24 2456662314 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.4089930118 Oct 15 11:31:23 AM UTC 24 Oct 15 11:31:38 AM UTC 24 898039056 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.779761883 Oct 15 11:31:32 AM UTC 24 Oct 15 11:31:38 AM UTC 24 251063911 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1202018090 Oct 15 11:31:24 AM UTC 24 Oct 15 11:31:42 AM UTC 24 309338288 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1270732980 Oct 15 11:31:35 AM UTC 24 Oct 15 11:31:42 AM UTC 24 794914805 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3127017379 Oct 15 11:31:23 AM UTC 24 Oct 15 11:31:43 AM UTC 24 612544777 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.841943109 Oct 15 11:31:10 AM UTC 24 Oct 15 11:31:44 AM UTC 24 2979113052 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.132474843 Oct 15 11:31:37 AM UTC 24 Oct 15 11:31:45 AM UTC 24 1738097134 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.801757806 Oct 15 11:31:31 AM UTC 24 Oct 15 11:31:45 AM UTC 24 149325964 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.928112412 Oct 15 11:31:37 AM UTC 24 Oct 15 11:31:45 AM UTC 24 601306439 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1792175901 Oct 15 11:31:33 AM UTC 24 Oct 15 11:31:47 AM UTC 24 1179010755 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.164687076 Oct 15 11:31:36 AM UTC 24 Oct 15 11:31:47 AM UTC 24 299321420 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.4244343269 Oct 15 11:31:12 AM UTC 24 Oct 15 11:31:47 AM UTC 24 560720155 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3489027230 Oct 15 11:31:20 AM UTC 24 Oct 15 11:31:48 AM UTC 24 2726875917 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.563132877 Oct 15 11:31:45 AM UTC 24 Oct 15 11:31:48 AM UTC 24 21856706 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.57518085 Oct 15 11:31:46 AM UTC 24 Oct 15 11:31:49 AM UTC 24 83865880 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3770605412 Oct 15 11:31:20 AM UTC 24 Oct 15 11:31:49 AM UTC 24 719985400 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1718260774 Oct 15 11:31:45 AM UTC 24 Oct 15 11:31:50 AM UTC 24 144023341 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2442849702 Oct 15 11:31:25 AM UTC 24 Oct 15 11:31:51 AM UTC 24 17191089962 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1563694043 Oct 15 11:31:49 AM UTC 24 Oct 15 11:31:52 AM UTC 24 135897281 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3194388952 Oct 15 11:30:35 AM UTC 24 Oct 15 11:31:53 AM UTC 24 18584599090 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.2850595392 Oct 15 11:31:43 AM UTC 24 Oct 15 11:31:54 AM UTC 24 817330093 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.3523606975 Oct 15 11:30:53 AM UTC 24 Oct 15 11:31:54 AM UTC 24 9591910215 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.3024650469 Oct 15 11:31:09 AM UTC 24 Oct 15 11:31:54 AM UTC 24 5051132329 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.363547650 Oct 15 11:31:36 AM UTC 24 Oct 15 11:31:54 AM UTC 24 2010128814 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3521774889 Oct 15 11:30:55 AM UTC 24 Oct 15 11:31:54 AM UTC 24 31777984405 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1292038067 Oct 15 11:31:20 AM UTC 24 Oct 15 11:31:55 AM UTC 24 3989294221 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3021558777 Oct 15 11:31:33 AM UTC 24 Oct 15 11:31:55 AM UTC 24 4378324175 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.899839071 Oct 15 11:31:33 AM UTC 24 Oct 15 11:31:56 AM UTC 24 329623676 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.279530905 Oct 15 11:31:49 AM UTC 24 Oct 15 11:31:57 AM UTC 24 4119974711 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.3898387108 Oct 15 11:31:56 AM UTC 24 Oct 15 11:31:58 AM UTC 24 40012852 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3461198711 Oct 15 11:31:50 AM UTC 24 Oct 15 11:31:59 AM UTC 24 4340565191 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.54092455 Oct 15 11:31:52 AM UTC 24 Oct 15 11:31:59 AM UTC 24 3047084641 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3824302465 Oct 15 11:31:57 AM UTC 24 Oct 15 11:31:59 AM UTC 24 51054852 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2575062024 Oct 15 11:31:48 AM UTC 24 Oct 15 11:31:59 AM UTC 24 305179472 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.1204303862 Oct 15 11:31:31 AM UTC 24 Oct 15 11:32:00 AM UTC 24 792610309 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1944988488 Oct 15 11:31:40 AM UTC 24 Oct 15 11:32:00 AM UTC 24 484979027 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.2764015471 Oct 15 11:31:43 AM UTC 24 Oct 15 11:32:02 AM UTC 24 488632368 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3528578410 Oct 15 11:31:58 AM UTC 24 Oct 15 11:32:02 AM UTC 24 73176875 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2743266637 Oct 15 11:31:49 AM UTC 24 Oct 15 11:32:03 AM UTC 24 790342985 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3158288746 Oct 15 11:31:57 AM UTC 24 Oct 15 11:32:03 AM UTC 24 60756157 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.2658567426 Oct 15 11:31:54 AM UTC 24 Oct 15 11:32:03 AM UTC 24 407659753 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1019789464 Oct 15 11:31:51 AM UTC 24 Oct 15 11:32:04 AM UTC 24 623546822 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1142703135 Oct 15 11:32:01 AM UTC 24 Oct 15 11:32:04 AM UTC 24 81698142 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.1149847915 Oct 15 11:31:22 AM UTC 24 Oct 15 11:32:05 AM UTC 24 1341454889 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2621157475 Oct 15 11:31:55 AM UTC 24 Oct 15 11:32:06 AM UTC 24 216540002 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1551300607 Oct 15 11:31:55 AM UTC 24 Oct 15 11:32:06 AM UTC 24 445578818 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.3919985221 Oct 15 11:31:48 AM UTC 24 Oct 15 11:32:07 AM UTC 24 2573613368 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.1928848221 Oct 15 11:31:06 AM UTC 24 Oct 15 11:32:08 AM UTC 24 50883831173 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.688555008 Oct 15 11:31:55 AM UTC 24 Oct 15 11:32:09 AM UTC 24 581321864 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.579020711 Oct 15 11:32:07 AM UTC 24 Oct 15 11:32:09 AM UTC 24 164839507 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2848617786 Oct 15 11:32:07 AM UTC 24 Oct 15 11:32:09 AM UTC 24 14862668 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3085693629 Oct 15 11:32:03 AM UTC 24 Oct 15 11:32:09 AM UTC 24 1629549210 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.167582241 Oct 15 11:31:58 AM UTC 24 Oct 15 11:32:09 AM UTC 24 219422818 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.536515854 Oct 15 11:32:01 AM UTC 24 Oct 15 11:32:11 AM UTC 24 729217207 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3156922561 Oct 15 11:32:07 AM UTC 24 Oct 15 11:32:11 AM UTC 24 168657563 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3516256332 Oct 15 11:32:01 AM UTC 24 Oct 15 11:32:14 AM UTC 24 199733815 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.790849169 Oct 15 11:32:10 AM UTC 24 Oct 15 11:32:14 AM UTC 24 1150503513 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1712337177 Oct 15 11:30:11 AM UTC 24 Oct 15 11:32:14 AM UTC 24 3654799452 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1812621842 Oct 15 11:30:35 AM UTC 24 Oct 15 11:32:15 AM UTC 24 5671729110 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1823239510 Oct 15 11:32:04 AM UTC 24 Oct 15 11:32:18 AM UTC 24 573166010 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.237515782 Oct 15 11:32:15 AM UTC 24 Oct 15 11:32:19 AM UTC 24 134330582 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.3684391296 Oct 15 11:31:59 AM UTC 24 Oct 15 11:32:19 AM UTC 24 718459729 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.955472204 Oct 15 11:32:09 AM UTC 24 Oct 15 11:32:20 AM UTC 24 380676574 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.1391517893 Oct 15 11:32:04 AM UTC 24 Oct 15 11:32:20 AM UTC 24 233732350 ps
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