Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.24 97.99 95.95 93.40 100.00 98.55 98.51 96.29


Total tests in report: 1012
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
64.70 64.70 81.29 81.29 45.00 45.00 55.71 55.71 58.14 58.14 81.12 81.12 92.04 92.04 39.58 39.58 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1964652615
74.91 10.21 87.98 6.69 71.92 26.91 72.33 16.62 62.79 4.65 87.14 6.02 93.78 1.74 48.41 8.83 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2800746526
80.84 5.93 88.83 0.86 75.70 3.78 74.08 1.75 74.42 11.63 90.25 3.11 94.03 0.25 68.55 20.14 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2061972405
83.83 2.99 95.17 6.34 77.86 2.16 76.83 2.75 76.74 2.33 92.32 2.07 94.03 0.00 73.85 5.30 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2462337198
85.73 1.90 95.17 0.00 79.75 1.89 77.16 0.32 86.05 9.30 92.32 0.00 94.03 0.00 75.62 1.77 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3392506599
87.31 1.59 95.67 0.50 81.37 1.62 80.27 3.11 90.70 4.65 93.36 1.04 94.03 0.00 75.80 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.777962638
88.89 1.57 96.68 1.01 85.69 4.32 80.51 0.24 90.70 0.00 94.81 1.45 95.02 1.00 78.80 3.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3590903382
90.29 1.40 96.73 0.05 85.96 0.27 87.15 6.64 90.70 0.00 95.02 0.21 95.02 0.00 81.45 2.65 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1204167952
91.33 1.04 96.98 0.25 87.85 1.89 87.25 0.10 90.70 0.00 95.64 0.62 96.27 1.24 84.63 3.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2291440938
92.10 0.77 97.03 0.05 88.48 0.63 87.91 0.66 93.02 2.33 95.85 0.21 96.52 0.25 85.87 1.24 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3267366938
92.84 0.75 97.03 0.00 89.20 0.72 87.91 0.00 95.35 2.33 95.85 0.00 96.77 0.25 87.81 1.94 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.475195841
93.57 0.72 97.13 0.10 89.38 0.18 91.07 3.17 95.35 0.00 96.06 0.21 96.77 0.00 89.22 1.41 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2619104214
94.29 0.72 97.28 0.15 89.38 0.00 91.44 0.36 97.67 2.33 96.68 0.62 96.77 0.00 90.81 1.59 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.323816626
94.77 0.48 97.28 0.00 90.19 0.81 91.48 0.04 100.00 2.33 96.68 0.00 96.77 0.00 90.99 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3782358565
95.16 0.39 97.28 0.00 91.45 1.26 91.48 0.00 100.00 0.00 96.89 0.21 96.77 0.00 92.23 1.24 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2912395677
95.38 0.23 97.28 0.00 91.54 0.09 91.48 0.00 100.00 0.00 96.89 0.00 98.26 1.49 92.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.713145918
95.60 0.22 97.64 0.35 92.44 0.90 91.74 0.26 100.00 0.00 96.89 0.00 98.26 0.00 92.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1904144684
95.81 0.21 97.74 0.10 92.44 0.00 92.05 0.30 100.00 0.00 97.10 0.21 98.26 0.00 93.11 0.88 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3044745817
96.02 0.21 97.79 0.05 93.43 0.99 92.05 0.00 100.00 0.00 97.51 0.41 98.26 0.00 93.11 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3127213360
96.16 0.14 97.94 0.15 93.43 0.00 92.26 0.21 100.00 0.00 97.93 0.41 98.26 0.00 93.29 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.217528607
96.27 0.11 97.94 0.00 93.88 0.45 92.26 0.00 100.00 0.00 97.93 0.00 98.26 0.00 93.64 0.35 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.790728052
96.38 0.10 97.94 0.00 93.88 0.00 92.99 0.73 100.00 0.00 97.93 0.00 98.26 0.00 93.64 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1981334217
96.48 0.10 97.94 0.00 93.88 0.00 92.99 0.00 100.00 0.00 97.93 0.00 98.26 0.00 94.35 0.71 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.749626974
96.55 0.08 97.94 0.00 93.88 0.00 92.99 0.00 100.00 0.00 97.93 0.00 98.26 0.00 94.88 0.53 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.735596453
96.62 0.06 97.94 0.00 94.15 0.27 92.99 0.00 100.00 0.00 97.93 0.00 98.26 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.50259680
96.68 0.06 97.94 0.00 94.33 0.18 93.02 0.03 100.00 0.00 98.13 0.21 98.26 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1907357932
96.73 0.05 97.94 0.00 94.33 0.00 93.20 0.18 100.00 0.00 98.13 0.00 98.26 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4237520671
96.77 0.04 97.94 0.00 94.42 0.09 93.20 0.00 100.00 0.00 98.34 0.21 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2165210761
96.81 0.04 97.94 0.00 94.69 0.27 93.20 0.00 100.00 0.00 98.34 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1068099966
96.85 0.04 97.94 0.00 94.96 0.27 93.20 0.00 100.00 0.00 98.34 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1229078356
96.88 0.04 97.94 0.00 95.23 0.27 93.20 0.00 100.00 0.00 98.34 0.00 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1449870524
96.92 0.04 97.99 0.05 95.23 0.00 93.21 0.01 100.00 0.00 98.55 0.21 98.26 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.998031189
96.96 0.04 97.99 0.00 95.23 0.00 93.21 0.00 100.00 0.00 98.55 0.00 98.51 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2423541613
96.99 0.03 97.99 0.00 95.23 0.00 93.24 0.03 100.00 0.00 98.55 0.00 98.51 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3771696667
97.01 0.03 97.99 0.00 95.41 0.18 93.24 0.00 100.00 0.00 98.55 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.862938066
97.04 0.03 97.99 0.00 95.59 0.18 93.24 0.00 100.00 0.00 98.55 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.942529395
97.07 0.03 97.99 0.00 95.59 0.00 93.24 0.00 100.00 0.00 98.55 0.00 98.51 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.649856757
97.09 0.03 97.99 0.00 95.59 0.00 93.24 0.00 100.00 0.00 98.55 0.00 98.51 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.1715034235
97.12 0.03 97.99 0.00 95.59 0.00 93.24 0.00 100.00 0.00 98.55 0.00 98.51 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.811619065
97.14 0.03 97.99 0.00 95.59 0.00 93.24 0.00 100.00 0.00 98.55 0.00 98.51 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1065287265
97.17 0.03 97.99 0.00 95.59 0.00 93.24 0.00 100.00 0.00 98.55 0.00 98.51 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.936263236
97.19 0.02 97.99 0.00 95.59 0.00 93.40 0.16 100.00 0.00 98.55 0.00 98.51 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3628692062
97.20 0.01 97.99 0.00 95.68 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.51 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2188664118
97.21 0.01 97.99 0.00 95.77 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.51 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1193832018
97.23 0.01 97.99 0.00 95.86 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.51 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2648676347
97.24 0.01 97.99 0.00 95.95 0.09 93.40 0.00 100.00 0.00 98.55 0.00 98.51 0.00 96.29 0.00 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.756284413

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3408699689
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4134758250
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2932971983
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.552039335
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4242842757
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.91459319
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4037105321
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3123460762
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1317149874
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.95591656
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3602828605
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4259568755
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4183713872
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2684625164
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.657890111
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.39817756
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.409371571
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2277879446
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.4154529233
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.361189357
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4155115917
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.894510679
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2010687800
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1079826958
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.738406328
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2472258284
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4004610223
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3217475397
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2524090681
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2687634860
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1503017307
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2327871762
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.923801187
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3676804849
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1294987441
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1075392266
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1569780092
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2026634781
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2084655478
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.313575237
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3730858884
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2886325352
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1746388088
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3785159640
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1869474884
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3861988945
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.944439151
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2632393553
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.380583864
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1458670756
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3242660153
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3946918548
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3181262034
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.202521757
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1298170782
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2476702394
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/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.496559378
/workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4123383459



Total test records in report: 1012
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1907357932 Feb 09 02:25:28 PM UTC 25 Feb 09 02:25:31 PM UTC 25 26134008 ps
T2 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.649856757 Feb 09 02:25:30 PM UTC 25 Feb 09 02:25:32 PM UTC 25 13088755 ps
T3 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.1141892126 Feb 09 02:25:28 PM UTC 25 Feb 09 02:25:32 PM UTC 25 213845390 ps
T4 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.459061290 Feb 09 02:25:30 PM UTC 25 Feb 09 02:25:33 PM UTC 25 67219365 ps
T5 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.345442756 Feb 09 02:25:30 PM UTC 25 Feb 09 02:25:39 PM UTC 25 298581304 ps
T12 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1964652615 Feb 09 02:25:30 PM UTC 25 Feb 09 02:25:40 PM UTC 25 445615752 ps
T6 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3771696667 Feb 09 02:25:30 PM UTC 25 Feb 09 02:25:41 PM UTC 25 338384586 ps
T13 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.1904144684 Feb 09 02:25:39 PM UTC 25 Feb 09 02:25:41 PM UTC 25 26799592 ps
T14 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1599280072 Feb 09 02:25:41 PM UTC 25 Feb 09 02:25:44 PM UTC 25 45276255 ps
T15 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.217528607 Feb 09 02:25:41 PM UTC 25 Feb 09 02:25:46 PM UTC 25 47697343 ps
T7 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3590903382 Feb 09 02:25:32 PM UTC 25 Feb 09 02:25:47 PM UTC 25 2519082424 ps
T16 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2061972405 Feb 09 02:25:30 PM UTC 25 Feb 09 02:25:47 PM UTC 25 426251825 ps
T8 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.444107714 Feb 09 02:25:32 PM UTC 25 Feb 09 02:25:47 PM UTC 25 4038583117 ps
T17 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1053011544 Feb 09 02:25:45 PM UTC 25 Feb 09 02:25:50 PM UTC 25 58528717 ps
T23 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3039977166 Feb 09 02:25:48 PM UTC 25 Feb 09 02:25:51 PM UTC 25 21639743 ps
T18 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.4238614103 Feb 09 02:25:31 PM UTC 25 Feb 09 02:25:51 PM UTC 25 2146270735 ps
T19 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2850647612 Feb 09 02:25:32 PM UTC 25 Feb 09 02:25:52 PM UTC 25 9906454234 ps
T31 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.1326293493 Feb 09 02:25:30 PM UTC 25 Feb 09 02:25:52 PM UTC 25 454717560 ps
T32 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.323816626 Feb 09 02:25:34 PM UTC 25 Feb 09 02:25:54 PM UTC 25 5550435305 ps
T33 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.998031189 Feb 09 02:25:34 PM UTC 25 Feb 09 02:25:54 PM UTC 25 1458216187 ps
T20 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2800746526 Feb 09 02:25:31 PM UTC 25 Feb 09 02:25:58 PM UTC 25 1182089329 ps
T43 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.786685757 Feb 09 02:25:43 PM UTC 25 Feb 09 02:25:59 PM UTC 25 113652950 ps
T9 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2910027308 Feb 09 02:25:54 PM UTC 25 Feb 09 02:25:59 PM UTC 25 520317527 ps
T21 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3808244620 Feb 09 02:25:52 PM UTC 25 Feb 09 02:26:00 PM UTC 25 2071751621 ps
T10 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3624798875 Feb 09 02:25:54 PM UTC 25 Feb 09 02:26:01 PM UTC 25 1594544728 ps
T231 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.2539987909 Feb 09 02:25:48 PM UTC 25 Feb 09 02:26:01 PM UTC 25 408242225 ps
T64 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3392506599 Feb 09 02:25:48 PM UTC 25 Feb 09 02:26:01 PM UTC 25 851735596 ps
T22 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3061021200 Feb 09 02:25:50 PM UTC 25 Feb 09 02:26:03 PM UTC 25 598009072 ps
T38 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2082841484 Feb 09 02:25:31 PM UTC 25 Feb 09 02:26:04 PM UTC 25 21215911763 ps
T96 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.1347317742 Feb 09 02:26:02 PM UTC 25 Feb 09 02:26:04 PM UTC 25 43548705 ps
T63 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.3267366938 Feb 09 02:25:36 PM UTC 25 Feb 09 02:26:52 PM UTC 25 887086723 ps
T41 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2218124914 Feb 09 02:25:47 PM UTC 25 Feb 09 02:26:06 PM UTC 25 3109807482 ps
T44 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.3628692062 Feb 09 02:25:52 PM UTC 25 Feb 09 02:26:07 PM UTC 25 1784934577 ps
T45 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.68830967 Feb 09 02:25:28 PM UTC 25 Feb 09 02:26:07 PM UTC 25 185553879 ps
T74 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.3907762363 Feb 09 02:26:04 PM UTC 25 Feb 09 02:26:08 PM UTC 25 119991198 ps
T42 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.2462337198 Feb 09 02:25:34 PM UTC 25 Feb 09 02:26:08 PM UTC 25 1236169426 ps
T34 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1898331789 Feb 09 02:26:08 PM UTC 25 Feb 09 02:26:10 PM UTC 25 27278413 ps
T103 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.1826020739 Feb 09 02:26:09 PM UTC 25 Feb 09 02:26:12 PM UTC 25 12949496 ps
T104 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2295282493 Feb 09 02:26:08 PM UTC 25 Feb 09 02:26:14 PM UTC 25 72788091 ps
T40 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3756703130 Feb 09 02:26:01 PM UTC 25 Feb 09 02:26:15 PM UTC 25 2817886106 ps
T93 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.897758969 Feb 09 02:26:08 PM UTC 25 Feb 09 02:26:17 PM UTC 25 435262446 ps
T232 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3463663384 Feb 09 02:26:08 PM UTC 25 Feb 09 02:26:17 PM UTC 25 841995464 ps
T252 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.259594807 Feb 09 02:26:09 PM UTC 25 Feb 09 02:26:17 PM UTC 25 758856304 ps
T53 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.3824805474 Feb 09 02:25:59 PM UTC 25 Feb 09 02:26:19 PM UTC 25 547506826 ps
T11 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.124763898 Feb 09 02:26:16 PM UTC 25 Feb 09 02:26:22 PM UTC 25 709070980 ps
T46 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.463045331 Feb 09 02:26:00 PM UTC 25 Feb 09 02:26:22 PM UTC 25 2610194008 ps
T62 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.919283445 Feb 09 02:26:12 PM UTC 25 Feb 09 02:26:27 PM UTC 25 472794003 ps
T243 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.1204167952 Feb 09 02:25:41 PM UTC 25 Feb 09 02:26:27 PM UTC 25 468042349 ps
T39 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2378755198 Feb 09 02:26:08 PM UTC 25 Feb 09 02:26:28 PM UTC 25 597034245 ps
T48 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_errors.4282414694 Feb 09 02:26:08 PM UTC 25 Feb 09 02:26:28 PM UTC 25 1176534943 ps
T247 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.674309144 Feb 09 02:26:16 PM UTC 25 Feb 09 02:26:28 PM UTC 25 485069249 ps
T47 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1049098465 Feb 09 02:26:20 PM UTC 25 Feb 09 02:26:30 PM UTC 25 1143146696 ps
T97 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3394684407 Feb 09 02:26:29 PM UTC 25 Feb 09 02:26:31 PM UTC 25 144945822 ps
T92 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2689505630 Feb 09 02:25:55 PM UTC 25 Feb 09 02:26:32 PM UTC 25 3910462606 ps
T35 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.769850082 Feb 09 02:26:30 PM UTC 25 Feb 09 02:26:32 PM UTC 25 26150112 ps
T253 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.678520765 Feb 09 02:26:30 PM UTC 25 Feb 09 02:26:34 PM UTC 25 39375994 ps
T54 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.2146404197 Feb 09 02:26:18 PM UTC 25 Feb 09 02:26:35 PM UTC 25 1296544452 ps
T254 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3633412979 Feb 09 02:26:33 PM UTC 25 Feb 09 02:26:37 PM UTC 25 29120679 ps
T68 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.247189543 Feb 09 02:26:02 PM UTC 25 Feb 09 02:26:40 PM UTC 25 2567138303 ps
T235 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3351481851 Feb 09 02:26:37 PM UTC 25 Feb 09 02:26:40 PM UTC 25 38056469 ps
T67 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.2889121169 Feb 09 02:26:35 PM UTC 25 Feb 09 02:26:42 PM UTC 25 874732559 ps
T255 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.857732477 Feb 09 02:26:32 PM UTC 25 Feb 09 02:26:43 PM UTC 25 268267458 ps
T76 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.44573612 Feb 09 02:26:18 PM UTC 25 Feb 09 02:26:44 PM UTC 25 661670621 ps
T209 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.56421505 Feb 09 02:26:18 PM UTC 25 Feb 09 02:26:45 PM UTC 25 4333712427 ps
T244 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.913727311 Feb 09 02:25:31 PM UTC 25 Feb 09 02:26:47 PM UTC 25 1409781057 ps
T256 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.392810502 Feb 09 02:26:23 PM UTC 25 Feb 09 02:26:49 PM UTC 25 2149893296 ps
T257 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.721352227 Feb 09 02:26:41 PM UTC 25 Feb 09 02:26:50 PM UTC 25 1070891007 ps
T24 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2680059247 Feb 09 02:26:46 PM UTC 25 Feb 09 02:26:51 PM UTC 25 260295604 ps
T258 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3502685280 Feb 09 02:26:33 PM UTC 25 Feb 09 02:26:53 PM UTC 25 574192640 ps
T259 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1700983437 Feb 09 02:26:44 PM UTC 25 Feb 09 02:26:53 PM UTC 25 373147275 ps
T260 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2796604418 Feb 09 02:26:49 PM UTC 25 Feb 09 02:26:55 PM UTC 25 593582878 ps
T261 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.4001681906 Feb 09 02:26:55 PM UTC 25 Feb 09 02:26:58 PM UTC 25 57051015 ps
T248 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.2220383620 Feb 09 02:26:43 PM UTC 25 Feb 09 02:26:58 PM UTC 25 1479002899 ps
T75 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3874100232 Feb 09 02:26:59 PM UTC 25 Feb 09 02:27:02 PM UTC 25 63735513 ps
T262 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.120395634 Feb 09 02:26:58 PM UTC 25 Feb 09 02:27:02 PM UTC 25 26851711 ps
T263 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.4287229274 Feb 09 02:26:08 PM UTC 25 Feb 09 02:27:03 PM UTC 25 715258976 ps
T249 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.474907760 Feb 09 02:26:11 PM UTC 25 Feb 09 02:27:04 PM UTC 25 2631714893 ps
T36 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.2598392931 Feb 09 02:26:52 PM UTC 25 Feb 09 02:27:05 PM UTC 25 1197117671 ps
T94 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.384081100 Feb 09 02:26:16 PM UTC 25 Feb 09 02:27:05 PM UTC 25 4742358357 ps
T233 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.380375881 Feb 09 02:26:36 PM UTC 25 Feb 09 02:27:08 PM UTC 25 374521339 ps
T236 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.1711587763 Feb 09 02:27:06 PM UTC 25 Feb 09 02:27:08 PM UTC 25 44358709 ps
T264 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3647067629 Feb 09 02:25:51 PM UTC 25 Feb 09 02:27:10 PM UTC 25 3677249708 ps
T265 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.2393249643 Feb 09 02:26:52 PM UTC 25 Feb 09 02:27:10 PM UTC 25 2809484970 ps
T266 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.689329020 Feb 09 02:27:04 PM UTC 25 Feb 09 02:27:10 PM UTC 25 331690747 ps
T95 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.1672625648 Feb 09 02:25:52 PM UTC 25 Feb 09 02:27:10 PM UTC 25 6334948003 ps
T250 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.288768678 Feb 09 02:26:50 PM UTC 25 Feb 09 02:27:11 PM UTC 25 3301096084 ps
T267 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.236054770 Feb 09 02:26:31 PM UTC 25 Feb 09 02:27:12 PM UTC 25 161293237 ps
T69 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.2816022908 Feb 09 02:26:29 PM UTC 25 Feb 09 02:27:13 PM UTC 25 118731148 ps
T268 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3964303660 Feb 09 02:27:09 PM UTC 25 Feb 09 02:27:14 PM UTC 25 656874983 ps
T269 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.307794791 Feb 09 02:27:03 PM UTC 25 Feb 09 02:27:15 PM UTC 25 324999613 ps
T70 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.2650116384 Feb 09 02:27:05 PM UTC 25 Feb 09 02:27:17 PM UTC 25 841956579 ps
T25 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.1841906091 Feb 09 02:27:11 PM UTC 25 Feb 09 02:27:18 PM UTC 25 384260435 ps
T100 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3044745817 Feb 09 02:26:01 PM UTC 25 Feb 09 02:27:19 PM UTC 25 11338413453 ps
T210 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.3261481272 Feb 09 02:27:06 PM UTC 25 Feb 09 02:27:20 PM UTC 25 446872380 ps
T270 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2854489786 Feb 09 02:27:11 PM UTC 25 Feb 09 02:27:22 PM UTC 25 321747506 ps
T271 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2196790724 Feb 09 02:27:12 PM UTC 25 Feb 09 02:27:22 PM UTC 25 1431474978 ps
T272 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2319919398 Feb 09 02:27:21 PM UTC 25 Feb 09 02:27:24 PM UTC 25 40906539 ps
T55 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.777962638 Feb 09 02:27:24 PM UTC 25 Feb 09 02:27:26 PM UTC 25 28638403 ps
T273 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3618184254 Feb 09 02:27:15 PM UTC 25 Feb 09 02:27:29 PM UTC 25 1187435898 ps
T274 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.1072402321 Feb 09 02:27:24 PM UTC 25 Feb 09 02:27:29 PM UTC 25 156830272 ps
T275 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3400932498 Feb 09 02:27:05 PM UTC 25 Feb 09 02:27:31 PM UTC 25 5077242449 ps
T276 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.866957787 Feb 09 02:26:49 PM UTC 25 Feb 09 02:27:32 PM UTC 25 3081796985 ps
T251 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2184875582 Feb 09 02:27:14 PM UTC 25 Feb 09 02:27:33 PM UTC 25 434848524 ps
T277 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.2025213652 Feb 09 02:27:11 PM UTC 25 Feb 09 02:27:33 PM UTC 25 538712322 ps
T37 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.3167595112 Feb 09 02:27:16 PM UTC 25 Feb 09 02:27:34 PM UTC 25 629349995 ps
T238 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.811619065 Feb 09 02:27:34 PM UTC 25 Feb 09 02:27:36 PM UTC 25 15867920 ps
T77 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.650712917 Feb 09 02:27:13 PM UTC 25 Feb 09 02:27:37 PM UTC 25 1982140105 ps
T278 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.816069255 Feb 09 02:27:30 PM UTC 25 Feb 09 02:27:37 PM UTC 25 184083634 ps
T245 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1942652727 Feb 09 02:27:27 PM UTC 25 Feb 09 02:27:37 PM UTC 25 101869689 ps
T101 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.113157609 Feb 09 02:26:54 PM UTC 25 Feb 09 02:27:37 PM UTC 25 116532139 ps
T71 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.857815495 Feb 09 02:27:31 PM UTC 25 Feb 09 02:27:41 PM UTC 25 991771009 ps
T279 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1727935397 Feb 09 02:27:30 PM UTC 25 Feb 09 02:27:44 PM UTC 25 1163864719 ps
T26 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.3439442148 Feb 09 02:27:38 PM UTC 25 Feb 09 02:27:47 PM UTC 25 1767042438 ps
T280 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.3213603843 Feb 09 02:27:34 PM UTC 25 Feb 09 02:27:48 PM UTC 25 611646280 ps
T281 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2916474264 Feb 09 02:27:02 PM UTC 25 Feb 09 02:27:49 PM UTC 25 168401081 ps
T282 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.9097494 Feb 09 02:27:38 PM UTC 25 Feb 09 02:27:51 PM UTC 25 1176523138 ps
T211 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.1817631537 Feb 09 02:27:34 PM UTC 25 Feb 09 02:27:54 PM UTC 25 242288350 ps
T78 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.4081281658 Feb 09 02:27:55 PM UTC 25 Feb 09 02:27:58 PM UTC 25 23269513 ps
T283 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.572612329 Feb 09 02:27:25 PM UTC 25 Feb 09 02:27:59 PM UTC 25 137426701 ps
T284 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.667870696 Feb 09 02:27:59 PM UTC 25 Feb 09 02:28:02 PM UTC 25 17343989 ps
T285 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.4089432494 Feb 09 02:27:48 PM UTC 25 Feb 09 02:28:02 PM UTC 25 946160825 ps
T286 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.3636290880 Feb 09 02:27:45 PM UTC 25 Feb 09 02:28:02 PM UTC 25 1498262254 ps
T287 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3206465564 Feb 09 02:28:00 PM UTC 25 Feb 09 02:28:03 PM UTC 25 14456852 ps
T288 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.3929427625 Feb 09 02:27:37 PM UTC 25 Feb 09 02:28:04 PM UTC 25 2475434194 ps
T289 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4206967798 Feb 09 02:27:42 PM UTC 25 Feb 09 02:28:06 PM UTC 25 1152998951 ps
T290 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3916983253 Feb 09 02:27:49 PM UTC 25 Feb 09 02:28:06 PM UTC 25 1828068730 ps
T246 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3970889282 Feb 09 02:28:02 PM UTC 25 Feb 09 02:28:08 PM UTC 25 597756310 ps
T291 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.618029956 Feb 09 02:28:07 PM UTC 25 Feb 09 02:28:09 PM UTC 25 62158736 ps
T292 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.2288914139 Feb 09 02:26:41 PM UTC 25 Feb 09 02:28:09 PM UTC 25 1598760053 ps
T293 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.4123563585 Feb 09 02:28:04 PM UTC 25 Feb 09 02:28:12 PM UTC 25 152889315 ps
T294 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3874534793 Feb 09 02:28:07 PM UTC 25 Feb 09 02:28:15 PM UTC 25 613033474 ps
T295 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.3581646658 Feb 09 02:28:10 PM UTC 25 Feb 09 02:28:17 PM UTC 25 116612799 ps
T49 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_errors.406490282 Feb 09 02:28:04 PM UTC 25 Feb 09 02:28:19 PM UTC 25 3699485546 ps
T65 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.410982100 Feb 09 02:28:04 PM UTC 25 Feb 09 02:28:19 PM UTC 25 324058831 ps
T296 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1300220390 Feb 09 02:28:05 PM UTC 25 Feb 09 02:28:19 PM UTC 25 245313931 ps
T212 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1656292248 Feb 09 02:28:16 PM UTC 25 Feb 09 02:28:21 PM UTC 25 670049679 ps
T297 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3066357441 Feb 09 02:27:11 PM UTC 25 Feb 09 02:28:21 PM UTC 25 9531491641 ps
T102 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3911456635 Feb 09 02:27:20 PM UTC 25 Feb 09 02:28:24 PM UTC 25 221879863 ps
T298 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.69620540 Feb 09 02:27:38 PM UTC 25 Feb 09 02:28:29 PM UTC 25 3446014410 ps
T299 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.168941282 Feb 09 02:28:26 PM UTC 25 Feb 09 02:28:29 PM UTC 25 20056428 ps
T300 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1917272186 Feb 09 02:28:19 PM UTC 25 Feb 09 02:28:31 PM UTC 25 1516888841 ps
T73 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3107441709 Feb 09 02:27:38 PM UTC 25 Feb 09 02:28:32 PM UTC 25 4419460223 ps
T301 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.2739712423 Feb 09 02:28:21 PM UTC 25 Feb 09 02:28:33 PM UTC 25 1799101902 ps
T302 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.365833595 Feb 09 02:28:31 PM UTC 25 Feb 09 02:28:33 PM UTC 25 18522130 ps
T86 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3196982725 Feb 09 02:28:31 PM UTC 25 Feb 09 02:28:36 PM UTC 25 45413598 ps
T303 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3826103754 Feb 09 02:28:33 PM UTC 25 Feb 09 02:28:36 PM UTC 25 80795378 ps
T304 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.880750031 Feb 09 02:28:10 PM UTC 25 Feb 09 02:28:37 PM UTC 25 2018398997 ps
T305 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.422381411 Feb 09 02:28:21 PM UTC 25 Feb 09 02:28:38 PM UTC 25 2194771625 ps
T239 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1065287265 Feb 09 02:28:37 PM UTC 25 Feb 09 02:28:40 PM UTC 25 16344978 ps
T98 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4237520671 Feb 09 02:26:02 PM UTC 25 Feb 09 02:28:40 PM UTC 25 19492801066 ps
T153 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2012860468 Feb 09 02:28:21 PM UTC 25 Feb 09 02:28:40 PM UTC 25 4524732940 ps
T154 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3282120858 Feb 09 02:28:21 PM UTC 25 Feb 09 02:28:41 PM UTC 25 3040697392 ps
T155 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1490245162 Feb 09 02:28:33 PM UTC 25 Feb 09 02:28:42 PM UTC 25 195967387 ps
T72 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.2456761289 Feb 09 02:28:35 PM UTC 25 Feb 09 02:28:47 PM UTC 25 1193170349 ps
T27 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1250522016 Feb 09 02:28:42 PM UTC 25 Feb 09 02:28:47 PM UTC 25 88343673 ps
T156 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3384977397 Feb 09 02:26:45 PM UTC 25 Feb 09 02:28:50 PM UTC 25 4426508031 ps
T157 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.4052572177 Feb 09 02:28:51 PM UTC 25 Feb 09 02:28:54 PM UTC 25 14820035 ps
T158 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.1987775362 Feb 09 02:28:37 PM UTC 25 Feb 09 02:28:51 PM UTC 25 217132408 ps
T159 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1509714512 Feb 09 02:27:09 PM UTC 25 Feb 09 02:28:53 PM UTC 25 64540973733 ps
T306 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1036978195 Feb 09 02:28:35 PM UTC 25 Feb 09 02:28:53 PM UTC 25 3104527494 ps
T307 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1358405541 Feb 09 02:28:39 PM UTC 25 Feb 09 02:28:54 PM UTC 25 546202269 ps
T308 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.3293001840 Feb 09 02:28:00 PM UTC 25 Feb 09 02:28:57 PM UTC 25 259748702 ps
T309 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3775359746 Feb 09 02:28:54 PM UTC 25 Feb 09 02:28:57 PM UTC 25 13468780 ps
T310 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3899881404 Feb 09 02:28:44 PM UTC 25 Feb 09 02:28:57 PM UTC 25 745895179 ps
T311 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.272628283 Feb 09 02:28:42 PM UTC 25 Feb 09 02:28:57 PM UTC 25 1861289915 ps
T312 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2832277339 Feb 09 02:28:58 PM UTC 25 Feb 09 02:29:01 PM UTC 25 25024407 ps
T313 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2350497664 Feb 09 02:28:47 PM UTC 25 Feb 09 02:29:01 PM UTC 25 300978989 ps
T314 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.937222735 Feb 09 02:28:55 PM UTC 25 Feb 09 02:29:02 PM UTC 25 179968944 ps
T315 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2733510374 Feb 09 02:28:49 PM UTC 25 Feb 09 02:29:04 PM UTC 25 269693290 ps
T316 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2944223218 Feb 09 02:29:02 PM UTC 25 Feb 09 02:29:04 PM UTC 25 13050423 ps
T317 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4031254995 Feb 09 02:28:54 PM UTC 25 Feb 09 02:29:05 PM UTC 25 472442441 ps
T318 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1727921256 Feb 09 02:28:49 PM UTC 25 Feb 09 02:29:06 PM UTC 25 384517738 ps
T319 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.4050972380 Feb 09 02:28:42 PM UTC 25 Feb 09 02:29:07 PM UTC 25 683141367 ps
T320 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2952762801 Feb 09 02:28:47 PM UTC 25 Feb 09 02:29:09 PM UTC 25 1062324378 ps
T321 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.3948353133 Feb 09 02:29:02 PM UTC 25 Feb 09 02:29:10 PM UTC 25 585976500 ps
T66 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3537966834 Feb 09 02:28:58 PM UTC 25 Feb 09 02:29:11 PM UTC 25 1512513532 ps
T322 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1045272326 Feb 09 02:28:58 PM UTC 25 Feb 09 02:29:12 PM UTC 25 601317510 ps
T323 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.4073963900 Feb 09 02:29:05 PM UTC 25 Feb 09 02:29:12 PM UTC 25 706461171 ps
T324 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_errors.3827217826 Feb 09 02:28:58 PM UTC 25 Feb 09 02:29:14 PM UTC 25 1438456127 ps
T28 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.2868168135 Feb 09 02:29:07 PM UTC 25 Feb 09 02:29:15 PM UTC 25 868331685 ps
T325 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.3273396202 Feb 09 02:29:15 PM UTC 25 Feb 09 02:29:18 PM UTC 25 52298979 ps
T326 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3633034189 Feb 09 02:29:15 PM UTC 25 Feb 09 02:29:20 PM UTC 25 631118345 ps
T327 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.2978903329 Feb 09 02:27:35 PM UTC 25 Feb 09 02:29:20 PM UTC 25 11723674492 ps
T328 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4123383459 Feb 09 02:29:18 PM UTC 25 Feb 09 02:29:21 PM UTC 25 21966745 ps
T329 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1313255840 Feb 09 02:29:05 PM UTC 25 Feb 09 02:29:21 PM UTC 25 1838908364 ps
T51 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.2261180323 Feb 09 02:28:12 PM UTC 25 Feb 09 02:29:22 PM UTC 25 1966195634 ps
T330 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.886944070 Feb 09 02:28:33 PM UTC 25 Feb 09 02:29:23 PM UTC 25 323784552 ps
T331 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.396978251 Feb 09 02:29:12 PM UTC 25 Feb 09 02:29:24 PM UTC 25 536481124 ps
T332 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.1801449015 Feb 09 02:29:08 PM UTC 25 Feb 09 02:29:25 PM UTC 25 1624883488 ps
T333 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1648574723 Feb 09 02:29:11 PM UTC 25 Feb 09 02:29:25 PM UTC 25 1025394046 ps
T334 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.294735349 Feb 09 02:29:12 PM UTC 25 Feb 09 02:29:27 PM UTC 25 661932867 ps
T335 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.614090816 Feb 09 02:29:22 PM UTC 25 Feb 09 02:29:27 PM UTC 25 136316755 ps
T237 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.936263236 Feb 09 02:29:25 PM UTC 25 Feb 09 02:29:27 PM UTC 25 156183850 ps
T79 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.1933186438 Feb 09 02:29:27 PM UTC 25 Feb 09 02:29:32 PM UTC 25 671125673 ps
T50 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2619104214 Feb 09 02:27:18 PM UTC 25 Feb 09 02:29:33 PM UTC 25 3458817123 ps
T336 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1848878286 Feb 09 02:28:42 PM UTC 25 Feb 09 02:29:34 PM UTC 25 5141391414 ps
T337 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.496559378 Feb 09 02:29:21 PM UTC 25 Feb 09 02:29:34 PM UTC 25 368412087 ps
T338 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.195032635 Feb 09 02:29:23 PM UTC 25 Feb 09 02:29:35 PM UTC 25 1067985350 ps
T339 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3071141303 Feb 09 02:28:55 PM UTC 25 Feb 09 02:29:37 PM UTC 25 231652990 ps
T340 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1442284439 Feb 09 02:29:33 PM UTC 25 Feb 09 02:29:37 PM UTC 25 171736627 ps
T29 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.2302091626 Feb 09 02:29:29 PM UTC 25 Feb 09 02:29:37 PM UTC 25 257231163 ps
T341 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_errors.256823604 Feb 09 02:29:22 PM UTC 25 Feb 09 02:29:39 PM UTC 25 1457216818 ps
T342 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.4281245114 Feb 09 02:29:28 PM UTC 25 Feb 09 02:29:40 PM UTC 25 326457967 ps
T343 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3868155161 Feb 09 02:29:38 PM UTC 25 Feb 09 02:29:40 PM UTC 25 16021841 ps
T344 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.1656357980 Feb 09 02:29:38 PM UTC 25 Feb 09 02:29:40 PM UTC 25 15078257 ps
T345 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1225000217 Feb 09 02:29:40 PM UTC 25 Feb 09 02:29:42 PM UTC 25 15944457 ps
T346 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1326207646 Feb 09 02:29:24 PM UTC 25 Feb 09 02:29:44 PM UTC 25 431190272 ps
T347 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3371994824 Feb 09 02:29:35 PM UTC 25 Feb 09 02:29:44 PM UTC 25 935938016 ps
T348 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3426230129 Feb 09 02:29:41 PM UTC 25 Feb 09 02:29:45 PM UTC 25 161577457 ps
T349 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2476702394 Feb 09 02:29:10 PM UTC 25 Feb 09 02:29:46 PM UTC 25 3055585849 ps
T350 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3922740390 Feb 09 02:29:35 PM UTC 25 Feb 09 02:29:47 PM UTC 25 1025576425 ps
T351 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.3459971231 Feb 09 02:29:35 PM UTC 25 Feb 09 02:29:48 PM UTC 25 1637996136 ps
T52 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.1400433531 Feb 09 02:29:05 PM UTC 25 Feb 09 02:29:53 PM UTC 25 24782123580 ps
T352 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1173316098 Feb 09 02:29:35 PM UTC 25 Feb 09 02:29:53 PM UTC 25 15464120360 ps
T353 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.997524237 Feb 09 02:28:39 PM UTC 25 Feb 09 02:29:53 PM UTC 25 2560331367 ps
T354 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.1781416802 Feb 09 02:28:09 PM UTC 25 Feb 09 02:29:54 PM UTC 25 8973244689 ps
T355 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3805557860 Feb 09 02:29:44 PM UTC 25 Feb 09 02:29:54 PM UTC 25 690652408 ps
T356 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.3739611560 Feb 09 02:29:21 PM UTC 25 Feb 09 02:29:54 PM UTC 25 738807853 ps
T357 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_errors.432204034 Feb 09 02:29:43 PM UTC 25 Feb 09 02:29:59 PM UTC 25 2217529469 ps
T358 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2440562325 Feb 09 02:29:41 PM UTC 25 Feb 09 02:29:59 PM UTC 25 58898743 ps
T359 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2589066038 Feb 09 02:30:00 PM UTC 25 Feb 09 02:30:02 PM UTC 25 118339948 ps
T360 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2113577379 Feb 09 02:29:48 PM UTC 25 Feb 09 02:30:02 PM UTC 25 585796451 ps
T240 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.52902851 Feb 09 02:29:44 PM UTC 25 Feb 09 02:30:02 PM UTC 25 352302680 ps
T87 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3074449794 Feb 09 02:30:00 PM UTC 25 Feb 09 02:30:03 PM UTC 25 17953338 ps
T361 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.3770312307 Feb 09 02:29:47 PM UTC 25 Feb 09 02:30:04 PM UTC 25 3736606333 ps
T362 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2765156263 Feb 09 02:29:28 PM UTC 25 Feb 09 02:30:05 PM UTC 25 3776484114 ps
T363 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2819758930 Feb 09 02:30:03 PM UTC 25 Feb 09 02:30:05 PM UTC 25 22217921 ps
T59 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.801424798 Feb 09 02:25:34 PM UTC 25 Feb 09 02:30:06 PM UTC 25 23215450998 ps
T364 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3110562715 Feb 09 02:29:56 PM UTC 25 Feb 09 02:30:08 PM UTC 25 491975093 ps
T365 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.4189539575 Feb 09 02:29:54 PM UTC 25 Feb 09 02:30:08 PM UTC 25 288507156 ps
T366 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1981334217 Feb 09 02:26:23 PM UTC 25 Feb 09 02:30:09 PM UTC 25 18151705701 ps
T30 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1326207563 Feb 09 02:29:54 PM UTC 25 Feb 09 02:30:09 PM UTC 25 1532370634 ps
T367 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.721921940 Feb 09 02:30:05 PM UTC 25 Feb 09 02:30:10 PM UTC 25 121631517 ps
T368 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.2566587753 Feb 09 02:30:09 PM UTC 25 Feb 09 02:30:13 PM UTC 25 287738532 ps
T369 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.1824790426 Feb 09 02:29:41 PM UTC 25 Feb 09 02:30:13 PM UTC 25 200272006 ps
T370 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1844120782 Feb 09 02:30:06 PM UTC 25 Feb 09 02:30:13 PM UTC 25 216875539 ps
T371 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.3389055726 Feb 09 02:30:03 PM UTC 25 Feb 09 02:30:17 PM UTC 25 264946136 ps
T372 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.1710788599 Feb 09 02:30:05 PM UTC 25 Feb 09 02:30:17 PM UTC 25 424161976 ps
T373 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1390717595 Feb 09 02:30:11 PM UTC 25 Feb 09 02:30:18 PM UTC 25 494398989 ps
T374 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.3486627024 Feb 09 02:30:06 PM UTC 25 Feb 09 02:30:19 PM UTC 25 258181208 ps
T375 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1671227834 Feb 09 02:29:54 PM UTC 25 Feb 09 02:30:21 PM UTC 25 870445526 ps
T376 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.1887414073 Feb 09 02:30:18 PM UTC 25 Feb 09 02:30:21 PM UTC 25 16000840 ps
T377 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2721171487 Feb 09 02:30:19 PM UTC 25 Feb 09 02:30:22 PM UTC 25 21116481 ps
T378 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3662943263 Feb 09 02:29:03 PM UTC 25 Feb 09 02:30:22 PM UTC 25 5039742964 ps
T379 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1136173860 Feb 09 02:30:11 PM UTC 25 Feb 09 02:30:22 PM UTC 25 531679557 ps
T380 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2428674481 Feb 09 02:30:18 PM UTC 25 Feb 09 02:30:25 PM UTC 25 134822180 ps
T381 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.469528967 Feb 09 02:26:53 PM UTC 25 Feb 09 02:30:25 PM UTC 25 18052176883 ps
T382 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.502723778 Feb 09 02:30:07 PM UTC 25 Feb 09 02:30:27 PM UTC 25 619647706 ps
T383 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.1888681599 Feb 09 02:29:28 PM UTC 25 Feb 09 02:30:27 PM UTC 25 1352718476 ps
T384 /workspaces/repo/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.1259178510 Feb 09 02:30:22 PM UTC 25 Feb 09 02:30:28 PM UTC 25 66097367 ps
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