Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::sec_token_mux_idx_error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_q	8	0	8	100.00	100	1	1	0

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_states[ClkMuxSt]	481	1			T39	13		T34	7		T48	3
fsm_states[CntIncrSt]	463	1			T39	11		T34	11		T48	7
fsm_states[CntProgSt]	438	1			T39	6		T34	7		T48	11
fsm_states[TransCheckSt]	458	1			T39	15		T34	8		T48	8
fsm_states[FlashRmaSt]	439	1			T39	8		T34	7		T48	7
fsm_states[TokenHashSt]	500	1			T39	11		T34	19		T48	7
fsm_states[TokenCheck0St]	436	1			T39	12		T34	8		T48	6
fsm_states[TokenCheck1St]	458	1			T39	10		T34	9		T48	10