OTBN Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: 042415198f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 0 1 0.00
V1 single_binary otbn_single 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 26.307us 5 5 100.00
V1 csr_rw otbn_csr_rw 10.000s 24.129us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 18.000s 296.481us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 8.000s 31.805us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 10.000s 25.345us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 10.000s 24.129us 20 20 100.00
otbn_csr_aliasing 8.000s 31.805us 5 5 100.00
V1 mem_walk otbn_mem_walk 21.000s 235.381us 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 14.000s 238.307us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 0 10 0.00
V2 multi_error otbn_multi_err 0 1 0.00
V2 back_to_back otbn_multi 0 10 0.00
V2 stress_all otbn_stress_all 0 10 0.00
V2 lc_escalation otbn_escalate 0 60 0.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 0 5 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 0 10 0.00
V2 alert_test otbn_alert_test 11.000s 16.843us 50 50 100.00
V2 intr_test otbn_intr_test 10.000s 21.311us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 12.000s 126.255us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 12.000s 126.255us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 26.307us 5 5 100.00
otbn_csr_rw 10.000s 24.129us 20 20 100.00
otbn_csr_aliasing 8.000s 31.805us 5 5 100.00
otbn_same_csr_outstanding 10.000s 78.215us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 26.307us 5 5 100.00
otbn_csr_rw 10.000s 24.129us 20 20 100.00
otbn_csr_aliasing 8.000s 31.805us 5 5 100.00
otbn_same_csr_outstanding 10.000s 78.215us 20 20 100.00
V2 TOTAL 140 246 56.91
V2S mem_integrity otbn_imem_err 0 10 0.00
otbn_dmem_err 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 0 5 0.00
otbn_controller_ispr_rdata_err 0 5 0.00
otbn_mac_bignum_acc_err 0 5 0.00
otbn_urnd_err 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 0 5 0.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 0 2 0.00
V2S tl_intg_err otbn_sec_cm 5.867m 14.086ms 5 5 100.00
otbn_tl_intg_err 1.167m 650.106us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 39.000s 217.346us 20 20 100.00
V2S prim_fsm_check otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S prim_count_check otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_mem_scramble otbn_smoke 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 0 10 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 1.167m 650.106us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 0 60 0.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 0 10 0.00
otbn_dmem_err 0 15 0.00
otbn_zero_state_err_urnd 0 5 0.00
otbn_illegal_mem_acc 0 5 0.00
otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_scramble_key_sideload otbn_single 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 0 10 0.00
otbn_dmem_err 0 15 0.00
otbn_zero_state_err_urnd 0 5 0.00
otbn_illegal_mem_acc 0 5 0.00
otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 0 60 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 0 10 0.00
otbn_dmem_err 0 15 0.00
otbn_zero_state_err_urnd 0 5 0.00
otbn_illegal_mem_acc 0 5 0.00
otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 0 5 0.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 0 7 0.00
V2S sec_cm_data_mem_sec_wipe otbn_single 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 0 5 0.00
V2S sec_cm_key_sideload otbn_single 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 5.867m 14.086ms 5 5 100.00
V2S TOTAL 45 153 29.41
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 250 575 43.48

Testplan Progress

Items Total Written Passing Progress
V1 9 9 7 77.78
V2 11 11 4 36.36
V2S 19 19 3 15.79
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.19 97.10 62.64 96.38 73.08 51.02 51.28 75.85 96.64

Failure Buckets

Past Results