OTP_CTRL Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: `3df77bec1`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.930s	63.143us	1	1	100.00
V1	smoke	otp_ctrl_smoke	11.840s	1.117ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.540s	366.090us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.290s	604.437us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.910s	1.630ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.130s	129.738us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.660s	175.834us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.290s	604.437us	20	20	100.00
		otp_ctrl_csr_aliasing	4.130s	129.738us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.520s	506.361us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.360s	48.788us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.720s	3.109ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.460s	2.890ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	23.040s	2.640ms	10	10	100.00
		otp_ctrl_check_fail	32.240s	13.608ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	10.740s	4.300ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	26.300s	10.648ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	30.240s	10.081ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	27.610s	10.370ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	15.320s	1.400ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	35.330s	15.938ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	49.800s	5.627ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.192m	79.290ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.960s	533.263us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.370s	313.698us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.100s	2.775ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.100s	2.775ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.540s	366.090us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	604.437us	20	20	100.00
		otp_ctrl_csr_aliasing	4.130s	129.738us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.070s	456.619us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.540s	366.090us	5	5	100.00
		otp_ctrl_csr_rw	2.290s	604.437us	20	20	100.00
		otp_ctrl_csr_aliasing	4.130s	129.738us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.070s	456.619us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
		otp_ctrl_tl_intg_err	37.340s	18.831ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	37.340s	18.831ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	11.840s	1.117ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	11.840s	1.117ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
		otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
		otp_ctrl_macro_errs	35.330s	15.938ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
		otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
		otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
		otp_ctrl_macro_errs	35.330s	15.938ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	14.450s	5.052ms	200	200	100.00
		otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.460s	2.890ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	32.240s	13.608ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	26.300s	10.648ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	26.300s	10.648ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	26.300s	10.648ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	26.300s	10.648ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	26.300s	10.648ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	11.840s	1.117ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	26.300s	10.648ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	11.840s	1.117ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.146m	130.973ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	10.740s	4.300ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	11.840s	1.117ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	11.840s	1.117ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	35.330s	15.938ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.290s	5.952ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.964h	571.240ms	95	100	95.00
V3		TOTAL			96	101	95.05
		TOTAL			1338	1343	99.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.22	92.63	91.24	92.05	91.55	93.29	96.53	95.27

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 22.otp_ctrl_stress_all_with_rand_reset.732389195
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4126c678-e4f3-43e8-bdb2-6c755f4a1188
```
  - 38.otp_ctrl_stress_all_with_rand_reset.3272594198
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d7f580f8-d032-4d1e-a18a-48f1de085fc2
```
  - ... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:449) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5430776) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }

has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

4.otp_ctrl_stress_all_with_rand_reset.2490449260
Line 484, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 511929296216 ps: (cip_base_scoreboard.sv:449) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@5430776) { a_addr: 'h4d848998  a_data: 'haf8ef498  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h52  a_opcode: 'h4  a_user: 'h271b1  d_param: 'h0  d_source: 'h52  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 511929296216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---