Unified Coverage Report :: Module :: otp_ctrl_lci

Module : otp_ctrl_lci

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.40	94.23	83.33		77.78	91.67	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lci	89.40	94.23	83.33		77.78	91.67	100.00

---

Module Instance : tb.dut.u_otp_ctrl_lci

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.40	94.23	83.33		77.78	91.67	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.42	95.08	83.33	100.00	77.78	92.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	95.77	87.62	85.09		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_lci

	Line No.	Total	Covered	Percent
TOTAL		52	49	94.23
CONT_ASSIGN	114	1	1	100.00
ALWAYS	117	41	38	92.68
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	267	1	1	100.00
ALWAYS	273	3	3	100.00
ALWAYS	276	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
114	1	1
117	1	1
120	1	1
121	1	1
124	1	1
127	1	1
128	1	1
131	1	1
132	1	1
135	1	1
136	1	1
138	1	1
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
150	1	1
151	1	1
152	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
172	1	1
173	1	1
179	1	1
180	0	1
			MISSING_ELSE
185	1	1
186	1	1
187	1	1
190	1	1
191	0	1
192	0	1
			MISSING_ELSE
196	1	1
197	1	1
			MISSING_ELSE
206	1	1
207	1	1
			MISSING_ELSE
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
			MISSING_ELSE
			MISSING_ELSE
257	1	1
263	1	1
264	1	1
267	1	1
273	3	3
276	1	1
277	1	1
279	1	1

---

Cond Coverage for Module : otp_ctrl_lci

	Total	Covered	Percent
Conditions	12	10	83.33
Logical	12	10	83.33
Non-Logical	0	0
Event	0	0

 LINE       179
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Not Covered

 LINE       185
 EXPRESSION (cnt == LastLcOtpWord)
            -----------1----------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T19,T20,T21

 LINE       190
 EXPRESSION (error_d != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Not Covered

 LINE       206
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T27,T28

 LINE       225
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T19,T26

 LINE       264
 EXPRESSION (otp_req_o ? (64'(data[cnt])) : '0)
             ----1----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T19,T20,T21

---

FSM Coverage for Module : otp_ctrl_lci

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	7	77.78
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	192	Covered	T29
IdleSt	144	Covered	T29
ResetSt	141	Covered	T29
WriteSt	151	Covered	T29
WriteWaitSt	164	Covered	T29

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	223	Covered	T29
IdleSt->WriteSt	151	Covered	T29
ResetSt->ErrorSt	223	Covered	T29
ResetSt->IdleSt	144	Covered	T29
WriteSt->ErrorSt	223	Not Covered
WriteSt->WriteWaitSt	164	Covered	T29
WriteWaitSt->ErrorSt	192	Not Covered
WriteWaitSt->IdleSt	186	Covered	T29
WriteWaitSt->WriteSt	196	Covered	T29

---

Branch Coverage for Module : otp_ctrl_lci

	Line No.	Total	Covered	Percent
Branches		24	22	91.67
TERNARY	264	2	2	100.00
CASE	138	15	13	86.67
IF	222	3	3	100.00
IF	273	2	2	100.00
IF	276	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lci.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	264	(otp_req_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	138	case (state_q)
-2-:	143	if (lci_en_i)
-3-:	150	if (lc_req_i)
-4-:	163	if (otp_gnt_i)
-5-:	173	if (otp_rvalid_i)
-6-:	179	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	185	if ((cnt == LastLcOtpWord))
-8-:	190	if ((error_d != NoError))
-9-:	206	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	-	0	-	-	-	-	-	-	Covered	T18,T19,T20
WriteSt	-	-	1	-	-	-	-	-	Covered	T19,T20,T21
WriteSt	-	-	0	-	-	-	-	-	Covered	T35,T38,T42
WriteWaitSt	-	-	-	1	1	-	-	-	Not Covered
WriteWaitSt	-	-	-	1	0	-	-	-	Covered	T19,T20,T21
WriteWaitSt	-	-	-	1	-	1	1	-	Not Covered
WriteWaitSt	-	-	-	1	-	1	0	-	Covered	T19,T20,T21
WriteWaitSt	-	-	-	1	-	0	-	-	Covered	T19,T20,T21
WriteWaitSt	-	-	-	0	-	-	-	-	Covered	T19,T20,T21
ErrorSt	-	-	-	-	-	-	-	1	Covered	T18,T27,T28
ErrorSt	-	-	-	-	-	-	-	0	Covered	T18,T19,T26
default	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	222	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	225	if ((error_q == NoError))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T26
1	0	Covered	T18,T19,T26
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	273	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	276	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

---

Assert Coverage for Module : otp_ctrl_lci

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorKnown_A	1570944001	1569874661	0	0
LcAckKnown_A	1570944001	1569874661	0	0
LcErrKnown_A	1570944001	1569874661	0	0
LcValueMustBeWiderThanNativeOtpWidth_A	1168	1168	0	0
LciIdleKnown_A	1570944001	1569874661	0	0
OtpAddrKnown_A	1570944001	1569874661	0	0
OtpCmdKnown_A	1570944001	1569874661	0	0
OtpReqKnown_A	1570944001	1569874661	0	0
OtpSizeKnown_A	1570944001	1569874661	0	0
OtpWdataKnown_A	1570944001	1569874661	0	0
u_state_regs_A	1570944001	1569874661	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

LcAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

LcErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

LcValueMustBeWiderThanNativeOtpWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

LciIdleKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0