Unified Coverage Report :: Module :: otp_ctrl

Module : otp_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.94	95.77	87.62	84.36		96.97	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	93.09	95.77	87.62	85.09		96.97	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.09	95.77	87.62	85.09		96.97	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.01	91.02	88.86	82.89	67.89	91.20	94.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
core_tlul_assert_device	99.18	100.00				100.00	97.55
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
gen_alert_tx[2].u_prim_alert_sender	100.00			100.00
gen_alert_tx[3].u_prim_alert_sender	100.00			100.00
gen_alert_tx[4].u_prim_alert_sender	77.78			77.78
gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[0].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[1].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[2].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[3].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[4].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[5].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
gen_bufs[6].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_read_lock	79.17	37.50				100.00	100.00
gen_bufs[7].u_prim_mubi8_sender_write_lock	79.17	37.50				100.00	100.00
gen_partitions[0].gen_unbuffered.u_part_unbuf	90.10	97.66	87.23	86.52	79.17	92.86	97.14
gen_partitions[1].gen_unbuffered.u_part_unbuf	88.02	93.13	86.49	96.45	66.67	91.07	94.29
gen_partitions[2].gen_unbuffered.u_part_unbuf	88.02	93.13	86.49	96.45	66.67	91.07	94.29
gen_partitions[3].gen_buffered.u_part_buf	74.49	79.90	77.36	67.18	62.07	74.39	86.05
gen_partitions[4].gen_buffered.u_part_buf	83.74	89.15	77.97	94.30	63.89	81.61	95.56
gen_partitions[5].gen_buffered.u_part_buf	82.74	89.15	77.97	88.26	63.89	81.61	95.56
gen_partitions[6].gen_buffered.u_part_buf	82.37	89.15	77.97	86.04	63.89	81.61	95.56
gen_partitions[7].gen_lifecycle.u_part_buf	68.88	65.87	64.52	69.32	61.90	68.75	82.93
otp_ctrl_core_csr_assert	7.69						7.69
prim_tlul_assert_device	99.18	100.00				100.00	97.55
u_edn_arb	87.10	92.31	62.75			100.00	93.33
u_intr_error	100.00	100.00	100.00			100.00	100.00
u_intr_operation_done	100.00	100.00	100.00			100.00	100.00
u_keygmr_key_valid	100.00	100.00				100.00
u_otp	94.08	91.72	88.79	93.24	100.00	90.71	100.00
u_otp_arb	93.92	93.01	88.94			100.00	93.75
u_otp_ctrl_dai	88.17	90.73	93.06	100.00	68.42	90.43	86.36
u_otp_ctrl_kdi	91.73	98.43	96.51	100.00	63.64	94.44	97.37
u_otp_ctrl_lci	91.42	95.08	83.33	100.00	77.78	92.31	100.00
u_otp_ctrl_lfsr_timer	91.04	100.00	88.75	76.92	88.89	91.67	100.00
u_otp_ctrl_scrmbl	91.62	81.50	100.00	100.00	70.00	98.21	100.00
u_otp_init_sync	100.00	100.00				100.00
u_otp_rsp_fifo	94.70	100.00	78.79			100.00	100.00
u_part_sel_idx	81.55	73.91	98.44			100.00	53.85
u_prim_edn_req	92.19	100.00	93.75			100.00	75.00
u_prim_lc_sender_rma_token_valid	100.00	100.00				100.00
u_prim_lc_sender_secrets_valid	100.00	100.00				100.00
u_prim_lc_sender_test_tokens_valid	100.00	100.00				100.00
u_prim_lc_sync_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_creator_seed_sw_rw_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_seed_hw_rd_en	100.00	100.00				100.00	100.00
u_reg_core	99.28	99.59	96.83	100.00		100.00	100.00
u_scrmbl_mtx	76.66	83.33	79.54			100.00	43.75
u_tlul_adapter_sram	91.72	89.54	84.55			92.77	100.00
u_tlul_lc_gate	86.31	95.45	100.00		57.14	91.43	87.50

Line Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
TOTAL		142	136	95.77
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
ALWAYS	265	14	13	92.86
ALWAYS	289	3	3	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	3	3	100.00
ALWAYS	421	20	20	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
ALWAYS	841	2	2	100.00
ALWAYS	899	2	2	100.00
ALWAYS	926	4	4	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	956	3	3	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1095	1	0	0.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1265	1	0	0.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1356	1	1	100.00
CONT_ASSIGN	1388	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
235	8	8
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
273	0	1
			MISSING_ELSE
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
289	1	1
290	1	1
292	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
310	1	1
320	1	1
324	1	1
325	1	1
329	1	1
330	1	1
			MISSING_ELSE
332	1	1
333	1	1
			MISSING_ELSE
335	1	1
336	1	1
			MISSING_ELSE
339	1	1
340	1	1
			MISSING_ELSE
375	1	1
379	1	1
383	1	1
384	1	1
385	1	1
387	1	1
395	1	1
396	1	1
399	1	1
400	1	1
402	1	1
421	1	1
424	1	1
425	1	1
426	1	1
428	1	1
430	1	1
433	1	1
435	1	1
438	1	1
439	1	1
			MISSING_ELSE
443	1	1
445	1	1
449	1	1
452	1	1
454	1	1
459	1	1
460	1	1
			MISSING_ELSE
462	1	1
463	1	1
			MISSING_ELSE
468	1	1
475	1	1
488	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
550	1	1
558	1	1
605	1	1
607	1	1
730	1	1
731	1	1
732	1	1
762	1	1
764	1	1
841	1	1
842	1	1
899	1	1
900	1	1
926	1	1
927	1	1
928	1	1
929	1	1
953	1	1
956	1	1
957	1	1
959	1	1
1008	1	1
1010	1	1
1044	1	1
1095	0	1
1150	3	3
1205	1	4
1265	0	1
1277	1	1
1300	1	1
1301	1	1
1304	1	1
1305	1	1
1306	1	1
1311	1	1
1334	1	1
1335	1	1
1337	1	1
1339	1	1
1343	1	1
1345	1	1
1347	1	1
1352	1	1
1354	1	1
1356	1	1
1388	1	1
1390	1	1
1394	1	1
1398	1	1
1402	1	1

---

Cond Coverage for Module : otp_ctrl

	Total	Covered	Percent
Conditions	105	92	87.62
Logical	105	92	87.62
Non-Logical	0	0
Event	0	0

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T20

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T21

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T18,T19,T20

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T23,T24,T25

 LINE       269
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T18,T19,T20

 LINE       278
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Not Covered
1	0	Covered	T18,T19,T20

 LINE       279
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Not Covered
1	0	Covered	T18,T19,T20

 LINE       375
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T18,T19,T20
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       395
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T19,T20,T21
1	1	Covered	T18,T19,T20

 LINE       426
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T27,T28
1	0	Not Covered

 LINE       435
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       439
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       459
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T26,T32
1	0	Covered	T19,T54,T23

 LINE       468
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T18,T19,T20
0	0	0	1	Covered	T18,T19,T26
0	0	1	0	Covered	T18,T27,T28
0	1	0	0	Covered	T18,T27,T28
1	0	0	0	Covered	T23,T24,T25

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       605
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T18,T19,T20
1	1	Covered	T20,T21,T22

 LINE       607
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T18,T19,T20
1	1	Covered	T20,T21,T22

 LINE       730
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T20

 LINE       731
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T18,T19,T20

 LINE       732
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T20

 LINE       842
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T18,T19,T20

 LINE       1300
 EXPRESSION (part_init_done[HwCfgIdx] ? On : Off)
             ------------1-----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       1304
 EXPRESSION (part_digest[Secret2Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1334
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1352
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1352
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1354
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1354
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1356
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1356
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

---

Toggle Coverage for Module : otp_ctrl

	Total	Covered	Percent
Totals	145	121	83.45
Total Bits	9412	7940	84.36
Total Bits 0->1	4706	3974	84.45
Total Bits 1->0	4706	3966	84.28

Ports	145	121	83.45
Port Bits	9412	7940	84.36
Port Bits 0->1	4706	3974	84.45
Port Bits 1->0	4706	3966	84.28

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	INPUT
clk_edn_i	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
rst_edn_ni	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	INPUT
edn_o.edn_req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
edn_i.edn_fips	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
edn_i.edn_ack	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
core_tl_i.d_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_valid	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_o.a_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T81,T11	Yes	T29,T81,T11	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T29,*T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T29,*T81,*T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_valid	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_o.a_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
prim_tl_o.d_error	Yes	Yes	T29,T81,T1	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_user.data_intg[6:0]	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	OUTPUT
prim_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T29,T81,T1	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T29,*T81,*T1	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
intr_otp_error_o	Yes	Yes	T29,T11,T13	Yes	T29,T11,T13	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
pwr_otp_i.otp_init	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	No	No		No		OUTPUT
lc_otp_program_i.count[0]	No	No		No		INPUT
lc_otp_program_i.count[1]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[2]	No	No		No		INPUT
lc_otp_program_i.count[3]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[5:4]	No	No		No		INPUT
lc_otp_program_i.count[8:6]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[9]	No	No		No		INPUT
lc_otp_program_i.count[11:10]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[12]	No	No		No		INPUT
lc_otp_program_i.count[13]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[14]	No	No		No		INPUT
lc_otp_program_i.count[15]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[16]	No	No		No		INPUT
lc_otp_program_i.count[19:17]	Yes	Yes	*T54,*T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[21:20]	No	No		No		INPUT
lc_otp_program_i.count[23:22]	Yes	Yes	*T54,*T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[24]	No	No		No		INPUT
lc_otp_program_i.count[25]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[26]	No	No		No		INPUT
lc_otp_program_i.count[27]	Yes	Yes	*T54,*T55,*T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[28]	No	No		No		INPUT
lc_otp_program_i.count[29]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[30]	No	No		No		INPUT
lc_otp_program_i.count[31]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[33:32]	No	No		No		INPUT
lc_otp_program_i.count[35:34]	Yes	Yes	T54,T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[36]	No	No		No		INPUT
lc_otp_program_i.count[38:37]	Yes	Yes	*T54,*T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[39]	No	No		No		INPUT
lc_otp_program_i.count[43:40]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[45:44]	No	No		No		INPUT
lc_otp_program_i.count[46]	Yes	Yes	*T54,*T55,*T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[48:47]	No	No		No		INPUT
lc_otp_program_i.count[53:49]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[55:54]	No	No		No		INPUT
lc_otp_program_i.count[58:56]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[59]	No	No		No		INPUT
lc_otp_program_i.count[60]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[63:61]	No	No		No		INPUT
lc_otp_program_i.count[64]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[65]	No	No		No		INPUT
lc_otp_program_i.count[67:66]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[68]	No	No		No		INPUT
lc_otp_program_i.count[69]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[70]	No	No		No		INPUT
lc_otp_program_i.count[77:71]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[79:78]	No	No		No		INPUT
lc_otp_program_i.count[81:80]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[82]	No	No		No		INPUT
lc_otp_program_i.count[86:83]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[87]	No	No		No		INPUT
lc_otp_program_i.count[90:88]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[91]	No	No		No		INPUT
lc_otp_program_i.count[92]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[93]	No	No		No		INPUT
lc_otp_program_i.count[94]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[95]	No	No		No		INPUT
lc_otp_program_i.count[98:96]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[99]	No	No		No		INPUT
lc_otp_program_i.count[105:100]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[106]	No	No		No		INPUT
lc_otp_program_i.count[111:107]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[112]	No	No		No		INPUT
lc_otp_program_i.count[113]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[116:114]	No	No		No		INPUT
lc_otp_program_i.count[118:117]	Yes	Yes	T54,T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[119]	No	No		No		INPUT
lc_otp_program_i.count[120]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[121]	No	No		No		INPUT
lc_otp_program_i.count[123:122]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[126:124]	No	No		No		INPUT
lc_otp_program_i.count[134:127]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[136:135]	No	No		No		INPUT
lc_otp_program_i.count[137]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[138]	No	No		No		INPUT
lc_otp_program_i.count[140:139]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[145:141]	No	No		No		INPUT
lc_otp_program_i.count[147:146]	Yes	Yes	T54,T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[148]	No	No		No		INPUT
lc_otp_program_i.count[150:149]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[151]	No	No		No		INPUT
lc_otp_program_i.count[155:152]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[157:156]	No	No		No		INPUT
lc_otp_program_i.count[164:158]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[166:165]	No	No		No		INPUT
lc_otp_program_i.count[167]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[168]	No	No		No		INPUT
lc_otp_program_i.count[174:169]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[176:175]	No	No		No		INPUT
lc_otp_program_i.count[177]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[179:178]	No	No		No		INPUT
lc_otp_program_i.count[184:180]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[186:185]	No	No		No		INPUT
lc_otp_program_i.count[187]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[189:188]	No	No		No		INPUT
lc_otp_program_i.count[190]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[192:191]	No	No		No		INPUT
lc_otp_program_i.count[193]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[195:194]	No	No		No		INPUT
lc_otp_program_i.count[202:196]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[203]	No	No		No		INPUT
lc_otp_program_i.count[204]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[206:205]	No	No		No		INPUT
lc_otp_program_i.count[212:207]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[213]	No	No		No		INPUT
lc_otp_program_i.count[214]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[216:215]	No	No		No		INPUT
lc_otp_program_i.count[217]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[219:218]	No	No		No		INPUT
lc_otp_program_i.count[222:220]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[223]	No	No		No		INPUT
lc_otp_program_i.count[224]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[225]	No	No		No		INPUT
lc_otp_program_i.count[226]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[229:227]	No	No		No		INPUT
lc_otp_program_i.count[232:230]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[234:233]	No	No		No		INPUT
lc_otp_program_i.count[235]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[236]	No	No		No		INPUT
lc_otp_program_i.count[237]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[238]	No	No		No		INPUT
lc_otp_program_i.count[241:239]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[244:242]	No	No		No		INPUT
lc_otp_program_i.count[251:245]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[253:252]	No	No		No		INPUT
lc_otp_program_i.count[258:254]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[259]	No	No		No		INPUT
lc_otp_program_i.count[263:260]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[265:264]	No	No		No		INPUT
lc_otp_program_i.count[268:266]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[269]	No	No		No		INPUT
lc_otp_program_i.count[270]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[272:271]	No	No		No		INPUT
lc_otp_program_i.count[275:273]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[276]	No	No		No		INPUT
lc_otp_program_i.count[285:277]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[286]	No	No		No		INPUT
lc_otp_program_i.count[287]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T22,T34	INPUT
lc_otp_program_i.count[288]	No	No		No		INPUT
lc_otp_program_i.count[290:289]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[291]	No	No		No		INPUT
lc_otp_program_i.count[292]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[293]	No	No		No		INPUT
lc_otp_program_i.count[297:294]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[299:298]	No	No		No		INPUT
lc_otp_program_i.count[300]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[301]	No	No		No		INPUT
lc_otp_program_i.count[303:302]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[304]	No	No		No		INPUT
lc_otp_program_i.count[305]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[306]	No	No		No		INPUT
lc_otp_program_i.count[311:307]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[313:312]	No	No		No		INPUT
lc_otp_program_i.count[317:314]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[318]	No	No		No		INPUT
lc_otp_program_i.count[321:319]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[329:322]	No	No		No		INPUT
lc_otp_program_i.count[331:330]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[332]	No	No		No		INPUT
lc_otp_program_i.count[333]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[335:334]	No	No		No		INPUT
lc_otp_program_i.count[336]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[337]	No	No		No		INPUT
lc_otp_program_i.count[340:338]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[341]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[343:342]	No	No		No		INPUT
lc_otp_program_i.count[344]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[345]	No	No		No		INPUT
lc_otp_program_i.count[350:346]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[351]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[353:352]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[354]	No	No		No		INPUT
lc_otp_program_i.count[355]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[357:356]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[358]	No	No		No		INPUT
lc_otp_program_i.count[359]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[362:360]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[363]	No	No		No		INPUT
lc_otp_program_i.count[364]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[365]	No	No		No		INPUT
lc_otp_program_i.count[366]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[368:367]	No	No		No		INPUT
lc_otp_program_i.count[369]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[370]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[371]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[372]	No	No		No		INPUT
lc_otp_program_i.count[374:373]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[375]	No	No		No		INPUT
lc_otp_program_i.count[379:376]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[380]	No	No		No		INPUT
lc_otp_program_i.count[382:381]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[383]	No	No		No		INPUT
lc_otp_program_i.state[3:0]	No	No		No		INPUT
lc_otp_program_i.state[6:4]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[7]	No	No		No		INPUT
lc_otp_program_i.state[9:8]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[10]	No	No		No		INPUT
lc_otp_program_i.state[13:11]	Yes	Yes	*T54,*T55,*T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[15:14]	No	No		No		INPUT
lc_otp_program_i.state[21:16]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[22]	No	No		No		INPUT
lc_otp_program_i.state[25:23]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[26]	No	No		No		INPUT
lc_otp_program_i.state[32:27]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[33]	No	No		No		INPUT
lc_otp_program_i.state[34]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[37:35]	No	No		No		INPUT
lc_otp_program_i.state[39:38]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[43:40]	No	No		No		INPUT
lc_otp_program_i.state[46:44]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[50:47]	No	No		No		INPUT
lc_otp_program_i.state[51]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[53:52]	No	No		No		INPUT
lc_otp_program_i.state[55:54]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[58:56]	No	No		No		INPUT
lc_otp_program_i.state[59]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[60]	No	No		No		INPUT
lc_otp_program_i.state[67:61]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[69:68]	No	No		No		INPUT
lc_otp_program_i.state[70]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[71]	No	No		No		INPUT
lc_otp_program_i.state[73:72]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[74]	No	No		No		INPUT
lc_otp_program_i.state[77:75]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[78]	No	No		No		INPUT
lc_otp_program_i.state[80:79]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[81]	No	No		No		INPUT
lc_otp_program_i.state[84:82]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[85]	No	No		No		INPUT
lc_otp_program_i.state[93:86]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[94]	No	No		No		INPUT
lc_otp_program_i.state[96:95]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[97]	No	No		No		INPUT
lc_otp_program_i.state[101:98]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[102]	No	No		No		INPUT
lc_otp_program_i.state[104:103]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[107:105]	No	No		No		INPUT
lc_otp_program_i.state[110:108]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[112:111]	No	No		No		INPUT
lc_otp_program_i.state[113]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[117:114]	No	No		No		INPUT
lc_otp_program_i.state[120:118]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[121]	No	No		No		INPUT
lc_otp_program_i.state[122]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[123]	No	No		No		INPUT
lc_otp_program_i.state[131:124]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[132]	No	No		No		INPUT
lc_otp_program_i.state[136:133]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[137]	No	No		No		INPUT
lc_otp_program_i.state[138]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[139]	No	No		No		INPUT
lc_otp_program_i.state[141:140]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[142]	No	No		No		INPUT
lc_otp_program_i.state[146:143]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[147]	No	No		No		INPUT
lc_otp_program_i.state[149:148]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[150]	No	No		No		INPUT
lc_otp_program_i.state[151]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[154:152]	No	No		No		INPUT
lc_otp_program_i.state[156:155]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[159:157]	No	No		No		INPUT
lc_otp_program_i.state[163:160]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[165:164]	No	No		No		INPUT
lc_otp_program_i.state[170:166]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[172:171]	No	No		No		INPUT
lc_otp_program_i.state[173]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[174]	No	No		No		INPUT
lc_otp_program_i.state[175]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[176]	No	No		No		INPUT
lc_otp_program_i.state[177]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[178]	No	No		No		INPUT
lc_otp_program_i.state[181:179]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[182]	No	No		No		INPUT
lc_otp_program_i.state[183]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[184]	No	No		No		INPUT
lc_otp_program_i.state[186:185]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[188:187]	No	No		No		INPUT
lc_otp_program_i.state[190:189]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[191]	No	No		No		INPUT
lc_otp_program_i.state[197:192]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[198]	No	No		No		INPUT
lc_otp_program_i.state[200:199]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[201]	No	No		No		INPUT
lc_otp_program_i.state[203:202]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[204]	No	No		No		INPUT
lc_otp_program_i.state[206:205]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[207]	No	No		No		INPUT
lc_otp_program_i.state[210:208]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[211]	No	No		No		INPUT
lc_otp_program_i.state[216:212]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[218:217]	No	No		No		INPUT
lc_otp_program_i.state[219]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[222:220]	No	No		No		INPUT
lc_otp_program_i.state[226:223]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[227]	No	No		No		INPUT
lc_otp_program_i.state[230:228]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[231]	No	No		No		INPUT
lc_otp_program_i.state[234:232]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[238:235]	No	No		No		INPUT
lc_otp_program_i.state[241:239]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[243:242]	No	No		No		INPUT
lc_otp_program_i.state[259:244]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[262:260]	No	No		No		INPUT
lc_otp_program_i.state[263]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[265:264]	No	No		No		INPUT
lc_otp_program_i.state[267:266]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[268]	No	No		No		INPUT
lc_otp_program_i.state[270:269]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[276:271]	No	No		No		INPUT
lc_otp_program_i.state[278:277]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[280:279]	No	No		No		INPUT
lc_otp_program_i.state[281]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[282]	No	No		No		INPUT
lc_otp_program_i.state[287:283]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[288]	No	No		No		INPUT
lc_otp_program_i.state[293:289]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[294]	No	No		No		INPUT
lc_otp_program_i.state[295]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[297:296]	No	No		No		INPUT
lc_otp_program_i.state[298]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[302:299]	No	No		No		INPUT
lc_otp_program_i.state[303]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[304]	No	No		No		INPUT
lc_otp_program_i.state[305]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[306]	No	No		No		INPUT
lc_otp_program_i.state[307]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[308]	No	No		No		INPUT
lc_otp_program_i.state[314:309]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[315]	No	No		No		INPUT
lc_otp_program_i.state[318:316]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[319]	No	No		No		INPUT
lc_otp_program_i.req	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
lc_otp_program_o.ack	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
lc_otp_program_o.err	No	No		No		OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T49,T64,T65	Yes	T49,T64,T65	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
otp_lc_data_o.rma_token[1:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[2]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[4:3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[5]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[9:6]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[13:10]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[15:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[18:16]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[19]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[20]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[22:21]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[24:23]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[26:25]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[27]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[28]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[31:29]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[32]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[33]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[41:34]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[42]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[51:43]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[52]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[54:53]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.rma_token[55]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[66:56]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[67]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[85:68]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.rma_token[86]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[91:87]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.rma_token[92]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[127:93]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.test_exit_token[82:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.test_exit_token[83]	No	No		No		OUTPUT
otp_lc_data_o.test_exit_token[127:84]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[10:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[15:12]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[16]	No	No		No		OUTPUT
otp_lc_data_o.count[27:17]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[28]	No	No		No		OUTPUT
otp_lc_data_o.count[31:29]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[32]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[61:43]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[64:62]	No	No		No		OUTPUT
otp_lc_data_o.count[78:65]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[88:80]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[89]	No	No		No		OUTPUT
otp_lc_data_o.count[100:90]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[102:101]	No	No		No		OUTPUT
otp_lc_data_o.count[104:103]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[118:106]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[121:120]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[134:123]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[142:136]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[150:144]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[158:152]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[159]	No	No		No		OUTPUT
otp_lc_data_o.count[174:160]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[177:175]	No	No		No		OUTPUT
otp_lc_data_o.count[186:178]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[187]	No	No		No		OUTPUT
otp_lc_data_o.count[188]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[189]	No	No		No		OUTPUT
otp_lc_data_o.count[194:190]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[195]	No	No		No		OUTPUT
otp_lc_data_o.count[196]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[215:198]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[226:219]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[227]	No	No		No		OUTPUT
otp_lc_data_o.count[228]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[240:230]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[243:242]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[245:244]	No	No		No		OUTPUT
otp_lc_data_o.count[265:246]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[266]	No	No		No		OUTPUT
otp_lc_data_o.count[274:267]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[285:276]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[286]	No	No		No		OUTPUT
otp_lc_data_o.count[316:287]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[317]	No	No		No		OUTPUT
otp_lc_data_o.count[335:318]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[337:336]	No	No		No		OUTPUT
otp_lc_data_o.count[338]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[339]	No	No		No		OUTPUT
otp_lc_data_o.count[343:340]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[375:345]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[376]	No	No		No		OUTPUT
otp_lc_data_o.count[383:377]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[12:7]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[19:14]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[20]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[31:23]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[36:33]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[46:38]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[48:47]	No	No		No		OUTPUT
otp_lc_data_o.state[52:49]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[65:54]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[68:67]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[69]	No	No		No		OUTPUT
otp_lc_data_o.state[77:70]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[78]	No	No		No		OUTPUT
otp_lc_data_o.state[79]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[84:81]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[85]	No	No		No		OUTPUT
otp_lc_data_o.state[98:86]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[99]	No	No		No		OUTPUT
otp_lc_data_o.state[103:100]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[114:105]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[115]	No	No		No		OUTPUT
otp_lc_data_o.state[131:116]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[132]	No	No		No		OUTPUT
otp_lc_data_o.state[134:133]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[136]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[146:138]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[152:148]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[154:153]	No	No		No		OUTPUT
otp_lc_data_o.state[157:155]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[158]	No	No		No		OUTPUT
otp_lc_data_o.state[165:159]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[166]	No	No		No		OUTPUT
otp_lc_data_o.state[177:167]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[181:179]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[184:182]	No	No		No		OUTPUT
otp_lc_data_o.state[187:185]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[188]	No	No		No		OUTPUT
otp_lc_data_o.state[191:189]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[192]	No	No		No		OUTPUT
otp_lc_data_o.state[199:193]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[200]	No	No		No		OUTPUT
otp_lc_data_o.state[206:201]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[214:208]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[219:216]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[220]	No	No		No		OUTPUT
otp_lc_data_o.state[230:221]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[236:235]	No	No		No		OUTPUT
otp_lc_data_o.state[241:237]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[242]	No	No		No		OUTPUT
otp_lc_data_o.state[243]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[277:248]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[278]	No	No		No		OUTPUT
otp_lc_data_o.state[279]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[280]	No	No		No		OUTPUT
otp_lc_data_o.state[301:281]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[306:303]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[307]	No	No		No		OUTPUT
otp_lc_data_o.state[311:308]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[312]	No	No		No		OUTPUT
otp_lc_data_o.state[319:313]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.error	Yes	Yes	T18,T19,T26	Yes	T18,T19,T26	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[2:0]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[7:4]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[8]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[9]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[11:10]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[12]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[16:13]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[18:17]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[20:19]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[21]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[26:22]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[28:27]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[29]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[30]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[32:31]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[34:33]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[36:35]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[41:37]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[42]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[43]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[45:44]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[48:46]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[49]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[50]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[51]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[55:52]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[56]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[59:57]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[60]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[61]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[71:62]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[72]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[76:73]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[77]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[81:78]	Yes	Yes	*T42,*T44,*T50	Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[82]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[87:83]	Yes	Yes	*T42,*T44,*T50	Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[88]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[92:89]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[93]	No	No		Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[94]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[95]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[97:96]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[100:98]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[101]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[103:102]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[105:104]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[108:106]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[109]	No	Yes	*T31,*T33,*T48	No		OUTPUT
otp_keymgr_key_o.key_share1[110]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[111]	No	No		Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[122:112]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[123]	No	No		Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[124]	No	Yes	*T31,*T33,*T48	No		OUTPUT
otp_keymgr_key_o.key_share1[125]	Yes	Yes	*T31,*T33,*T48	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[126]	No	Yes	*T31,*T33,*T48	No		OUTPUT
otp_keymgr_key_o.key_share1[127]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[128]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[129]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[130]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[131]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[132]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[137:133]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[139:138]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[140]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[141]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[143:142]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[146:144]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[147]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[151:148]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[152]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[153]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[155:154]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[156]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[157]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[158]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[171:159]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[172]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[176:173]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[177]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[182:178]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[183]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[186:184]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[187]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[188]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[189]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[192:190]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[193]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[194]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[196:195]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[199:197]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[200]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[201]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[208:202]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[210:209]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[211]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[213:212]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[214]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[221:215]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[222]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[223]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[224]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[227:225]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[228]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[230:229]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[231]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[238:232]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[239]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[243:240]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[245:244]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[247:246]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[250:248]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[254:251]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[255]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[2:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[3]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[4]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[5]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[9:6]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[10]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[11]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[12]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[17:13]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[18]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[29:19]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[31:30]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[38:32]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[39]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[48:40]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[50:49]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[53:51]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[54]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[56:55]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[57]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[61:58]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[62]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[64:63]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[65]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[71:66]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[72]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[74:73]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[75]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[78:76]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[79]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[80]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[81]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[88:82]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[89]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[90]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[91]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[94:92]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[95]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[96]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[97]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[104:98]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[106:105]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[113:107]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[119:114]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[130:120]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[131]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[134:132]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[135]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[138:136]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[139]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[145:140]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[146]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[148:147]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[149]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[156:150]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[157]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[159:158]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[160]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[170:161]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[171]	No	No		Yes	T20,T22,T34	OUTPUT
otp_keymgr_key_o.key_share0[178:172]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[179]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[180]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[181]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[190:182]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[191]	No	No		Yes	T20,T22,T34	OUTPUT
otp_keymgr_key_o.key_share0[194:192]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[199:195]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[201:200]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[205:202]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[206]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[207]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[208]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[210:209]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[212:211]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[214:213]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[216:215]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[217]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[219:218]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[222:220]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[223]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[225:224]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[227:226]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[228]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[229]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[232:230]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[233]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[235:234]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[240:236]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[245:241]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[248:246]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[249]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[250]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[251]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[254:252]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[255]	No	No		No		OUTPUT
otp_keymgr_key_o.valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
flash_otp_key_i.data_req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
sram_otp_key_i[1].req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
sram_otp_key_i[2].req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T20,T22,T31	Yes	T20,T22,T31	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_hw_cfg_o.data.device_id[41:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[42]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[43]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[44]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[47:45]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[49:48]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[52:50]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[53]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[56:54]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[57]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[58]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[59]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[64:60]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[65]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[73:66]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[74]	No	No		Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.device_id[85:75]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[86]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[87]	No	No		Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.device_id[91:88]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[92]	No	No		Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.device_id[96:93]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[97]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[103:98]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[104]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[108:105]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[111:109]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[114:112]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[115]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[122:116]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
otp_hw_cfg_o.data.device_id[123]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[162:124]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[163]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[164]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[165]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[169:166]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[170]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[177:171]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[180:178]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[188:181]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[190:189]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[195:191]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[196]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[204:197]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
otp_hw_cfg_o.data.device_id[205]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[224:206]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[227:225]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[228]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[229]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[234:230]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[237:235]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[241:238]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[242]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[245:243]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[255:246]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[1:0]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[3:2]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[7:5]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[8]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[15:9]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[16]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[18:17]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[19]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[21:20]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[22]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[38:23]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[39]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[64:40]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[65]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[74:66]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
otp_hw_cfg_o.data.manuf_state[76:75]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[95:77]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[96]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[100:97]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[101]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[106:102]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[108:107]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[130:109]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[131]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[133:132]	Yes	Yes	*T42,*T44,*T89	Yes	T53,T92,T42	OUTPUT
otp_hw_cfg_o.data.manuf_state[134]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[145:135]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[146]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[154:147]	Yes	Yes	*T42,*T44,*T50	Yes	T53,T92,T42	OUTPUT
otp_hw_cfg_o.data.manuf_state[155]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[156]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
otp_hw_cfg_o.data.manuf_state[157]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[162:158]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
otp_hw_cfg_o.data.manuf_state[163]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[176:164]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[177]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[184:178]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	OUTPUT
otp_hw_cfg_o.data.manuf_state[185]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[187:186]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	OUTPUT
otp_hw_cfg_o.data.manuf_state[189:188]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[196:190]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[197]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[198]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[199]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[201:200]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[202]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[212:203]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[213]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[216:214]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[217]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[221:218]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[222]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[231:223]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[233:232]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[242:234]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[243]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[249:244]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[250]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[255:251]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[3:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[6:5]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[7]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[1]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[7:2]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[2:1]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[6:3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[7]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[2:1]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[6:5]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[7]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[2:0]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[3]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[5]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[8:6]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[11:9]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[13:12]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[16:14]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[17]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[18]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[22:19]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[23]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[24]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[27:25]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[28]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[31:29]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.hw_cfg_digest[63:0]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.valid[3:0]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
scan_rst_ni	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
scanmode_i[3:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
cio_test_o[7:0]	No	No		No		OUTPUT
cio_test_en_o[7:0]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : otp_ctrl

	Line No.	Total	Covered	Percent
Branches		33	32	96.97
TERNARY	1300	2	2	100.00
TERNARY	1352	2	2	100.00
TERNARY	1354	2	2	100.00
TERNARY	1356	2	2	100.00
IF	268	3	2	66.67
IF	289	2	2	100.00
IF	329	2	2	100.00
IF	332	2	2	100.00
IF	335	2	2	100.00
IF	339	2	2	100.00
IF	399	2	2	100.00
IF	438	2	2	100.00
IF	459	2	2	100.00
IF	462	2	2	100.00
IF	499	2	2	100.00
IF	956	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1300	(part_init_done[HwCfgIdx]) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1352	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1354	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1356	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	268	if (tlul_req)
-2-:	269	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T20
1	0	Not Covered
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	289	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	329	if ((!reg2hw.vendor_test_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	332	if ((!reg2hw.creator_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	if ((!reg2hw.owner_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T49
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	339	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	399	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	438	if (otp_ctrl_part_pkg::PartInfo[k].ecc_fatal)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	459	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T26
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	462	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T26
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	499	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	956	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

---

Assert Coverage for Module : otp_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	64	64	100.00	64	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	64	64	100.00	64	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1570944001	1569874661	0	0
CoreTlOutKnown_A	1570944001	1569874661	0	0
CreatorRootKeyShare0Size_A	1168	1168	0	0
CreatorRootKeyShare1Size_A	1168	1168	0	0
ErrorCodeWidth_A	1168	1168	0	0
FlashAddrKeySeedSize_A	1168	1168	0	0
FlashDataKeySeedSize_A	1168	1168	0	0
FlashOtpKeyRspKnown_A	1570944001	1569874661	0	0
FpvSecCmCntCnstyCheck_A	1570944001	50	0	0
FpvSecCmCntDaiCheck_A	1570944001	50	0	0
FpvSecCmCntIntegCheck_A	1570944001	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1570944001	50	0	0
FpvSecCmCntKdiSeedCheck_A	1570944001	50	0	0
FpvSecCmCntLciCheck_A	1570944001	50	0	0
FpvSecCmCntScrmblCheck_A	1570944001	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1570944001	50	0	0
FpvSecCmDoubleLfsrCheck_A	1570944001	50	0	0
FpvSecCmRegWeOnehotCheck_A	1570944001	50	0	0
FpvSecCmTlLcGateFsm_A	1570944001	50	0	0
IntrOtpErrorKnown_A	1570944001	1569874661	0	0
IntrOtpOperationDoneKnown_A	1570944001	1569874661	0	0
LcOtpProgramRspKnown_A	1570944001	1569874661	0	0
LcSeedHwRdEnStable_A	1570944001	2650	0	0
LcStateSize_A	1168	1168	0	0
LcTransitionCntSize_A	1168	1168	0	0
OtpAstPwrSeqKnown_A	1570944001	1569874661	0	0
OtpErrorCode0_A	1168	1168	0	0
OtpErrorCode1_A	1168	1168	0	0
OtpErrorCode2_A	1168	1168	0	0
OtpErrorCode3_A	1168	1168	0	0
OtpErrorCode4_A	1168	1168	0	0
OtpHwCfgKnown_A	1570944001	1569874661	0	0
OtpIfWidth_A	1168	1168	0	0
OtpKeymgrKeyKnown_A	1570944001	1569874661	0	0
OtpLcDataKnown_A	1570944001	1569874661	0	0
OtpOtgnKeyKnown_A	1570944001	1569874661	0	0
OtpRespFifoUnderflow_A	1570944001	1326224	0	0
OtpSramKeyKnown_A	1570944001	1569874661	0	0
PartSelMustBeOnehot_A	1570944001	1569874661	0	0
PrimTlOutKnown_A	1570944001	1569874661	0	0
PwrOtpInitRspKnown_A	1570944001	1569874661	0	0
RmaTokenSize_A	1168	1168	0	0
SramDataKeySeedSize_A	1168	1168	0	0
TestExitTokenSize_A	1168	1168	0	0
TestUnlockTokenSize_A	1168	1168	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1570944001	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1570944001	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1570944001	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1570944001	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1570944001	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1570944001	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1570944001	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

LcSeedHwRdEnStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	2650	0	0
T20	54961	5	0	0
T21	34632	3	0	0
T22	54961	5	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	1	0	0
T32	15666	0	0	0
T33	13744	1	0	0
T34	0	5	0	0
T36	0	3	0	0
T47	15666	0	0	0
T48	13744	1	0	0
T52	0	1	0	0
T53	0	1	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpHwCfgKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1326224	0	0
T18	853907	15652	0	0
T19	38999	238	0	0
T20	54961	807	0	0
T21	34632	720	0	0
T22	54961	807	0	0
T26	15666	197	0	0
T30	7104	52	0	0
T31	13744	303	0	0
T32	15666	197	0	0
T33	13744	303	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		142	136	95.77
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
CONT_ASSIGN	235	1	1	100.00
ALWAYS	265	14	13	92.86
ALWAYS	289	3	3	100.00
CONT_ASSIGN	302	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	307	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
ALWAYS	320	11	11	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	383	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
ALWAYS	399	3	3	100.00
ALWAYS	421	20	20	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	496	1	1	100.00
ALWAYS	499	9	9	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	605	1	1	100.00
CONT_ASSIGN	607	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
ALWAYS	841	2	2	100.00
ALWAYS	899	2	2	100.00
ALWAYS	926	4	4	100.00
CONT_ASSIGN	953	1	1	100.00
ALWAYS	956	3	3	100.00
CONT_ASSIGN	1008	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1044	1	1	100.00
CONT_ASSIGN	1095	1	0	0.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1150	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1205	1	0	0.00
CONT_ASSIGN	1265	1	0	0.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1339	1	1	100.00
CONT_ASSIGN	1343	1	1	100.00
CONT_ASSIGN	1345	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1354	1	1	100.00
CONT_ASSIGN	1356	1	1	100.00
CONT_ASSIGN	1388	1	1	100.00
CONT_ASSIGN	1390	1	1	100.00
CONT_ASSIGN	1394	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
235	8	8
265	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
273	0	1
			MISSING_ELSE
278	1	1
279	1	1
280	1	1
281	1	1
282	1	1
283	1	1
284	1	1
289	1	1
290	1	1
292	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
310	1	1
320	1	1
324	1	1
325	1	1
329	1	1
330	1	1
			MISSING_ELSE
332	1	1
333	1	1
			MISSING_ELSE
335	1	1
336	1	1
			MISSING_ELSE
339	1	1
340	1	1
			MISSING_ELSE
375	1	1
379	1	1
383	1	1
384	1	1
385	1	1
387	1	1
395	1	1
396	1	1
399	1	1
400	1	1
402	1	1
421	1	1
424	1	1
425	1	1
426	1	1
428	1	1
430	1	1
433	1	1
435	1	1
438	1	1
439	1	1
			MISSING_ELSE
443	1	1
445	1	1
449	1	1
452	1	1
454	1	1
459	1	1
460	1	1
			MISSING_ELSE
462	1	1
463	1	1
			MISSING_ELSE
468	1	1
475	1	1
488	1	1
496	1	1
499	1	1
500	1	1
501	1	1
502	1	1
503	1	1
505	1	1
506	1	1
507	1	1
508	1	1
550	1	1
558	1	1
605	1	1
607	1	1
730	1	1
731	1	1
732	1	1
762	1	1
764	1	1
841	1	1
842	1	1
899	1	1
900	1	1
926	1	1
927	1	1
928	1	1
929	1	1
953	1	1
956	1	1
957	1	1
959	1	1
1008	1	1
1010	1	1
1044	1	1
1095	0	1
1150	3	3
1205	1	4
1265	0	1
1277	1	1
1300	1	1
1301	1	1
1304	1	1
1305	1	1
1306	1	1
1311	1	1
1334	1	1
1335	1	1
1337	1	1
1339	1	1
1343	1	1
1345	1	1
1347	1	1
1352	1	1
1354	1	1
1356	1	1
1388	1	1
1390	1	1
1394	1	1
1398	1	1
1402	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	105	92	87.62
Logical	105	92	87.62
Non-Logical	0	0
Event	0	0

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b0) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[0].PartEnd))
             --------------1-------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T20

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b00001000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[1].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T21

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b01101100000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[2].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T18,T19,T20

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11010000000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[3].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[4].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11011111000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[5].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11101010000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[6].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       235
 EXPRESSION (({tlul_addr, 2'b0} >= 11'b11110101000) & ({1'b0, {tlul_addr, 2'b0}} < gen_part_sel[7].PartEnd))
             -------------------1------------------   --------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T23,T24,T25

 LINE       269
 EXPRESSION (tlul_part_sel_oh != '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T18,T19,T20

 LINE       278
 EXPRESSION (((|part_tlul_gnt)) | tlul_oob_err_q)
             ---------1--------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Not Covered
1	0	Covered	T18,T19,T20

 LINE       279
 EXPRESSION (((|part_tlul_rvalid)) | tlul_oob_err_q)
             ----------1----------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Not Covered
1	0	Covered	T18,T19,T20

 LINE       375
 EXPRESSION (reg2hw.direct_access_cmd.digest.qe | reg2hw.direct_access_cmd.wr.qe | reg2hw.direct_access_cmd.rd.qe)
             -----------------1----------------   ---------------2--------------   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T18,T19,T20
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       395
 EXPRESSION (lci_prog_idle & dai_prog_idle)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T19,T20,T21
1	1	Covered	T18,T19,T20

 LINE       426
 EXPRESSION (fatal_bus_integ_error_q | ((|intg_error)))
             -----------1-----------   -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T27,T28
1	0	Not Covered

 LINE       435
 EXPRESSION (part_error[k] == MacroError)
            --------------1--------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       439
 EXPRESSION (part_error[k] == MacroEccUncorrError)
            -------------------1------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       459
 EXPRESSION (fatal_macro_error_q || fatal_check_error_q)
             ---------1---------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T26,T32
1	0	Covered	T19,T54,T23

 LINE       468
 EXPRESSION (chk_timeout | lfsr_fsm_err | scrmbl_fsm_err | ((|part_fsm_err)))
             -----1-----   ------2-----   -------3------   --------4--------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T18,T19,T20
0	0	0	1	Covered	T18,T19,T26
0	0	1	0	Covered	T18,T27,T28
0	1	0	0	Covered	T18,T27,T28
1	0	0	0	Covered	T23,T24,T25

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_otp_alert.q & reg2hw.alert_test.recov_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_otp_alert.q & reg2hw.alert_test.fatal_prim_otp_alert.qe)
                 --------------------1-------------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_bus_integ_error.q & reg2hw.alert_test.fatal_bus_integ_error.qe)
                 --------------------1--------------------   ---------------------2--------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_check_error.q & reg2hw.alert_test.fatal_check_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       558
 SUB-EXPRESSION (reg2hw.alert_test.fatal_macro_error.q & reg2hw.alert_test.fatal_macro_error.qe)
                 ------------------1------------------   -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T90,T91
1	0	Covered	T18,T19,T20
1	1	Covered	T30,T90,T91

 LINE       605
 EXPRESSION (reg2hw.check_trigger.integrity.q & reg2hw.check_trigger.integrity.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T18,T19,T20
1	1	Covered	T20,T21,T22

 LINE       607
 EXPRESSION (reg2hw.check_trigger.consistency.q & reg2hw.check_trigger.consistency.qe)
             -----------------1----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T22
1	0	Covered	T18,T19,T20
1	1	Covered	T20,T21,T22

 LINE       730
 EXPRESSION (otp_prim_ready & otp_rsp_fifo_ready)
             -------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T20

 LINE       731
 EXPRESSION (otp_arb_valid & otp_rsp_fifo_ready)
             ------1------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T18,T19,T20

 LINE       732
 EXPRESSION (otp_prim_ready & otp_prim_valid)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T20
1	1	Covered	T18,T19,T20

 LINE       842
 EXPRESSION (otp_rvalid & otp_fifo_valid)
             -----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T18,T19,T20

 LINE       1300
 EXPRESSION (part_init_done[HwCfgIdx] ? On : Off)
             ------------1-----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       1304
 EXPRESSION (part_digest[Secret2Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1334
 EXPRESSION (part_digest[Secret1Idx] != '0)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1352
 EXPRESSION ((part_digest[Secret0Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1352
 SUB-EXPRESSION (part_digest[Secret0Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1354
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1354
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1356
 EXPRESSION ((part_digest[Secret2Idx] != '0) ? On : Off)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       1356
 SUB-EXPRESSION (part_digest[Secret2Idx] != '0)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	141	120	85.11
Total Bits	9308	7920	85.09
Total Bits 0->1	4654	3964	85.17
Total Bits 1->0	4654	3956	85.00

Ports	141	120	85.11
Port Bits	9308	7920	85.09
Port Bits 0->1	4654	3964	85.17
Port Bits 1->0	4654	3956	85.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	INPUT
clk_edn_i	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
rst_edn_ni	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	INPUT
edn_o.edn_req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
edn_i.edn_fips	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
edn_i.edn_ack	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
core_tl_i.d_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.data_intg[6:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.instr_type[3:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_data[31:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_mask[3:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_address[31:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_source[7:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_size[1:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
core_tl_i.a_opcode[2:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_i.a_valid	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
core_tl_o.a_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
core_tl_o.d_user.data_intg[6:0]	Yes	Yes	T29,T81,T11	Yes	T29,T81,T11	OUTPUT
core_tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T29,*T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_data[31:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_source[7:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_size[1:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_opcode[0]	Yes	Yes	*T29,*T81,*T1	Yes	T29,T81,T1	OUTPUT
core_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
core_tl_o.d_valid	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
prim_tl_i.d_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
prim_tl_i.a_user.data_intg[6:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
prim_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_data[31:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_mask[3:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_address[31:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_source[7:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_size[1:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
prim_tl_i.a_opcode[2:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_i.a_valid	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	INPUT
prim_tl_o.a_ready	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
prim_tl_o.d_error	Yes	Yes	T29,T81,T1	Yes	T1,T2,T3	OUTPUT
prim_tl_o.d_user.data_intg[0]	Excluded	Excluded	*T81,*T12,*T2	Excluded	T81,T12,T2	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[1]	Yes	Yes	*T81,*T12,*T2	Yes	T81,T12,T2	OUTPUT
prim_tl_o.d_user.data_intg[2]	Excluded	Excluded	*T81,*T12,*T2	Excluded	T81,T12,T2	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[3]	Yes	Yes	*T81,*T12,*T2	Yes	T81,T12,T2	OUTPUT
prim_tl_o.d_user.data_intg[4]	Excluded	Excluded	*T81,*T12,*T2	Excluded	T81,T12,T2	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.data_intg[5]	Yes	Yes	*T81,*T12,*T2	Yes	T81,T12,T2	OUTPUT
prim_tl_o.d_user.data_intg[6]	Excluded	Excluded	T81,T12,T2	Excluded	T81,T12,T2	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[5:0]	Excluded	Excluded	T81,T1,T12	Excluded	T81,T1,T12	OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
prim_tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_data[31:0]	Yes	Yes	T29,T81,T1	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_source[7:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_size[1:0]	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_opcode[0]	Yes	Yes	*T29,*T81,*T1	Yes	T81,T1,T12	OUTPUT
prim_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
prim_tl_o.d_valid	Yes	Yes	T81,T1,T12	Yes	T81,T1,T12	OUTPUT
intr_otp_operation_done_o	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
intr_otp_error_o	Yes	Yes	T29,T11,T13	Yes	T29,T11,T13	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	INPUT
alert_rx_i[2].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[2].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	INPUT
alert_rx_i[3].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[3].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ack_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
alert_rx_i[4].ack_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	INPUT
alert_rx_i[4].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[4].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T81,T12,T2	Yes	T81,T12,T2	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	OUTPUT
alert_tx_o[4].alert_n	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	OUTPUT
alert_tx_o[4].alert_p	Yes	Yes	T12,T2,T4	Yes	T12,T2,T4	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
otp_ast_pwr_seq_o.pwr_seq[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
otp_ast_pwr_seq_h_i.pwr_seq_h[1:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
pwr_otp_i.otp_init	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
pwr_otp_o.otp_idle	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
pwr_otp_o.otp_done	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
lc_otp_vendor_test_i.ctrl[31:0]	No	No		No		INPUT
lc_otp_vendor_test_o.status[31:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
lc_otp_program_i.count[0]	No	No		No		INPUT
lc_otp_program_i.count[1]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[2]	No	No		No		INPUT
lc_otp_program_i.count[3]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[5:4]	No	No		No		INPUT
lc_otp_program_i.count[8:6]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[9]	No	No		No		INPUT
lc_otp_program_i.count[11:10]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[12]	No	No		No		INPUT
lc_otp_program_i.count[13]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[14]	No	No		No		INPUT
lc_otp_program_i.count[15]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[16]	No	No		No		INPUT
lc_otp_program_i.count[19:17]	Yes	Yes	*T54,*T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[21:20]	No	No		No		INPUT
lc_otp_program_i.count[23:22]	Yes	Yes	*T54,*T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[24]	No	No		No		INPUT
lc_otp_program_i.count[25]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[26]	No	No		No		INPUT
lc_otp_program_i.count[27]	Yes	Yes	*T54,*T55,*T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[28]	No	No		No		INPUT
lc_otp_program_i.count[29]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[30]	No	No		No		INPUT
lc_otp_program_i.count[31]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[33:32]	No	No		No		INPUT
lc_otp_program_i.count[35:34]	Yes	Yes	T54,T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[36]	No	No		No		INPUT
lc_otp_program_i.count[38:37]	Yes	Yes	*T54,*T55,T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[39]	No	No		No		INPUT
lc_otp_program_i.count[43:40]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[45:44]	No	No		No		INPUT
lc_otp_program_i.count[46]	Yes	Yes	*T54,*T55,*T42	Yes	T54,T55,T42	INPUT
lc_otp_program_i.count[48:47]	No	No		No		INPUT
lc_otp_program_i.count[53:49]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[55:54]	No	No		No		INPUT
lc_otp_program_i.count[58:56]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[59]	No	No		No		INPUT
lc_otp_program_i.count[60]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[63:61]	No	No		No		INPUT
lc_otp_program_i.count[64]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[65]	No	No		No		INPUT
lc_otp_program_i.count[67:66]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[68]	No	No		No		INPUT
lc_otp_program_i.count[69]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[70]	No	No		No		INPUT
lc_otp_program_i.count[77:71]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[79:78]	No	No		No		INPUT
lc_otp_program_i.count[81:80]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[82]	No	No		No		INPUT
lc_otp_program_i.count[86:83]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[87]	No	No		No		INPUT
lc_otp_program_i.count[90:88]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[91]	No	No		No		INPUT
lc_otp_program_i.count[92]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[93]	No	No		No		INPUT
lc_otp_program_i.count[94]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[95]	No	No		No		INPUT
lc_otp_program_i.count[98:96]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[99]	No	No		No		INPUT
lc_otp_program_i.count[105:100]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[106]	No	No		No		INPUT
lc_otp_program_i.count[111:107]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[112]	No	No		No		INPUT
lc_otp_program_i.count[113]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[116:114]	No	No		No		INPUT
lc_otp_program_i.count[118:117]	Yes	Yes	T54,T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[119]	No	No		No		INPUT
lc_otp_program_i.count[120]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[121]	No	No		No		INPUT
lc_otp_program_i.count[123:122]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[126:124]	No	No		No		INPUT
lc_otp_program_i.count[134:127]	Yes	Yes	*T54,*T55,T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[136:135]	No	No		No		INPUT
lc_otp_program_i.count[137]	Yes	Yes	*T54,*T55,*T42	Yes	T35,T54,T55	INPUT
lc_otp_program_i.count[138]	No	No		No		INPUT
lc_otp_program_i.count[140:139]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[145:141]	No	No		No		INPUT
lc_otp_program_i.count[147:146]	Yes	Yes	T54,T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[148]	No	No		No		INPUT
lc_otp_program_i.count[150:149]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[151]	No	No		No		INPUT
lc_otp_program_i.count[155:152]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[157:156]	No	No		No		INPUT
lc_otp_program_i.count[164:158]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[166:165]	No	No		No		INPUT
lc_otp_program_i.count[167]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[168]	No	No		No		INPUT
lc_otp_program_i.count[174:169]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[176:175]	No	No		No		INPUT
lc_otp_program_i.count[177]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[179:178]	No	No		No		INPUT
lc_otp_program_i.count[184:180]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[186:185]	No	No		No		INPUT
lc_otp_program_i.count[187]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[189:188]	No	No		No		INPUT
lc_otp_program_i.count[190]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[192:191]	No	No		No		INPUT
lc_otp_program_i.count[193]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[195:194]	No	No		No		INPUT
lc_otp_program_i.count[202:196]	Yes	Yes	*T54,*T55,T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[203]	No	No		No		INPUT
lc_otp_program_i.count[204]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[206:205]	No	No		No		INPUT
lc_otp_program_i.count[212:207]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[213]	No	No		No		INPUT
lc_otp_program_i.count[214]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[216:215]	No	No		No		INPUT
lc_otp_program_i.count[217]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[219:218]	No	No		No		INPUT
lc_otp_program_i.count[222:220]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[223]	No	No		No		INPUT
lc_otp_program_i.count[224]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[225]	No	No		No		INPUT
lc_otp_program_i.count[226]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[229:227]	No	No		No		INPUT
lc_otp_program_i.count[232:230]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[234:233]	No	No		No		INPUT
lc_otp_program_i.count[235]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[236]	No	No		No		INPUT
lc_otp_program_i.count[237]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[238]	No	No		No		INPUT
lc_otp_program_i.count[241:239]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[244:242]	No	No		No		INPUT
lc_otp_program_i.count[251:245]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[253:252]	No	No		No		INPUT
lc_otp_program_i.count[258:254]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[259]	No	No		No		INPUT
lc_otp_program_i.count[263:260]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[265:264]	No	No		No		INPUT
lc_otp_program_i.count[268:266]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[269]	No	No		No		INPUT
lc_otp_program_i.count[270]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[272:271]	No	No		No		INPUT
lc_otp_program_i.count[275:273]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[276]	No	No		No		INPUT
lc_otp_program_i.count[285:277]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[286]	No	No		No		INPUT
lc_otp_program_i.count[287]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T22,T34	INPUT
lc_otp_program_i.count[288]	No	No		No		INPUT
lc_otp_program_i.count[290:289]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[291]	No	No		No		INPUT
lc_otp_program_i.count[292]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[293]	No	No		No		INPUT
lc_otp_program_i.count[297:294]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[299:298]	No	No		No		INPUT
lc_otp_program_i.count[300]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[301]	No	No		No		INPUT
lc_otp_program_i.count[303:302]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[304]	No	No		No		INPUT
lc_otp_program_i.count[305]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[306]	No	No		No		INPUT
lc_otp_program_i.count[311:307]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[313:312]	No	No		No		INPUT
lc_otp_program_i.count[317:314]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[318]	No	No		No		INPUT
lc_otp_program_i.count[321:319]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.count[329:322]	No	No		No		INPUT
lc_otp_program_i.count[331:330]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[332]	No	No		No		INPUT
lc_otp_program_i.count[333]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[335:334]	No	No		No		INPUT
lc_otp_program_i.count[336]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[337]	No	No		No		INPUT
lc_otp_program_i.count[340:338]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[341]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[343:342]	No	No		No		INPUT
lc_otp_program_i.count[344]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[345]	No	No		No		INPUT
lc_otp_program_i.count[350:346]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[351]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[353:352]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[354]	No	No		No		INPUT
lc_otp_program_i.count[355]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[357:356]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[358]	No	No		No		INPUT
lc_otp_program_i.count[359]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[362:360]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[363]	No	No		No		INPUT
lc_otp_program_i.count[364]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[365]	No	No		No		INPUT
lc_otp_program_i.count[366]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[368:367]	No	No		No		INPUT
lc_otp_program_i.count[369]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[370]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[371]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[372]	No	No		No		INPUT
lc_otp_program_i.count[374:373]	No	No		Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[375]	No	No		No		INPUT
lc_otp_program_i.count[379:376]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[380]	No	No		No		INPUT
lc_otp_program_i.count[382:381]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.count[383]	No	No		No		INPUT
lc_otp_program_i.state[3:0]	No	No		No		INPUT
lc_otp_program_i.state[6:4]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[7]	No	No		No		INPUT
lc_otp_program_i.state[9:8]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[10]	No	No		No		INPUT
lc_otp_program_i.state[13:11]	Yes	Yes	*T54,*T55,*T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[15:14]	No	No		No		INPUT
lc_otp_program_i.state[21:16]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[22]	No	No		No		INPUT
lc_otp_program_i.state[25:23]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[26]	No	No		No		INPUT
lc_otp_program_i.state[32:27]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[33]	No	No		No		INPUT
lc_otp_program_i.state[34]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[37:35]	No	No		No		INPUT
lc_otp_program_i.state[39:38]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[43:40]	No	No		No		INPUT
lc_otp_program_i.state[46:44]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[50:47]	No	No		No		INPUT
lc_otp_program_i.state[51]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[53:52]	No	No		No		INPUT
lc_otp_program_i.state[55:54]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[58:56]	No	No		No		INPUT
lc_otp_program_i.state[59]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[60]	No	No		No		INPUT
lc_otp_program_i.state[67:61]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[69:68]	No	No		No		INPUT
lc_otp_program_i.state[70]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[71]	No	No		No		INPUT
lc_otp_program_i.state[73:72]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[74]	No	No		No		INPUT
lc_otp_program_i.state[77:75]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[78]	No	No		No		INPUT
lc_otp_program_i.state[80:79]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[81]	No	No		No		INPUT
lc_otp_program_i.state[84:82]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[85]	No	No		No		INPUT
lc_otp_program_i.state[93:86]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[94]	No	No		No		INPUT
lc_otp_program_i.state[96:95]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[97]	No	No		No		INPUT
lc_otp_program_i.state[101:98]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[102]	No	No		No		INPUT
lc_otp_program_i.state[104:103]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[107:105]	No	No		No		INPUT
lc_otp_program_i.state[110:108]	Yes	Yes	*T54,*T55,T42	Yes	T21,T36,T54	INPUT
lc_otp_program_i.state[112:111]	No	No		No		INPUT
lc_otp_program_i.state[113]	Yes	Yes	*T54,*T55,*T42	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[117:114]	No	No		No		INPUT
lc_otp_program_i.state[120:118]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[121]	No	No		No		INPUT
lc_otp_program_i.state[122]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[123]	No	No		No		INPUT
lc_otp_program_i.state[131:124]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[132]	No	No		No		INPUT
lc_otp_program_i.state[136:133]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[137]	No	No		No		INPUT
lc_otp_program_i.state[138]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[139]	No	No		No		INPUT
lc_otp_program_i.state[141:140]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[142]	No	No		No		INPUT
lc_otp_program_i.state[146:143]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[147]	No	No		No		INPUT
lc_otp_program_i.state[149:148]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[150]	No	No		No		INPUT
lc_otp_program_i.state[151]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[154:152]	No	No		No		INPUT
lc_otp_program_i.state[156:155]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[159:157]	No	No		No		INPUT
lc_otp_program_i.state[163:160]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[165:164]	No	No		No		INPUT
lc_otp_program_i.state[170:166]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[172:171]	No	No		No		INPUT
lc_otp_program_i.state[173]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[174]	No	No		No		INPUT
lc_otp_program_i.state[175]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[176]	No	No		No		INPUT
lc_otp_program_i.state[177]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[178]	No	No		No		INPUT
lc_otp_program_i.state[181:179]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[182]	No	No		No		INPUT
lc_otp_program_i.state[183]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[184]	No	No		No		INPUT
lc_otp_program_i.state[186:185]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[188:187]	No	No		No		INPUT
lc_otp_program_i.state[190:189]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[191]	No	No		No		INPUT
lc_otp_program_i.state[197:192]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[198]	No	No		No		INPUT
lc_otp_program_i.state[200:199]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[201]	No	No		No		INPUT
lc_otp_program_i.state[203:202]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[204]	No	No		No		INPUT
lc_otp_program_i.state[206:205]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[207]	No	No		No		INPUT
lc_otp_program_i.state[210:208]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[211]	No	No		No		INPUT
lc_otp_program_i.state[216:212]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[218:217]	No	No		No		INPUT
lc_otp_program_i.state[219]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[222:220]	No	No		No		INPUT
lc_otp_program_i.state[226:223]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[227]	No	No		No		INPUT
lc_otp_program_i.state[230:228]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[231]	No	No		No		INPUT
lc_otp_program_i.state[234:232]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[238:235]	No	No		No		INPUT
lc_otp_program_i.state[241:239]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[243:242]	No	No		No		INPUT
lc_otp_program_i.state[259:244]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[262:260]	No	No		No		INPUT
lc_otp_program_i.state[263]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[265:264]	No	No		No		INPUT
lc_otp_program_i.state[267:266]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[268]	No	No		No		INPUT
lc_otp_program_i.state[270:269]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[276:271]	No	No		No		INPUT
lc_otp_program_i.state[278:277]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[280:279]	No	No		No		INPUT
lc_otp_program_i.state[281]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[282]	No	No		No		INPUT
lc_otp_program_i.state[287:283]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[288]	No	No		No		INPUT
lc_otp_program_i.state[293:289]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[294]	No	No		No		INPUT
lc_otp_program_i.state[295]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[297:296]	No	No		No		INPUT
lc_otp_program_i.state[298]	Yes	Yes	*T42,*T44,*T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[302:299]	No	No		No		INPUT
lc_otp_program_i.state[303]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[304]	No	No		No		INPUT
lc_otp_program_i.state[305]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[306]	No	No		No		INPUT
lc_otp_program_i.state[307]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[308]	No	No		No		INPUT
lc_otp_program_i.state[314:309]	Yes	Yes	T42,T44,T50	Yes	T20,T21,T22	INPUT
lc_otp_program_i.state[315]	No	No		No		INPUT
lc_otp_program_i.state[318:316]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	INPUT
lc_otp_program_i.state[319]	No	No		No		INPUT
lc_otp_program_i.req	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
lc_otp_program_o.ack	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
lc_otp_program_o.err	No	No		No		OUTPUT
lc_creator_seed_sw_rw_en_i[3:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
lc_seed_hw_rd_en_i[3:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	INPUT
lc_dft_en_i[3:0]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	INPUT
lc_escalate_en_i[3:0]	Yes	Yes	T49,T64,T65	Yes	T49,T64,T65	INPUT
lc_check_byp_en_i[3:0]	Yes	Yes	T29,T81,T1	Yes	T29,T81,T1	INPUT
otp_lc_data_o.rma_token[1:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[2]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[4:3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[5]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[9:6]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[13:10]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[15:14]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[18:16]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[19]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[20]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[22:21]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[24:23]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[26:25]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[27]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[28]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[31:29]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[32]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[33]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[41:34]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[42]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[51:43]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token[52]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[54:53]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.rma_token[55]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[66:56]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.rma_token[67]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[85:68]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.rma_token[86]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[91:87]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.rma_token[92]	No	No		No		OUTPUT
otp_lc_data_o.rma_token[127:93]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_lc_data_o.rma_token_valid[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.test_exit_token[82:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.test_exit_token[83]	No	No		No		OUTPUT
otp_lc_data_o.test_exit_token[127:84]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_lc_data_o.test_unlock_token[127:0]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.test_tokens_valid[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.secrets_valid[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[10:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[11]	No	No		No		OUTPUT
otp_lc_data_o.count[15:12]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[16]	No	No		No		OUTPUT
otp_lc_data_o.count[27:17]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[28]	No	No		No		OUTPUT
otp_lc_data_o.count[31:29]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[32]	No	No		No		OUTPUT
otp_lc_data_o.count[41:33]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[42]	No	No		No		OUTPUT
otp_lc_data_o.count[61:43]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[64:62]	No	No		No		OUTPUT
otp_lc_data_o.count[78:65]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[79]	No	No		No		OUTPUT
otp_lc_data_o.count[88:80]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[89]	No	No		No		OUTPUT
otp_lc_data_o.count[100:90]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[102:101]	No	No		No		OUTPUT
otp_lc_data_o.count[104:103]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[105]	No	No		No		OUTPUT
otp_lc_data_o.count[118:106]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[119]	No	No		No		OUTPUT
otp_lc_data_o.count[121:120]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[122]	No	No		No		OUTPUT
otp_lc_data_o.count[134:123]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[135]	No	No		No		OUTPUT
otp_lc_data_o.count[142:136]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[143]	No	No		No		OUTPUT
otp_lc_data_o.count[150:144]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[151]	No	No		No		OUTPUT
otp_lc_data_o.count[158:152]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[159]	No	No		No		OUTPUT
otp_lc_data_o.count[174:160]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[177:175]	No	No		No		OUTPUT
otp_lc_data_o.count[186:178]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[187]	No	No		No		OUTPUT
otp_lc_data_o.count[188]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[189]	No	No		No		OUTPUT
otp_lc_data_o.count[194:190]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[195]	No	No		No		OUTPUT
otp_lc_data_o.count[196]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[197]	No	No		No		OUTPUT
otp_lc_data_o.count[215:198]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[216]	No	No		No		OUTPUT
otp_lc_data_o.count[217]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[218]	No	No		No		OUTPUT
otp_lc_data_o.count[226:219]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[227]	No	No		No		OUTPUT
otp_lc_data_o.count[228]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[229]	No	No		No		OUTPUT
otp_lc_data_o.count[240:230]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[241]	No	No		No		OUTPUT
otp_lc_data_o.count[243:242]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[245:244]	No	No		No		OUTPUT
otp_lc_data_o.count[265:246]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[266]	No	No		No		OUTPUT
otp_lc_data_o.count[274:267]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[275]	No	No		No		OUTPUT
otp_lc_data_o.count[285:276]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[286]	No	No		No		OUTPUT
otp_lc_data_o.count[316:287]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[317]	No	No		No		OUTPUT
otp_lc_data_o.count[335:318]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[337:336]	No	No		No		OUTPUT
otp_lc_data_o.count[338]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[339]	No	No		No		OUTPUT
otp_lc_data_o.count[343:340]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.count[344]	No	No		No		OUTPUT
otp_lc_data_o.count[375:345]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.count[376]	No	No		No		OUTPUT
otp_lc_data_o.count[383:377]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[5:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[6]	No	No		No		OUTPUT
otp_lc_data_o.state[12:7]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[13]	No	No		No		OUTPUT
otp_lc_data_o.state[19:14]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[20]	No	No		No		OUTPUT
otp_lc_data_o.state[21]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[22]	No	No		No		OUTPUT
otp_lc_data_o.state[31:23]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[32]	No	No		No		OUTPUT
otp_lc_data_o.state[36:33]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[37]	No	No		No		OUTPUT
otp_lc_data_o.state[46:38]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[48:47]	No	No		No		OUTPUT
otp_lc_data_o.state[52:49]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[53]	No	No		No		OUTPUT
otp_lc_data_o.state[65:54]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[66]	No	No		No		OUTPUT
otp_lc_data_o.state[68:67]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[69]	No	No		No		OUTPUT
otp_lc_data_o.state[77:70]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[78]	No	No		No		OUTPUT
otp_lc_data_o.state[79]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[80]	No	No		No		OUTPUT
otp_lc_data_o.state[84:81]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[85]	No	No		No		OUTPUT
otp_lc_data_o.state[98:86]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[99]	No	No		No		OUTPUT
otp_lc_data_o.state[103:100]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[104]	No	No		No		OUTPUT
otp_lc_data_o.state[114:105]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[115]	No	No		No		OUTPUT
otp_lc_data_o.state[131:116]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[132]	No	No		No		OUTPUT
otp_lc_data_o.state[134:133]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[135]	No	No		No		OUTPUT
otp_lc_data_o.state[136]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[137]	No	No		No		OUTPUT
otp_lc_data_o.state[146:138]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[147]	No	No		No		OUTPUT
otp_lc_data_o.state[152:148]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[154:153]	No	No		No		OUTPUT
otp_lc_data_o.state[157:155]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[158]	No	No		No		OUTPUT
otp_lc_data_o.state[165:159]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[166]	No	No		No		OUTPUT
otp_lc_data_o.state[177:167]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[178]	No	No		No		OUTPUT
otp_lc_data_o.state[181:179]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[184:182]	No	No		No		OUTPUT
otp_lc_data_o.state[187:185]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[188]	No	No		No		OUTPUT
otp_lc_data_o.state[191:189]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[192]	No	No		No		OUTPUT
otp_lc_data_o.state[199:193]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[200]	No	No		No		OUTPUT
otp_lc_data_o.state[206:201]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[207]	No	No		No		OUTPUT
otp_lc_data_o.state[214:208]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[215]	No	No		No		OUTPUT
otp_lc_data_o.state[219:216]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[220]	No	No		No		OUTPUT
otp_lc_data_o.state[230:221]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[231]	No	No		No		OUTPUT
otp_lc_data_o.state[234:232]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[236:235]	No	No		No		OUTPUT
otp_lc_data_o.state[241:237]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[242]	No	No		No		OUTPUT
otp_lc_data_o.state[243]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[244]	No	No		No		OUTPUT
otp_lc_data_o.state[246:245]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[247]	No	No		No		OUTPUT
otp_lc_data_o.state[277:248]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[278]	No	No		No		OUTPUT
otp_lc_data_o.state[279]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[280]	No	No		No		OUTPUT
otp_lc_data_o.state[301:281]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.state[302]	No	No		No		OUTPUT
otp_lc_data_o.state[306:303]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[307]	No	No		No		OUTPUT
otp_lc_data_o.state[311:308]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_lc_data_o.state[312]	No	No		No		OUTPUT
otp_lc_data_o.state[319:313]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_lc_data_o.error	Yes	Yes	T18,T19,T26	Yes	T18,T19,T26	OUTPUT
otp_lc_data_o.valid	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[2:0]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[7:4]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[8]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[9]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[11:10]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[12]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[16:13]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[18:17]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[20:19]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[21]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[26:22]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[28:27]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[29]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[30]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[32:31]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[34:33]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[36:35]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[41:37]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[42]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[43]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[45:44]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[48:46]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[49]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[50]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[51]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[55:52]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[56]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[59:57]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[60]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[61]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[71:62]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[72]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[76:73]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[77]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[81:78]	Yes	Yes	*T42,*T44,*T50	Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[82]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[87:83]	Yes	Yes	*T42,*T44,*T50	Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[88]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[92:89]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[93]	No	No		Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[94]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[95]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[97:96]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[100:98]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[101]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[103:102]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[105:104]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[108:106]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[109]	No	Yes	*T31,*T33,*T48	No		OUTPUT
otp_keymgr_key_o.key_share1[110]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[111]	No	No		Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[122:112]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[123]	No	No		Yes	T31,T33,T48	OUTPUT
otp_keymgr_key_o.key_share1[124]	No	Yes	*T31,*T33,*T48	No		OUTPUT
otp_keymgr_key_o.key_share1[125]	Yes	Yes	*T31,*T33,*T48	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[126]	No	Yes	*T31,*T33,*T48	No		OUTPUT
otp_keymgr_key_o.key_share1[127]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[128]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[129]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[130]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[131]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[132]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[137:133]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[139:138]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[140]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[141]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[143:142]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[146:144]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[147]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[151:148]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[152]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[153]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[155:154]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[156]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[157]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[158]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[171:159]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[172]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[176:173]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[177]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[182:178]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[183]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[186:184]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[187]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[188]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[189]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[192:190]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[193]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[194]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[196:195]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[199:197]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[200]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[201]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[208:202]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[210:209]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[211]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[213:212]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[214]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[221:215]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[222]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[223]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[224]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[227:225]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[228]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[230:229]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share1[231]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[238:232]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[239]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[243:240]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[245:244]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[247:246]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share1[250:248]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share1[254:251]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share1[255]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[2:0]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[3]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[4]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[5]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[9:6]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[10]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[11]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[12]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[17:13]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[18]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[29:19]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[31:30]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[38:32]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[39]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[48:40]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[50:49]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[53:51]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[54]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[56:55]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[57]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[61:58]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[62]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[64:63]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[65]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[71:66]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[72]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[74:73]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[75]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[78:76]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[79]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[80]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[81]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[88:82]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[89]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[90]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[91]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[94:92]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[95]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[96]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[97]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[104:98]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[106:105]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[113:107]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[119:114]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[130:120]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[131]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[134:132]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[135]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[138:136]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[139]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[145:140]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[146]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[148:147]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[149]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[156:150]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[157]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[159:158]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[160]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[170:161]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[171]	No	No		Yes	T20,T22,T34	OUTPUT
otp_keymgr_key_o.key_share0[178:172]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[179]	No	Yes	*T20,*T22,*T34	No		OUTPUT
otp_keymgr_key_o.key_share0[180]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[181]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[190:182]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_keymgr_key_o.key_share0[191]	No	No		Yes	T20,T22,T34	OUTPUT
otp_keymgr_key_o.key_share0[194:192]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[199:195]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[201:200]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[205:202]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[206]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[207]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[208]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[210:209]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[212:211]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[214:213]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[216:215]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[217]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[219:218]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[222:220]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[223]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[225:224]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[227:226]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[228]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[229]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[232:230]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[233]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[235:234]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[240:236]	Yes	Yes	T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[245:241]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[248:246]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_keymgr_key_o.key_share0[249]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[250]	Yes	Yes	*T2,*T4,*T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[251]	No	No		No		OUTPUT
otp_keymgr_key_o.key_share0[254:252]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_keymgr_key_o.key_share0[255]	No	No		No		OUTPUT
otp_keymgr_key_o.valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_i.addr_req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
flash_otp_key_i.data_req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
flash_otp_key_o.seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.rand_key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.addr_ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
flash_otp_key_o.data_ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_i[0].req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
sram_otp_key_i[1].req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
sram_otp_key_i[2].req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
sram_otp_key_o[0].seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[0].nonce[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[0].key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[0].ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].nonce[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[1].ack	Yes	Yes	T20,T22,T31	Yes	T20,T22,T31	OUTPUT
sram_otp_key_o[2].seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[2].nonce[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[2].key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
sram_otp_key_o[2].ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_i.req	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
otbn_otp_key_o.seed_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_o.nonce[63:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_o.key[127:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otbn_otp_key_o.ack	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
otp_hw_cfg_o.data.device_id[41:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[42]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[43]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[44]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[47:45]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[49:48]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[52:50]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[53]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[56:54]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[57]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[58]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[59]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[64:60]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[65]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[73:66]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[74]	No	No		Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.device_id[85:75]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[86]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[87]	No	No		Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.device_id[91:88]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[92]	No	No		Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.device_id[96:93]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[97]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[103:98]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[104]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[108:105]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[111:109]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[114:112]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[115]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[122:116]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
otp_hw_cfg_o.data.device_id[123]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[162:124]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[163]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[164]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[165]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[169:166]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[170]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[177:171]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[180:178]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[188:181]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[190:189]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[195:191]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[196]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[204:197]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
otp_hw_cfg_o.data.device_id[205]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[224:206]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.device_id[227:225]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[228]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[229]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[234:230]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[237:235]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[241:238]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[242]	No	No		No		OUTPUT
otp_hw_cfg_o.data.device_id[245:243]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.device_id[255:246]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[1:0]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[3:2]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[7:5]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[8]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[15:9]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[16]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[18:17]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[19]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[21:20]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[22]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[38:23]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[39]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[64:40]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[65]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[74:66]	Yes	Yes	*T35,*T38,*T42	Yes	T35,T38,T42	OUTPUT
otp_hw_cfg_o.data.manuf_state[76:75]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[95:77]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[96]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[100:97]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[101]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[106:102]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[108:107]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[130:109]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[131]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[133:132]	Yes	Yes	*T42,*T44,*T89	Yes	T53,T92,T42	OUTPUT
otp_hw_cfg_o.data.manuf_state[134]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[145:135]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[146]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[154:147]	Yes	Yes	*T42,*T44,*T50	Yes	T53,T92,T42	OUTPUT
otp_hw_cfg_o.data.manuf_state[155]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[156]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
otp_hw_cfg_o.data.manuf_state[157]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[162:158]	Yes	Yes	*T42,*T44,*T89	Yes	T42,T44,T89	OUTPUT
otp_hw_cfg_o.data.manuf_state[163]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[176:164]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[177]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[184:178]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	OUTPUT
otp_hw_cfg_o.data.manuf_state[185]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[187:186]	Yes	Yes	*T31,*T33,*T48	Yes	T31,T33,T48	OUTPUT
otp_hw_cfg_o.data.manuf_state[189:188]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[196:190]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[197]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[198]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[199]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[201:200]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[202]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[212:203]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[213]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[216:214]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[217]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[221:218]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.manuf_state[222]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[231:223]	Yes	Yes	*T54,*T55,*T56	Yes	T54,T55,T56	OUTPUT
otp_hw_cfg_o.data.manuf_state[233:232]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[242:234]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[243]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[249:244]	Yes	Yes	*T42,*T44,*T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.manuf_state[250]	No	No		No		OUTPUT
otp_hw_cfg_o.data.manuf_state[255:251]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[3:0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[6:5]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_sram_ifetch[7]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[1]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_csrng_sw_app_read[7:2]	Yes	Yes	T42,T44,T50	Yes	T42,T44,T50	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[2:1]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[6:3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_read[7]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[0]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[2:1]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[3]	Yes	Yes	*T29,*T81,*T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[6:5]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.data.en_entropy_src_fw_over[7]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[2:0]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[3]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[4]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[5]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[8:6]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[11:9]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[13:12]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[16:14]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[17]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[18]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[22:19]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[23]	Yes	Yes	*T89,*T93,*T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[24]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[27:25]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.unallocated[28]	No	No		No		OUTPUT
otp_hw_cfg_o.data.unallocated[31:29]	Yes	Yes	T89,T93,T94	Yes	T89,T93,T94	OUTPUT
otp_hw_cfg_o.data.hw_cfg_digest[63:0]	Yes	Yes	T29,T81,T1	Yes	T2,T4,T5	OUTPUT
otp_hw_cfg_o.valid[3:0]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT
otp_ext_voltage_h_io	No	No		No		INOUT
scan_en_i	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
scan_rst_ni	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
scanmode_i[3:0]	Yes	Yes	T2,T4,T8	Yes	T2,T4,T5	INPUT
cio_test_o[7:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
cio_test_en_o[7:0]	Yes	Yes	T2,T4,T5	Yes	T29,T81,T1	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		33	32	96.97
TERNARY	1300	2	2	100.00
TERNARY	1352	2	2	100.00
TERNARY	1354	2	2	100.00
TERNARY	1356	2	2	100.00
IF	268	3	2	66.67
IF	289	2	2	100.00
IF	329	2	2	100.00
IF	332	2	2	100.00
IF	335	2	2	100.00
IF	339	2	2	100.00
IF	399	2	2	100.00
IF	438	2	2	100.00
IF	459	2	2	100.00
IF	462	2	2	100.00
IF	499	2	2	100.00
IF	956	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1300	(part_init_done[HwCfgIdx]) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1352	((part_digest[Secret0Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1354	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	1356	((part_digest[Secret2Idx] != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	268	if (tlul_req)
-2-:	269	if ((tlul_part_sel_oh != '0))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T20
1	0	Not Covered
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	289	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	329	if ((!reg2hw.vendor_test_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	332	if ((!reg2hw.creator_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	if ((!reg2hw.owner_sw_cfg_read_lock))

Branches:

-1-	Status	Tests
1	Covered	T19,T21,T49
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	339	if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_creator_seed_sw_rw_en))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	399	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	438	if (otp_ctrl_part_pkg::PartInfo[k].ecc_fatal)

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	459	if ((fatal_macro_error_q || fatal_check_error_q))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T26
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	462	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_escalate_en[k]))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T26
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	499	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	956	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	64	64	100.00	64	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	64	64	100.00	64	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnown_A	1570944001	1569874661	0	0
CoreTlOutKnown_A	1570944001	1569874661	0	0
CreatorRootKeyShare0Size_A	1168	1168	0	0
CreatorRootKeyShare1Size_A	1168	1168	0	0
ErrorCodeWidth_A	1168	1168	0	0
FlashAddrKeySeedSize_A	1168	1168	0	0
FlashDataKeySeedSize_A	1168	1168	0	0
FlashOtpKeyRspKnown_A	1570944001	1569874661	0	0
FpvSecCmCntCnstyCheck_A	1570944001	50	0	0
FpvSecCmCntDaiCheck_A	1570944001	50	0	0
FpvSecCmCntIntegCheck_A	1570944001	50	0	0
FpvSecCmCntKdiEntropyCheck_A	1570944001	50	0	0
FpvSecCmCntKdiSeedCheck_A	1570944001	50	0	0
FpvSecCmCntLciCheck_A	1570944001	50	0	0
FpvSecCmCntScrmblCheck_A	1570944001	50	0	0
FpvSecCmCtrlDaiFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlKdiFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlLciFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlLfsrTimerFsmCheck_A	1570944001	50	0	0
FpvSecCmCtrlScrambleFsmCheck_A	1570944001	50	0	0
FpvSecCmDoubleLfsrCheck_A	1570944001	50	0	0
FpvSecCmRegWeOnehotCheck_A	1570944001	50	0	0
FpvSecCmTlLcGateFsm_A	1570944001	50	0	0
IntrOtpErrorKnown_A	1570944001	1569874661	0	0
IntrOtpOperationDoneKnown_A	1570944001	1569874661	0	0
LcOtpProgramRspKnown_A	1570944001	1569874661	0	0
LcSeedHwRdEnStable_A	1570944001	2650	0	0
LcStateSize_A	1168	1168	0	0
LcTransitionCntSize_A	1168	1168	0	0
OtpAstPwrSeqKnown_A	1570944001	1569874661	0	0
OtpErrorCode0_A	1168	1168	0	0
OtpErrorCode1_A	1168	1168	0	0
OtpErrorCode2_A	1168	1168	0	0
OtpErrorCode3_A	1168	1168	0	0
OtpErrorCode4_A	1168	1168	0	0
OtpHwCfgKnown_A	1570944001	1569874661	0	0
OtpIfWidth_A	1168	1168	0	0
OtpKeymgrKeyKnown_A	1570944001	1569874661	0	0
OtpLcDataKnown_A	1570944001	1569874661	0	0
OtpOtgnKeyKnown_A	1570944001	1569874661	0	0
OtpRespFifoUnderflow_A	1570944001	1326224	0	0
OtpSramKeyKnown_A	1570944001	1569874661	0	0
PartSelMustBeOnehot_A	1570944001	1569874661	0	0
PrimTlOutKnown_A	1570944001	1569874661	0	0
PwrOtpInitRspKnown_A	1570944001	1569874661	0	0
RmaTokenSize_A	1168	1168	0	0
SramDataKeySeedSize_A	1168	1168	0	0
TestExitTokenSize_A	1168	1168	0	0
TestUnlockTokenSize_A	1168	1168	0	0
gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1570944001	50	0	0
gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1570944001	50	0	0
gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A	1570944001	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A	1570944001	50	0	0
gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A	1570944001	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A	1570944001	50	0	0
gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A	1570944001	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A	1570944001	50	0	0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A	1570944001	50	0	0

AlertTxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

CoreTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

CreatorRootKeyShare0Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

CreatorRootKeyShare1Size_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

ErrorCodeWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

FlashAddrKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

FlashDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

FlashOtpKeyRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

FpvSecCmCntCnstyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntDaiCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntIntegCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntKdiEntropyCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntKdiSeedCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntLciCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCntScrmblCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlDaiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlKdiFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlLciFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlLfsrTimerFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmCtrlScrambleFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmDoubleLfsrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

FpvSecCmTlLcGateFsm_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

IntrOtpErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

IntrOtpOperationDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

LcOtpProgramRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

LcSeedHwRdEnStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	2650	0	0
T20	54961	5	0	0
T21	34632	3	0	0
T22	54961	5	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	1	0	0
T32	15666	0	0	0
T33	13744	1	0	0
T34	0	5	0	0
T36	0	3	0	0
T47	15666	0	0	0
T48	13744	1	0	0
T52	0	1	0	0
T53	0	1	0	0

LcStateSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

LcTransitionCntSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpAstPwrSeqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpErrorCode0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpErrorCode4_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpHwCfgKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpIfWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpKeymgrKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpLcDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpOtgnKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpRespFifoUnderflow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1326224	0	0
T18	853907	15652	0	0
T19	38999	238	0	0
T20	54961	807	0	0
T21	34632	720	0	0
T22	54961	807	0	0
T26	15666	197	0	0
T30	7104	52	0	0
T31	13744	303	0	0
T32	15666	197	0	0
T33	13744	303	0	0

OtpSramKeyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

PartSelMustBeOnehot_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

PrimTlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

PwrOtpInitRspKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

RmaTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

SramDataKeySeedSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

TestExitTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

TestUnlockTokenSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

gen_partitions[0].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[1].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[2].gen_unbuffered.FpvSecCmCtrlPartUnbufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[3].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[3].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[4].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[4].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[5].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCntPartBufCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[6].gen_buffered.FpvSecCmCtrlPartBufFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCntPartLcCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_partitions[7].gen_lifecycle.FpvSecCmCtrlPartLcFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	50	0	0
T18	853907	10	0	0
T19	38999	0	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T26	15666	0	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T95	0	10	0	0
T96	0	10	0	0