Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
7.69						7.69

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	7.69						7.69

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
7.69						7.69

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
7.69						7.69

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	95.77	87.62	85.09		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	1	7.69
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	1	7.69

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1573118121	6950380	0	0
check_regwen_rd_A	1573118121	0	0	0
check_timeout_rd_A	1573118121	0	0	0
check_trigger_regwen_rd_A	1573118121	0	0	0
consistency_check_period_rd_A	1573118121	0	0	0
creator_sw_cfg_read_lock_rd_A	1573118121	0	0	0
direct_access_address_rd_A	1573118121	0	0	0
direct_access_wdata_0_rd_A	1573118121	0	0	0
direct_access_wdata_1_rd_A	1573118121	0	0	0
integrity_check_period_rd_A	1573118121	0	0	0
intr_enable_rd_A	1573118121	0	0	0
owner_sw_cfg_read_lock_rd_A	1573118121	0	0	0
vendor_test_read_lock_rd_A	1573118121	0	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	6950380	0	0
T1	7141	180	0	0
T2	64750	2	0	0
T3	7141	180	0	0
T4	0	2	0	0
T5	0	17	0	0
T6	0	17	0	0
T7	0	180	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	17	0	0
T11	3821	0	0	0
T12	22545	0	0	0
T13	3821	0	0	0
T14	3821	0	0	0
T15	3821	0	0	0
T16	7146	0	0	0
T17	3821	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1573118121	0	0	0