Unified Coverage Report :: Module :: otp_ctrl_lfsr_timer

Module : otp_ctrl_lfsr_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.71	100.00	88.46		88.89	91.18	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer	93.71	100.00	88.46		88.89	91.18	100.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.71	100.00	88.46		88.89	91.18	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.04	100.00	88.75	76.92	88.89	91.67	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	95.77	87.62	85.09		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count_cnsty	93.60			93.60
u_prim_count_integ	93.60			93.60
u_prim_double_lfsr	87.95	100.00	100.00	51.81			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	52	52	100.00
ALWAYS	365	3	3	100.00
ALWAYS	368	13	13	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
72	1	1
77	1	1
78	1	1
87	1	1
114	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
139	1	1
141	1	1
142	1	1
143	1	1
144	1	1
187	1	1
188	1	1
189	1	1
191	1	1
199	1	1
200	1	1
241	1	1
244	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
255	1	1
256	1	1
259	1	1
260	1	1
261	1	1
264	1	1
265	1	1
267	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
			MISSING_ELSE
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
305	1	1
306	1	1
			MISSING_ELSE
314	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	1	1
328	1	1
			MISSING_ELSE
335	1	1
336	1	1
337	1	1
338	1	1
			MISSING_ELSE
354	1	1
356	1	1
357	1	1
			MISSING_ELSE
365	3	3
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1

---

Cond Coverage for Module : otp_ctrl_lfsr_timer

	Total	Covered	Percent
Conditions	78	69	88.46
Logical	78	69	88.46
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T19,T20
1	0	Not Covered

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       166
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T35,T38,T42
1	1	Covered	T18,T20,T21

 LINE       189
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       191
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       199
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Not Covered

 LINE       199
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T20,T21,T22
1	1	Not Covered

 LINE       200
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22

 LINE       200
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       260
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T21,T49,T35
1	0	Covered	T20,T21,T22

 LINE       281
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T23,T24,T25

 LINE       281
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       286
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T23,T24,T25

 LINE       286
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       299
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T54,T55,T42
1	0	Covered	T20,T21,T22
1	1	Covered	T23,T24,T25

 LINE       302
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

 LINE       321
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T21,T35,T36
1	0	Covered	T20,T21,T22
1	1	Covered	T23,T24,T25

 LINE       324
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T20,T21,T22
1	Covered	T20,T21,T22

---

FSM Coverage for Module : otp_ctrl_lfsr_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	8	88.89
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyWaitSt	287	Covered	T29
ErrorSt	300	Covered	T29
IdleSt	273	Covered	T29
IntegWaitSt	282	Covered	T29
ResetSt	271	Covered	T29

transitions	Line No.	Covered	Tests
CnstyWaitSt->ErrorSt	322	Covered	T29
CnstyWaitSt->IdleSt	325	Covered	T29
IdleSt->CnstyWaitSt	287	Covered	T29
IdleSt->ErrorSt	356	Covered	T29
IdleSt->IntegWaitSt	282	Covered	T29
IntegWaitSt->ErrorSt	300	Covered	T29
IntegWaitSt->IdleSt	303	Covered	T29
ResetSt->ErrorSt	356	Not Covered
ResetSt->IdleSt	273	Covered	T29

---

Branch Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
Branches		34	31	91.18
TERNARY	72	4	2	50.00
TERNARY	87	2	1	50.00
TERNARY	143	2	2	100.00
TERNARY	144	2	2	100.00
TERNARY	189	2	2	100.00
TERNARY	191	2	2	100.00
CASE	267	14	14	100.00
IF	354	2	2	100.00
IF	365	2	2	100.00
IF	368	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	(reseed_en) ? 
-2-:	72	(edn_req_o) ? 
-3-:	72	(lfsr_en) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T18,T19,T20
0	0	0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	87	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	143	(integ_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	144	(cnsty_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	189	(set_all_integ_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	191	(set_all_cnsty_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	267	case (state_q)
-2-:	272	if (timer_en_i)
-3-:	281	if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q))
-4-:	286	if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q))
-5-:	299	if (((!timeout_zero) && integ_cnt_zero))
-6-:	302	if ((integ_chk_req_q == '0))
-7-:	321	if (((!timeout_zero) && cnsty_cnt_zero))
-8-:	324	if ((cnsty_chk_req_q == '0))
-9-:	337	if ((!chk_timeout_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	1	-	-	-	-	-	-	Covered	T20,T21,T22
IdleSt	-	0	1	-	-	-	-	-	Covered	T20,T21,T22
IdleSt	-	0	0	-	-	-	-	-	Covered	T18,T19,T20
IntegWaitSt	-	-	-	1	-	-	-	-	Covered	T23,T24,T25
IntegWaitSt	-	-	-	0	1	-	-	-	Covered	T20,T21,T22
IntegWaitSt	-	-	-	0	0	-	-	-	Covered	T20,T21,T22
CnstyWaitSt	-	-	-	-	-	1	-	-	Covered	T23,T24,T25
CnstyWaitSt	-	-	-	-	-	0	1	-	Covered	T20,T21,T22
CnstyWaitSt	-	-	-	-	-	0	0	-	Covered	T20,T21,T22
ErrorSt	-	-	-	-	-	-	-	1	Covered	T18,T49,T64
ErrorSt	-	-	-	-	-	-	-	0	Covered	T23,T24,T25
default	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	354	if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:

-1-	Status	Tests
1	Covered	T18,T49,T64
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	365	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	368	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

---

Assert Coverage for Module : otp_ctrl_lfsr_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChkPendingKnown_A	1570944001	1569874661	0	0
ChkTimeoutKnown_A	1570944001	1569874661	0	0
CnstyChkReqKnown_A	1570944001	1569874661	0	0
EdnIsWideEnough_A	1168	1168	0	0
EdnReqKnown_A	1570944001	1569874661	0	0
IntegChkReqKnown_A	1570944001	1569874661	0	0
u_state_regs_A	1570944001	1569874661	0	0

ChkPendingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

ChkTimeoutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

CnstyChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

EdnIsWideEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

EdnReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

IntegChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0