Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.04	90.91	86.19		57.58	89.39	96.15

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	84.60	89.66	85.71		66.67	88.64	92.31
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	84.60	89.66	85.71		66.67	88.64	92.31
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	89.86	96.43	86.67		79.17	90.91	96.15

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.60	89.66	85.71		66.67	88.64	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.02	93.13	86.49	96.45	66.67	91.07	94.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	95.77	87.62	85.09		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.29	100.00	100.00	96.45		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.60	89.66	85.71		66.67	88.64	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.02	93.13	86.49	96.45	66.67	91.07	94.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	95.77	87.62	85.09		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.29	100.00	100.00	96.45		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.86	96.43	86.67		79.17	90.91	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.10	97.66	87.23	86.52	79.17	92.86	97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.09	95.77	87.62	85.09		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	97.30	100.00	100.00	86.52		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
89.86	96.43

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	82	93.18
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	61	91.04
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	0	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
84.60	89.66

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	79	89.77
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	58	86.57
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	0	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
84.60	89.66

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	79	89.77
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	58	86.57
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	0	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
89.86	86.67

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	39	86.67
Logical	45	39	86.67
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T18,T19,T20
1	0	Not Covered

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T18,T19,T20
-	1	Not Covered

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T20,T26,T22
1	0	Covered	T54,T55,T56

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T20,T26,T22
-	1	Covered	T54,T55,T56

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T54,T55,T56

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T54,T55,T56

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T27,T28

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T26,T32,T47
1	Covered	T26,T32,T47

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T19,T49

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T26,T22

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T49
1	1	Covered	T20,T26,T22

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T18,T19,T20

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T18,T19,T20

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T42,T44,T50

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T42,T44,T50

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 + Info=226594821,DigestOffset=1656,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
84.60	85.71

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	COND
84.60	85.71

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	30	85.71
Logical	35	30	85.71
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T18,T19,T20
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T20,T21,T26
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T20,T21,T26
1	Covered	T54,T55,T56

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T27,T28

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T19,T26

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T26

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T49
1	1	Covered	T20,T21,T26

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T26
1	Covered	T18,T19,T20

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T20,T21,T26
1	Covered	T18,T19,T20

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	9	69.23
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T29
IdleSt	199	Covered	T29
InitSt	175	Covered	T29
InitWaitSt	185	Covered	T29
ReadSt	221	Covered	T29
ReadWaitSt	239	Covered	T29
ResetSt	173	Covered	T29

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T29
IdleSt->ReadSt	221	Covered	T29
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Covered	T29
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Covered	T29
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T29
ReadSt->ReadWaitSt	239	Covered	T29
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T29
ResetSt->ErrorSt	309	Covered	T29
ResetSt->InitSt	175	Covered	T29

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T29
CheckFailError	311	Covered	T29
FsmStateError	283	Covered	T29
MacroEccCorrError	206	Covered	T29
NoError	220	Covered	T29

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	311	Not Covered
AccessError->FsmStateError	319	Covered	T29
AccessError->MacroEccCorrError	206	Not Covered
AccessError->NoError	220	Covered	T29
CheckFailError->AccessError	243	Not Covered
CheckFailError->FsmStateError	319	Not Covered
CheckFailError->MacroEccCorrError	206	Not Covered
CheckFailError->NoError	220	Covered	T29
FsmStateError->AccessError	243	Not Covered
FsmStateError->CheckFailError	311	Not Covered
FsmStateError->MacroEccCorrError	206	Not Covered
FsmStateError->NoError	220	Covered	T29
MacroEccCorrError->AccessError	243	Not Covered
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T29
MacroEccCorrError->NoError	220	Covered	T29
NoError->AccessError	243	Covered	T29
NoError->CheckFailError	311	Covered	T29
NoError->FsmStateError	283	Covered	T29
NoError->MacroEccCorrError	206	Covered	T29

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
84.60	88.64

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	39	88.64
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	1	33.33
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T26,T32
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T21,T26,T32

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T21,T26,T32

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T21,T26
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T21,T26,T32
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T42,T44,T50
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T35,T23
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T54,T55,T56
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T21,T26,T32
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T21,T26,T32
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T18,T19,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T18,T19,T26
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T26
1	0	Covered	T18,T19,T26
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T19,T21
0	0	Covered	T18,T19,T20

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
84.60	88.64

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	39	88.64
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	1	33.33
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T26
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T21,T26

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T21,T26

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T20,T21,T26
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T38,T42
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T23,T24
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T54,T55,T56
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T20,T21,T26
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T20,T21,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T18,T19,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T18,T19,T26
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T26
1	0	Covered	T18,T19,T26
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T19,T20

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
89.86	90.91

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	40	90.91
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	19	82.61
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T26,T22

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T26,T22

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T44,T50
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T20,T26
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T20,T26,T22
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T42,T44,T50
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T23,T24
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T54,T55,T56
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T20,T26,T22
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T20,T26,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T18,T19,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T18,T19,T26
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T26,T32,T47
1	0	Covered	T26,T32,T47
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T49
1	0	Covered	T18,T19,T26
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T19,T20

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	3504	3504	0	0
EccErrorState_A	2147483647	1158600	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	1151862264	0	0
InitWriteLocksPartition_A	2147483647	1151862264	0	0
OffsetMustBeBlockAligned_A	3504	3504	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	0	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	118655730	0	0
SizeMustBeBlockAligned_A	3504	3504	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	31880	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	3062800	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	58459350	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3504	3504	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0
T21	3	3	0	0
T22	3	3	0	0
T26	3	3	0	0
T30	3	3	0	0
T31	3	3	0	0
T32	3	3	0	0
T33	3	3	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1158600	0	0
T22	54961	0	0	0
T26	15666	3862	0	0
T31	13744	0	0	0
T32	15666	3862	0	0
T33	13744	0	0	0
T34	54961	0	0	0
T35	48639	0	0	0
T47	15666	3862	0	0
T48	13744	0	0	0
T49	17690	0	0	0
T57	0	3862	0	0
T58	0	3862	0	0
T59	0	3862	0	0
T60	0	3862	0	0
T61	0	3862	0	0
T62	0	3862	0	0
T63	0	3862	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1151862264	0	0
T18	2561721	347871	0	0
T19	116997	85890	0	0
T20	164883	3360	0	0
T21	103896	3213	0	0
T22	164883	3360	0	0
T26	46998	15903	0	0
T30	21312	372	0	0
T31	41232	1347	0	0
T32	46998	15903	0	0
T33	41232	1347	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1151862264	0	0
T18	2561721	347871	0	0
T19	116997	85890	0	0
T20	164883	3360	0	0
T21	103896	3213	0	0
T22	164883	3360	0	0
T26	46998	15903	0	0
T30	21312	372	0	0
T31	41232	1347	0	0
T32	46998	15903	0	0
T33	41232	1347	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3504	3504	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0
T21	3	3	0	0
T22	3	3	0	0
T26	3	3	0	0
T30	3	3	0	0
T31	3	3	0	0
T32	3	3	0	0
T33	3	3	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118655730	0	0
T19	116997	94995	0	0
T20	164883	2548	0	0
T21	103896	7788	0	0
T22	164883	2548	0	0
T23	0	380968	0	0
T26	46998	0	0	0
T30	21312	0	0	0
T31	41232	0	0	0
T32	46998	0	0	0
T33	41232	0	0	0
T34	0	2548	0	0
T35	0	2974	0	0
T36	0	7788	0	0
T47	46998	0	0	0
T49	0	3268	0	0
T54	0	12575	0	0
T64	0	3268	0	0
T65	0	1112	0	0
T66	0	1112	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3504	3504	0	0
T18	3	3	0	0
T19	3	3	0	0
T20	3	3	0	0
T21	3	3	0	0
T22	3	3	0	0
T26	3	3	0	0
T30	3	3	0	0
T31	3	3	0	0
T32	3	3	0	0
T33	3	3	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31880	0	0
T18	2561721	118	0	0
T19	116997	89	0	0
T20	164883	0	0	0
T21	103896	0	0	0
T22	164883	0	0	0
T23	0	175	0	0
T26	46998	0	0	0
T30	21312	0	0	0
T31	41232	0	0	0
T32	46998	0	0	0
T33	41232	0	0	0
T35	0	1	0	0
T49	0	6	0	0
T54	0	36	0	0
T55	0	21	0	0
T64	0	6	0	0
T65	0	6	0	0
T66	0	6	0	0
T67	0	6	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3062800	0	0
T20	109922	13671	0	0
T21	69264	2412	0	0
T22	109922	13671	0	0
T26	31332	0	0	0
T30	14208	0	0	0
T31	27488	0	0	0
T32	31332	0	0	0
T33	27488	0	0	0
T34	0	13671	0	0
T35	0	4247	0	0
T36	0	2412	0	0
T37	0	13671	0	0
T38	0	4247	0	0
T39	0	13671	0	0
T40	0	1241	0	0
T41	0	13671	0	0
T42	710720	28041	0	0
T43	61495	0	0	0
T44	710720	1772	0	0
T47	31332	0	0	0
T48	27488	0	0	0
T50	710720	1772	0	0
T51	0	1772	0	0
T68	0	1772	0	0
T69	0	1772	0	0
T70	0	1772	0	0
T71	0	1772	0	0
T72	0	1772	0	0
T73	0	1772	0	0
T74	15666	0	0	0
T75	15666	0	0	0
T76	150268	0	0	0
T77	38999	0	0	0
T78	17690	0	0	0
T79	150268	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	58459350	0	0
T20	109922	94419	0	0
T21	69264	40932	0	0
T22	109922	94419	0	0
T26	31332	0	0	0
T30	14208	0	0	0
T31	27488	0	0	0
T32	31332	0	0	0
T33	27488	0	0	0
T34	0	94419	0	0
T35	0	54489	0	0
T36	0	40932	0	0
T42	710720	52247	0	0
T43	61495	0	0	0
T44	710720	52247	0	0
T47	31332	0	0	0
T48	27488	0	0	0
T49	0	5695	0	0
T50	710720	52247	0	0
T51	0	52247	0	0
T54	0	24397	0	0
T64	0	5695	0	0
T65	0	5695	0	0
T68	0	52247	0	0
T69	0	52247	0	0
T70	0	52247	0	0
T71	0	52247	0	0
T72	0	52247	0	0
T73	0	52247	0	0
T74	15666	0	0	0
T75	15666	0	0	0
T76	150268	0	0	0
T77	38999	0	0	0
T78	17690	0	0	0
T79	150268	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T18	2561721	2500671	0	0
T19	116997	116340	0	0
T20	164883	162762	0	0
T21	103896	101559	0	0
T22	164883	162762	0	0
T26	46998	46323	0	0
T30	21312	21132	0	0
T31	41232	40476	0	0
T32	46998	46323	0	0
T33	41232	40476	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	78	89.66
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	57	86.36
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	0	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	30	85.71
Logical	35	30	85.71
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T18,T19,T20
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T21,T26,T32
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T21,T26,T32
1	Covered	T54,T55,T56

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T27,T28

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T19,T26

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T21,T26,T32

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T49
1	1	Covered	T21,T26,T32

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T21,T26,T32
1	Covered	T18,T19,T20

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T21,T26,T32
1	Covered	T18,T19,T20

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	9	69.23
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T29
IdleSt	199	Covered	T29
InitSt	175	Covered	T29
InitWaitSt	185	Covered	T29
ReadSt	221	Covered	T29
ReadWaitSt	239	Covered	T29
ResetSt	173	Covered	T29

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T29
IdleSt->ReadSt	221	Covered	T29
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Covered	T29
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Covered	T29
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T29
ReadSt->ReadWaitSt	239	Covered	T29
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T29
ResetSt->ErrorSt	309	Covered	T29
ResetSt->InitSt	175	Covered	T29

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	7	63.64
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T29
CheckFailError	311	Not Covered
FsmStateError	283	Covered	T29
MacroEccCorrError	206	Covered	T29
NoError	220	Covered	T29

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T29
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T29
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Not Covered
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T29
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T29
MacroEccCorrError->NoError	220	Not Covered
NoError->AccessError	243	Covered	T29
NoError->CheckFailError	311	Not Covered
NoError->FsmStateError	283	Covered	T29
NoError->MacroEccCorrError	206	Covered	T29

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	39	88.64
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	1	33.33
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T26,T32
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T21,T26,T32

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T21,T26,T32

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T21,T26
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T21,T26,T32
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T42,T44,T50
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T35,T23
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T54,T55,T56
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T21,T26,T32
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T21,T26,T32
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T18,T19,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T18,T19,T26
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T26
1	0	Covered	T18,T19,T26
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T19,T21
0	0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	24	92.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	24	92.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1570944001	1569874661	0	0
DigestKnown_A	1570944001	1569874661	0	0
DigestOffsetMustBeRepresentable_A	1168	1168	0	0
EccErrorState_A	1570944001	0	0	0
ErrorKnown_A	1570944001	1569874661	0	0
FsmStateKnown_A	1570944001	1569874661	0	0
InitDoneKnown_A	1570944001	1569874661	0	0
InitReadLocksPartition_A	1570944001	383954888	0	0
InitWriteLocksPartition_A	1570944001	383954888	0	0
OffsetMustBeBlockAligned_A	1168	1168	0	0
OtpAddrKnown_A	1570944001	1569874661	0	0
OtpCmdKnown_A	1570944001	1569874661	0	0
OtpErrorState_A	1570944001	0	0	0
OtpReqKnown_A	1570944001	1569874661	0	0
OtpSizeKnown_A	1570944001	1569874661	0	0
OtpWdataKnown_A	1570944001	1569874661	0	0
ReadLockPropagation_A	1570944001	30106690	0	0
SizeMustBeBlockAligned_A	1168	1168	0	0
TlulGntKnown_A	1570944001	1569874661	0	0
TlulRdataKnown_A	1570944001	1569874661	0	0
TlulReadOnReadLock_A	1570944001	10340	0	0
TlulRerrorKnown_A	1570944001	1569874661	0	0
TlulRvalidKnown_A	1570944001	1569874661	0	0
WriteLockPropagation_A	1570944001	2098250	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1570944001	28963470	0	0
u_state_regs_A	1570944001	1569874661	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	383954888	0	0
T18	853907	115957	0	0
T19	38999	28630	0	0
T20	54961	1122	0	0
T21	34632	1073	0	0
T22	54961	1122	0	0
T26	15666	5301	0	0
T30	7104	124	0	0
T31	13744	449	0	0
T32	15666	5301	0	0
T33	13744	449	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	383954888	0	0
T18	853907	115957	0	0
T19	38999	28630	0	0
T20	54961	1122	0	0
T21	34632	1073	0	0
T22	54961	1122	0	0
T26	15666	5301	0	0
T30	7104	124	0	0
T31	13744	449	0	0
T32	15666	5301	0	0
T33	13744	449	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	30106690	0	0
T19	38999	31554	0	0
T20	54961	1266	0	0
T21	34632	3584	0	0
T22	54961	1266	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T34	0	1266	0	0
T35	0	1435	0	0
T36	0	3584	0	0
T47	15666	0	0	0
T49	0	1123	0	0
T54	0	3699	0	0
T64	0	1123	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	10340	0	0
T18	853907	60	0	0
T19	38999	29	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T23	0	53	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T35	0	1	0	0
T49	0	2	0	0
T54	0	15	0	0
T64	0	2	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	2098250	0	0
T20	54961	12435	0	0
T21	34632	0	0	0
T22	54961	12435	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T34	0	12435	0	0
T35	0	2020	0	0
T37	0	12435	0	0
T38	0	2020	0	0
T39	0	12435	0	0
T40	0	1241	0	0
T41	0	12435	0	0
T42	0	26269	0	0
T47	15666	0	0	0
T48	13744	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	28963470	0	0
T20	54961	47269	0	0
T21	34632	20517	0	0
T22	54961	47269	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T34	0	47269	0	0
T35	0	24063	0	0
T36	0	20517	0	0
T47	15666	0	0	0
T48	13744	0	0	0
T49	0	2856	0	0
T54	0	8571	0	0
T64	0	2856	0	0
T65	0	2856	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	78	89.66
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	57	86.36
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	0	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	0	1
310	0	1
311	0	1
			==> MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	30	85.71
Logical	35	30	85.71
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T18,T19,T20
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T20,T21,T26
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T20,T21,T26
1	Covered	T54,T55,T56

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T27,T28

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T19,T26

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T26

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T49
1	1	Covered	T20,T21,T26

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T21,T26
1	Covered	T18,T19,T20

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T20,T21,T26
1	Covered	T18,T19,T20

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T21,T22

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	9	69.23
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T29
IdleSt	199	Covered	T29
InitSt	175	Covered	T29
InitWaitSt	185	Covered	T29
ReadSt	221	Covered	T29
ReadWaitSt	239	Covered	T29
ResetSt	173	Covered	T29

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T29
IdleSt->ReadSt	221	Covered	T29
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Covered	T29
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Covered	T29
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T29
ReadSt->ReadWaitSt	239	Covered	T29
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T29
ResetSt->ErrorSt	309	Covered	T29
ResetSt->InitSt	175	Covered	T29

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	4	80.00	(Not included in score)
Transitions	11	7	63.64
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T29
CheckFailError	311	Not Covered
FsmStateError	283	Covered	T29
MacroEccCorrError	206	Covered	T29
NoError	220	Covered	T29

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T29
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T29
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Not Covered
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T29
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T29
MacroEccCorrError->NoError	220	Not Covered
NoError->AccessError	243	Covered	T29
NoError->CheckFailError	311	Not Covered
NoError->FsmStateError	283	Covered	T29
NoError->MacroEccCorrError	206	Covered	T29

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	39	88.64
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	1	33.33
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T26
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T21,T26

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T21,T26

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T20,T21,T26
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T35,T38,T42
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T23,T24
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T54,T55,T56
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T20,T21,T26
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T20,T21,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T18,T19,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T18,T19,T26
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T26
1	0	Covered	T18,T19,T26
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	24	92.31
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	24	92.31

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1570944001	1569874661	0	0
DigestKnown_A	1570944001	1569874661	0	0
DigestOffsetMustBeRepresentable_A	1168	1168	0	0
EccErrorState_A	1570944001	0	0	0
ErrorKnown_A	1570944001	1569874661	0	0
FsmStateKnown_A	1570944001	1569874661	0	0
InitDoneKnown_A	1570944001	1569874661	0	0
InitReadLocksPartition_A	1570944001	384176004	0	0
InitWriteLocksPartition_A	1570944001	384176004	0	0
OffsetMustBeBlockAligned_A	1168	1168	0	0
OtpAddrKnown_A	1570944001	1569874661	0	0
OtpCmdKnown_A	1570944001	1569874661	0	0
OtpErrorState_A	1570944001	0	0	0
OtpReqKnown_A	1570944001	1569874661	0	0
OtpSizeKnown_A	1570944001	1569874661	0	0
OtpWdataKnown_A	1570944001	1569874661	0	0
ReadLockPropagation_A	1570944001	43820890	0	0
SizeMustBeBlockAligned_A	1168	1168	0	0
TlulGntKnown_A	1570944001	1569874661	0	0
TlulRdataKnown_A	1570944001	1569874661	0	0
TlulReadOnReadLock_A	1570944001	10805	0	0
TlulRerrorKnown_A	1570944001	1569874661	0	0
TlulRvalidKnown_A	1570944001	1569874661	0	0
WriteLockPropagation_A	1570944001	875950	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1570944001	26883530	0	0
u_state_regs_A	1570944001	1569874661	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	384176004	0	0
T18	853907	121074	0	0
T19	38999	28698	0	0
T20	54961	1269	0	0
T21	34632	1220	0	0
T22	54961	1269	0	0
T26	15666	5335	0	0
T30	7104	141	0	0
T31	13744	517	0	0
T32	15666	5335	0	0
T33	13744	517	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	384176004	0	0
T18	853907	121074	0	0
T19	38999	28698	0	0
T20	54961	1269	0	0
T21	34632	1220	0	0
T22	54961	1269	0	0
T26	15666	5335	0	0
T30	7104	141	0	0
T31	13744	517	0	0
T32	15666	5335	0	0
T33	13744	517	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	43820890	0	0
T19	38999	31760	0	0
T20	54961	0	0	0
T21	34632	1300	0	0
T22	54961	0	0	0
T23	0	380968	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T35	0	847	0	0
T36	0	1300	0	0
T47	15666	0	0	0
T49	0	1112	0	0
T54	0	5148	0	0
T64	0	1112	0	0
T65	0	1112	0	0
T66	0	1112	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	10805	0	0
T18	853907	55	0	0
T19	38999	31	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T23	0	59	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T49	0	1	0	0
T54	0	9	0	0
T55	0	9	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	875950	0	0
T20	54961	1236	0	0
T21	34632	2412	0	0
T22	54961	1236	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T34	0	1236	0	0
T35	0	2227	0	0
T36	0	2412	0	0
T37	0	1236	0	0
T38	0	2227	0	0
T39	0	1236	0	0
T41	0	1236	0	0
T47	15666	0	0	0
T48	13744	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	26883530	0	0
T20	54961	47150	0	0
T21	34632	20415	0	0
T22	54961	47150	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T34	0	47150	0	0
T35	0	30426	0	0
T36	0	20415	0	0
T47	15666	0	0	0
T48	13744	0	0	0
T49	0	2839	0	0
T54	0	15826	0	0
T64	0	2839	0	0
T65	0	2839	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		84	81	96.43
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	63	60	95.24
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	0	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270		excluded
			Exclude Annotation: VC_COV_UNR
271		excluded
			Exclude Annotation: VC_COV_UNR
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	39	86.67
Logical	45	39	86.67
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T18,T19,T20
1	0	Not Covered

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T18,T19,T20
-	1	Not Covered

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Not Covered

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T20,T26,T22
1	0	Covered	T54,T55,T56

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T20,T26,T22
-	1	Covered	T54,T55,T56

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T54,T55,T56

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T54,T55,T56

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T27,T28

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T26,T32,T47
1	Covered	T26,T32,T47

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T18,T19,T26
1	Covered	T18,T19,T49

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T20,T26,T22

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T18,T19,T49
1	1	Covered	T20,T26,T22

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T18,T19,T20

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T20,T26,T22
1	Covered	T18,T19,T20

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T18,T19,T20

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T42,T44,T50

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T42,T44,T50

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	9	69.23
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T29
IdleSt	199	Covered	T29
InitSt	175	Covered	T29
InitWaitSt	185	Covered	T29
ReadSt	221	Covered	T29
ReadWaitSt	239	Covered	T29
ResetSt	173	Covered	T29

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T29
IdleSt->ReadSt	221	Covered	T29
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Covered	T29
InitWaitSt->ErrorSt	209	Not Covered
InitWaitSt->IdleSt	199	Covered	T29
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T29
ReadSt->ReadWaitSt	239	Covered	T29
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T29
ResetSt->ErrorSt	309	Covered	T29
ResetSt->InitSt	175	Covered	T29

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T29
CheckFailError	311	Covered	T29
FsmStateError	283	Covered	T29
MacroEccCorrError	206	Covered	T29
NoError	220	Covered	T29

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T29
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T29
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T29
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T29
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T29
MacroEccCorrError->NoError	220	Covered	T29
NoError->AccessError	243	Covered	T29
NoError->CheckFailError	311	Covered	T29
NoError->FsmStateError	283	Covered	T29
NoError->MacroEccCorrError	206	Covered	T29

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	40	90.91
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	19	82.61
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T26,T22
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T26,T22

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T20,T26,T22

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T44,T50
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T19,T20,T26
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T18,T19,T20
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T20,T26,T22
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T42,T44,T50
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T19,T23,T24
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T54,T55,T56
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T20,T26,T22
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T20,T26,T22
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T18,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T18,T19,T26
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T18,T19,T49
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T18,T19,T26
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T27,T28

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T26,T32,T47
1	0	Covered	T26,T32,T47
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T19,T49
1	0	Covered	T18,T19,T26
0	-	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T19,T20
0	1	Covered	T18,T19,T20
0	0	Covered	T18,T19,T20

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	1570944001	1569874661	0	0
DigestKnown_A	1570944001	1569874661	0	0
DigestOffsetMustBeRepresentable_A	1168	1168	0	0
EccErrorState_A	1570944001	1158600	0	0
ErrorKnown_A	1570944001	1569874661	0	0
FsmStateKnown_A	1570944001	1569874661	0	0
InitDoneKnown_A	1570944001	1569874661	0	0
InitReadLocksPartition_A	1570944001	383731372	0	0
InitWriteLocksPartition_A	1570944001	383731372	0	0
OffsetMustBeBlockAligned_A	1168	1168	0	0
OtpAddrKnown_A	1570944001	1569874661	0	0
OtpCmdKnown_A	1570944001	1569874661	0	0
OtpErrorState_A	1570944001	0	0	0
OtpReqKnown_A	1570944001	1569874661	0	0
OtpSizeKnown_A	1570944001	1569874661	0	0
OtpWdataKnown_A	1570944001	1569874661	0	0
ReadLockPropagation_A	1570944001	44728150	0	0
SizeMustBeBlockAligned_A	1168	1168	0	0
TlulGntKnown_A	1570944001	1569874661	0	0
TlulRdataKnown_A	1570944001	1569874661	0	0
TlulReadOnReadLock_A	1570944001	10735	0	0
TlulRerrorKnown_A	1570944001	1569874661	0	0
TlulRvalidKnown_A	1570944001	1569874661	0	0
WriteLockPropagation_A	1570944001	88600	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	1570944001	2612350	0	0
u_state_regs_A	1570944001	1569874661	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1158600	0	0
T22	54961	0	0	0
T26	15666	3862	0	0
T31	13744	0	0	0
T32	15666	3862	0	0
T33	13744	0	0	0
T34	54961	0	0	0
T35	48639	0	0	0
T47	15666	3862	0	0
T48	13744	0	0	0
T49	17690	0	0	0
T57	0	3862	0	0
T58	0	3862	0	0
T59	0	3862	0	0
T60	0	3862	0	0
T61	0	3862	0	0
T62	0	3862	0	0
T63	0	3862	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	383731372	0	0
T18	853907	110840	0	0
T19	38999	28562	0	0
T20	54961	969	0	0
T21	34632	920	0	0
T22	54961	969	0	0
T26	15666	5267	0	0
T30	7104	107	0	0
T31	13744	381	0	0
T32	15666	5267	0	0
T33	13744	381	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	383731372	0	0
T18	853907	110840	0	0
T19	38999	28562	0	0
T20	54961	969	0	0
T21	34632	920	0	0
T22	54961	969	0	0
T26	15666	5267	0	0
T30	7104	107	0	0
T31	13744	381	0	0
T32	15666	5267	0	0
T33	13744	381	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	44728150	0	0
T19	38999	31681	0	0
T20	54961	1282	0	0
T21	34632	2904	0	0
T22	54961	1282	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T34	0	1282	0	0
T35	0	692	0	0
T36	0	2904	0	0
T47	15666	0	0	0
T49	0	1033	0	0
T54	0	3728	0	0
T64	0	1033	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168	1168	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T26	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	10735	0	0
T18	853907	3	0	0
T19	38999	29	0	0
T20	54961	0	0	0
T21	34632	0	0	0
T22	54961	0	0	0
T23	0	63	0	0
T26	15666	0	0	0
T30	7104	0	0	0
T31	13744	0	0	0
T32	15666	0	0	0
T33	13744	0	0	0
T49	0	3	0	0
T54	0	12	0	0
T55	0	12	0	0
T64	0	3	0	0
T65	0	3	0	0
T66	0	3	0	0
T67	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	88600	0	0
T42	710720	1772	0	0
T43	61495	0	0	0
T44	710720	1772	0	0
T50	710720	1772	0	0
T51	0	1772	0	0
T68	0	1772	0	0
T69	0	1772	0	0
T70	0	1772	0	0
T71	0	1772	0	0
T72	0	1772	0	0
T73	0	1772	0	0
T74	15666	0	0	0
T75	15666	0	0	0
T76	150268	0	0	0
T77	38999	0	0	0
T78	17690	0	0	0
T79	150268	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	2612350	0	0
T42	710720	52247	0	0
T43	61495	0	0	0
T44	710720	52247	0	0
T50	710720	52247	0	0
T51	0	52247	0	0
T68	0	52247	0	0
T69	0	52247	0	0
T70	0	52247	0	0
T71	0	52247	0	0
T72	0	52247	0	0
T73	0	52247	0	0
T74	15666	0	0	0
T75	15666	0	0	0
T76	150268	0	0	0
T77	38999	0	0	0
T78	17690	0	0	0
T79	150268	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1570944001	1569874661	0	0
T18	853907	833557	0	0
T19	38999	38780	0	0
T20	54961	54254	0	0
T21	34632	33853	0	0
T22	54961	54254	0	0
T26	15666	15441	0	0
T30	7104	7044	0	0
T31	13744	13492	0	0
T32	15666	15441	0	0
T33	13744	13492	0	0