Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
33.20	22.22	27.78	13.35	0.00	22.77	99.69	46.58

Total tests in report: 174

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
30.69	30.69	21.69	21.69	24.40	24.40	35.91	35.91	0.00	0.00	22.09	22.09	95.79	95.79	14.94	14.94	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.4023027772
33.83	3.14	21.75	0.06	25.08	0.68	36.84	0.93	0.00	0.00	22.25	0.16	95.79	0.00	35.11	20.17	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.502978893
34.86	1.03	21.96	0.21	26.38	1.30	37.10	0.26	0.00	0.00	22.30	0.05	95.79	0.00	40.51	5.40	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1780662739
35.45	0.59	22.09	0.13	26.85	0.46	37.15	0.06	0.00	0.00	22.51	0.21	95.94	0.16	43.63	3.12	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.717893768
36.00	0.55	22.22	0.13	27.42	0.57	37.15	0.00	0.00	0.00	22.83	0.32	98.44	2.50	43.97	0.34	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.774605593
36.22	0.21	22.22	0.00	27.42	0.00	37.19	0.04	0.00	0.00	22.83	0.00	98.44	0.00	45.40	1.43	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1995692120
36.35	0.14	22.22	0.00	27.44	0.03	37.19	0.00	0.00	0.00	22.83	0.00	99.22	0.78	45.57	0.17	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.545050540
36.43	0.08	22.22	0.00	27.50	0.05	37.19	0.00	0.00	0.00	22.83	0.00	99.53	0.31	45.74	0.17	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1950817925
36.48	0.05	22.22	0.00	27.69	0.19	37.19	0.00	0.00	0.00	22.83	0.00	99.53	0.00	45.91	0.17	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3098609704
36.53	0.05	22.22	0.00	27.69	0.00	37.21	0.02	0.00	0.00	22.83	0.00	99.53	0.00	46.24	0.34	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2938240984
36.57	0.04	22.22	0.00	27.69	0.00	37.21	0.00	0.00	0.00	22.83	0.00	99.53	0.00	46.50	0.25	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2754045712
36.59	0.02	22.22	0.00	27.69	0.00	37.21	0.00	0.00	0.00	22.83	0.00	99.69	0.16	46.50	0.00	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2366174348
36.61	0.02	22.22	0.00	27.74	0.05	37.21	0.00	0.00	0.00	22.83	0.00	99.69	0.00	46.58	0.08	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1112468607
36.62	0.01	22.22	0.00	27.82	0.08	37.21	0.00	0.00	0.00	22.83	0.00	99.69	0.00	46.58	0.00	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1051835865
36.63	0.01	22.22	0.00	27.82	0.00	37.23	0.02	0.00	0.00	22.83	0.00	99.69	0.00	46.58	0.00	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.280952255
36.63	0.01	22.24	0.02	27.82	0.00	37.23	0.00	0.00	0.00	22.83	0.00	99.69	0.00	46.58	0.00	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1526618886

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2776096872
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1018597563
/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2949864537
/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2230127541
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3246758421
/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3374274637
/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4207173570
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4133661355
/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.10415415
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3601423536
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1223887603
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.4192365510
/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3476502774
/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2861445742
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2878279922
/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2263733660
/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3149425012
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1969908680
/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1755676463
/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3577565034
/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.173813320
/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1405226651
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3458651714
/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.163209738
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1204683270
/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2765321906
/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.64612152
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4266997310
/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3069343876
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1258891223
/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1458856681
/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3482108369
/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1531094658
/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.4152251028
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2639885750
/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2698178512
/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1100399242
/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1437678511
/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2307985971
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2977574961
/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.4025879609
/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.4200540617
/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3439694076
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2180478652
/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.896053946
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.360392138
/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.4030524720
/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3346694905
/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2872078148
/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1199032540
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4160561346
/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1016822443
/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1158632349
/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3559650554
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1639878308
/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1955818470
/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.318933642
/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.355024180
/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.4077617827
/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2208597897
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1591926187
/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1693876058
/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1966903533
/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.136102971
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1803027377
/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2674341935
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.26056192
/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1353421455
/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3772489962
/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1877042349
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3810613363
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3538641455
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.266980099
/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2015098935
/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2672345872
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3316681697
/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1811188312
/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2278281686
/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2787045954
/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2482704140
/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.749998459
/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3386563997
/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1347931057
/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3607155054
/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2641370117
/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3988575188
/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3275874629
/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2175370442
/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2821247083
/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3886210371
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3424823676
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1887999069
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2755807823
/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2285401568
/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1025591457
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3123734390
/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3959165416
/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4189782448
/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1265516393
/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.398038311
/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2969052222
/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2322090532
/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2696876633
/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.369860584
/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2785638700
/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2578191507
/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2601605529
/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2773447670
/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2608627125
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3249146536
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1820302760
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4207539119
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.147301594
/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2024229788
/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1789641504
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2486859727
/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2724456284
/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.884019907
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3538317391
/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3912183377
/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2444726822
/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.509845061
/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1390994269
/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1280847326
/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2697992570
/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.966896777
/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3549409599
/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.311757273
/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2884497565
/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3089304489
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2579350935
/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.21799182
/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3800900741
/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.279192483
/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2699006110
/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1732632286
/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3860463143
/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3103596694
/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2928497841
/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1320948584
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1684221723
/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.127516463
/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.717873891
/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1033005767
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3455022623
/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1199997648
/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.4131040861
/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2210277873
/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.968934181
/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2171464453
/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.484494015
/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.597105160
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3537091611
/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2883010567
/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1017398277
/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1364611387
/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.348662232
/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4025885571

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Total test records in report: 174

---

tests.html | tests1.html | tests2.html

---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2821247083			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:27 PM PST 23	50942388 ps
T2	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3098609704			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:40 PM PST 23	2390935909 ps
T3	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.545050540			Dec 20 12:37:25 PM PST 23	Dec 20 12:38:39 PM PST 23	203106382 ps
T7	/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2884497565			Dec 20 12:37:15 PM PST 23	Dec 20 12:38:11 PM PST 23	37649708 ps
T6	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1199032540			Dec 20 12:37:04 PM PST 23	Dec 20 12:37:50 PM PST 23	780983627 ps
T15	/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2175370442			Dec 20 12:37:18 PM PST 23	Dec 20 12:38:18 PM PST 23	71526809 ps
T4	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.4023027772			Dec 20 12:37:01 PM PST 23	Dec 20 12:37:42 PM PST 23	137712472 ps
T14	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1639878308			Dec 20 12:36:53 PM PST 23	Dec 20 12:37:32 PM PST 23	516277182 ps
T9	/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3549409599			Dec 20 12:37:01 PM PST 23	Dec 20 12:37:41 PM PST 23	81065146 ps
T8	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1223887603			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:25 PM PST 23	3699776434 ps
T21	/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3482108369			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:23 PM PST 23	66771957 ps
T5	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1955818470			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:43 PM PST 23	1126755107 ps
T68	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.509845061			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:28 PM PST 23	538424656 ps
T16	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1780662739			Dec 20 12:37:23 PM PST 23	Dec 20 12:38:34 PM PST 23	548922287 ps
T10	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.717893768			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:56 PM PST 23	72614750 ps
T69	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2230127541			Dec 20 12:36:56 PM PST 23	Dec 20 12:37:32 PM PST 23	142925764 ps
T96	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3246758421			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:38 PM PST 23	498971938 ps
T13	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1112468607			Dec 20 12:36:26 PM PST 23	Dec 20 12:36:32 PM PST 23	198313236 ps
T11	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.597105160			Dec 20 12:37:10 PM PST 23	Dec 20 12:38:09 PM PST 23	2256683413 ps
T24	/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.136102971			Dec 20 12:36:33 PM PST 23	Dec 20 12:36:40 PM PST 23	161428230 ps
T25	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3439694076			Dec 20 12:37:38 PM PST 23	Dec 20 12:38:56 PM PST 23	101176209 ps
T32	/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2444726822			Dec 20 12:37:07 PM PST 23	Dec 20 12:37:48 PM PST 23	40712438 ps
T33	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3346694905			Dec 20 12:36:29 PM PST 23	Dec 20 12:36:35 PM PST 23	129586809 ps
T34	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2696876633			Dec 20 12:36:49 PM PST 23	Dec 20 12:37:21 PM PST 23	75634221 ps
T35	/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1158632349			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:27 PM PST 23	41622699 ps
T26	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2698178512			Dec 20 12:36:56 PM PST 23	Dec 20 12:37:34 PM PST 23	39757910 ps
T12	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.502978893			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:38 PM PST 23	18310141429 ps
T36	/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2322090532			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:27 PM PST 23	82197288 ps
T17	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2928497841			Dec 20 12:37:24 PM PST 23	Dec 20 12:38:40 PM PST 23	112410188 ps
T37	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2486859727			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:27 PM PST 23	64072535 ps
T27	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1458856681			Dec 20 12:37:24 PM PST 23	Dec 20 12:38:37 PM PST 23	42508099 ps
T78	/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2861445742			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:06 PM PST 23	76476994 ps
T97	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3123734390			Dec 20 12:36:39 PM PST 23	Dec 20 12:36:53 PM PST 23	81422158 ps
T95	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2754045712			Dec 20 12:36:45 PM PST 23	Dec 20 12:37:14 PM PST 23	72801014 ps
T18	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1204683270			Dec 20 12:36:35 PM PST 23	Dec 20 12:36:44 PM PST 23	124516598 ps
T28	/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1033005767			Dec 20 12:37:09 PM PST 23	Dec 20 12:37:54 PM PST 23	116232824 ps
T22	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1995692120			Dec 20 12:36:39 PM PST 23	Dec 20 12:37:31 PM PST 23	18294088247 ps
T79	/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.311757273			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:42 PM PST 23	68294723 ps
T19	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.484494015			Dec 20 12:37:34 PM PST 23	Dec 20 12:39:08 PM PST 23	3066313948 ps
T29	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4189782448			Dec 20 12:36:30 PM PST 23	Dec 20 12:36:38 PM PST 23	197623879 ps
T20	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.266980099			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:30 PM PST 23	79536882 ps
T23	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4160561346			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:08 PM PST 23	195325983 ps
T30	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3601423536			Dec 20 12:37:03 PM PST 23	Dec 20 12:37:44 PM PST 23	156283818 ps
T98	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.4192365510			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:09 PM PST 23	228894207 ps
T31	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.774605593			Dec 20 12:37:37 PM PST 23	Dec 20 12:38:55 PM PST 23	71459196 ps
T38	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.318933642			Dec 20 12:37:29 PM PST 23	Dec 20 12:38:44 PM PST 23	83528837 ps
T46	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3959165416			Dec 20 12:36:35 PM PST 23	Dec 20 12:36:45 PM PST 23	555491317 ps
T47	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2578191507			Dec 20 12:37:11 PM PST 23	Dec 20 12:37:58 PM PST 23	36611864 ps
T48	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3316681697			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:24 PM PST 23	131283386 ps
T49	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1258891223			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:30 PM PST 23	131834732 ps
T50	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1966903533			Dec 20 12:36:44 PM PST 23	Dec 20 12:37:09 PM PST 23	136349702 ps
T51	/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.4077617827			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:28 PM PST 23	228898532 ps
T39	/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2872078148			Dec 20 12:37:05 PM PST 23	Dec 20 12:37:53 PM PST 23	112764608 ps
T40	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3559650554			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:02 PM PST 23	46646846 ps
T41	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3538641455			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:51 PM PST 23	1241271339 ps
T99	/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2785638700			Dec 20 12:37:18 PM PST 23	Dec 20 12:38:18 PM PST 23	533866691 ps
T42	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.279192483			Dec 20 12:37:15 PM PST 23	Dec 20 12:38:12 PM PST 23	83844676 ps
T100	/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1347931057			Dec 20 12:36:36 PM PST 23	Dec 20 12:36:49 PM PST 23	547284886 ps
T70	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2674341935			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:09 PM PST 23	2684931998 ps
T80	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4266997310			Dec 20 12:36:30 PM PST 23	Dec 20 12:36:38 PM PST 23	89921206 ps
T71	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.360392138			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:44 PM PST 23	104806040 ps
T101	/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1280847326			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:42 PM PST 23	615116298 ps
T102	/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.968934181			Dec 20 12:37:21 PM PST 23	Dec 20 12:38:27 PM PST 23	74570832 ps
T103	/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.369860584			Dec 20 12:37:17 PM PST 23	Dec 20 12:38:13 PM PST 23	75585162 ps
T83	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2787045954			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:33 PM PST 23	126992241 ps
T104	/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2608627125			Dec 20 12:37:06 PM PST 23	Dec 20 12:37:50 PM PST 23	38594288 ps
T105	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.10415415			Dec 20 12:36:53 PM PST 23	Dec 20 12:37:37 PM PST 23	2361727199 ps
T106	/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3860463143			Dec 20 12:37:27 PM PST 23	Dec 20 12:38:42 PM PST 23	593102788 ps
T52	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2210277873			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:04 PM PST 23	70750241 ps
T107	/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.966896777			Dec 20 12:37:20 PM PST 23	Dec 20 12:38:22 PM PST 23	42584079 ps
T53	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2024229788			Dec 20 12:37:00 PM PST 23	Dec 20 12:37:40 PM PST 23	594087384 ps
T89	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2699006110			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:11 PM PST 23	1211086556 ps
T108	/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1017398277			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:29 PM PST 23	40171015 ps
T109	/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.173813320			Dec 20 12:36:37 PM PST 23	Dec 20 12:36:50 PM PST 23	136509890 ps
T110	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3538317391			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:10 PM PST 23	340962927 ps
T43	/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.64612152			Dec 20 12:36:39 PM PST 23	Dec 20 12:36:54 PM PST 23	81253275 ps
T111	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2878279922			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:52 PM PST 23	127310312 ps
T72	/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1405226651			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:31 PM PST 23	235361013 ps
T94	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1877042349			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:39 PM PST 23	2420234428 ps
T82	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1051835865			Dec 20 12:37:12 PM PST 23	Dec 20 12:38:05 PM PST 23	975782919 ps
T112	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1437678511			Dec 20 12:37:42 PM PST 23	Dec 20 12:39:04 PM PST 23	50143587 ps
T113	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1789641504			Dec 20 12:36:45 PM PST 23	Dec 20 12:37:14 PM PST 23	39998523 ps
T114	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3386563997			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:56 PM PST 23	71745363 ps
T44	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1820302760			Dec 20 12:37:28 PM PST 23	Dec 20 12:38:51 PM PST 23	1495772203 ps
T115	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.896053946			Dec 20 12:36:38 PM PST 23	Dec 20 12:37:07 PM PST 23	1274123271 ps
T88	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2938240984			Dec 20 12:36:55 PM PST 23	Dec 20 12:37:51 PM PST 23	3558142959 ps
T81	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4207539119			Dec 20 12:37:19 PM PST 23	Dec 20 12:38:23 PM PST 23	1458203003 ps
T116	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1591926187			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:03 PM PST 23	136781754 ps
T117	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2773447670			Dec 20 12:36:54 PM PST 23	Dec 20 12:37:30 PM PST 23	69570564 ps
T86	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3069343876			Dec 20 12:36:24 PM PST 23	Dec 20 12:36:45 PM PST 23	4943648947 ps
T118	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.749998459			Dec 20 12:36:29 PM PST 23	Dec 20 12:36:35 PM PST 23	88928796 ps
T119	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1390994269			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:52 PM PST 23	72175010 ps
T120	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.163209738			Dec 20 12:36:29 PM PST 23	Dec 20 12:36:58 PM PST 23	9748882832 ps
T45	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1887999069			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:34 PM PST 23	161456038 ps
T64	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.127516463			Dec 20 12:36:51 PM PST 23	Dec 20 12:37:26 PM PST 23	41700239 ps
T54	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2765321906			Dec 20 12:36:51 PM PST 23	Dec 20 12:37:26 PM PST 23	46509014 ps
T55	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1950817925			Dec 20 12:36:32 PM PST 23	Dec 20 12:36:39 PM PST 23	136059838 ps
T65	/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3988575188			Dec 20 12:36:29 PM PST 23	Dec 20 12:36:35 PM PST 23	74421724 ps
T66	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2579350935			Dec 20 12:37:05 PM PST 23	Dec 20 12:37:47 PM PST 23	66127585 ps
T56	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3476502774			Dec 20 12:37:26 PM PST 23	Dec 20 12:38:40 PM PST 23	39156703 ps
T121	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1803027377			Dec 20 12:36:42 PM PST 23	Dec 20 12:37:03 PM PST 23	105798770 ps
T122	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2977574961			Dec 20 12:37:31 PM PST 23	Dec 20 12:38:47 PM PST 23	75339111 ps
T123	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3772489962			Dec 20 12:36:34 PM PST 23	Dec 20 12:36:42 PM PST 23	67908017 ps
T57	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2015098935			Dec 20 12:37:30 PM PST 23	Dec 20 12:38:46 PM PST 23	145717871 ps
T124	/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.717873891			Dec 20 12:36:59 PM PST 23	Dec 20 12:37:37 PM PST 23	73350634 ps
T125	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3089304489			Dec 20 12:37:17 PM PST 23	Dec 20 12:38:12 PM PST 23	55252651 ps
T126	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1016822443			Dec 20 12:37:06 PM PST 23	Dec 20 12:37:47 PM PST 23	41183712 ps
T127	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.280952255			Dec 20 12:37:01 PM PST 23	Dec 20 12:37:47 PM PST 23	913540262 ps
T128	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2949864537			Dec 20 12:37:35 PM PST 23	Dec 20 12:38:51 PM PST 23	62057400 ps
T129	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2601605529			Dec 20 12:37:04 PM PST 23	Dec 20 12:37:44 PM PST 23	38194155 ps
T130	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.4030524720			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:52 PM PST 23	40842045 ps
T58	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1353421455			Dec 20 12:36:32 PM PST 23	Dec 20 12:36:40 PM PST 23	583148930 ps
T67	/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3800900741			Dec 20 12:37:30 PM PST 23	Dec 20 12:38:50 PM PST 23	125256449 ps
T59	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3577565034			Dec 20 12:36:40 PM PST 23	Dec 20 12:36:55 PM PST 23	135294203 ps
T131	/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1025591457			Dec 20 12:36:34 PM PST 23	Dec 20 12:36:42 PM PST 23	138507823 ps
T73	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.147301594			Dec 20 12:36:54 PM PST 23	Dec 20 12:37:32 PM PST 23	144858900 ps
T132	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2697992570			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:29 PM PST 23	567149766 ps
T133	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2755807823			Dec 20 12:36:29 PM PST 23	Dec 20 12:36:38 PM PST 23	207345883 ps
T134	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1693876058			Dec 20 12:36:32 PM PST 23	Dec 20 12:36:40 PM PST 23	42442835 ps
T135	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1265516393			Dec 20 12:36:28 PM PST 23	Dec 20 12:36:37 PM PST 23	378687212 ps
T136	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2307985971			Dec 20 12:36:50 PM PST 23	Dec 20 12:37:26 PM PST 23	192476852 ps
T90	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3912183377			Dec 20 12:36:31 PM PST 23	Dec 20 12:36:52 PM PST 23	1219358169 ps
T137	/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2672345872			Dec 20 12:37:40 PM PST 23	Dec 20 12:38:54 PM PST 23	84939644 ps
T138	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.4152251028			Dec 20 12:36:42 PM PST 23	Dec 20 12:37:06 PM PST 23	1470277666 ps
T139	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.4131040861			Dec 20 12:37:18 PM PST 23	Dec 20 12:38:18 PM PST 23	74226429 ps
T140	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2171464453			Dec 20 12:37:09 PM PST 23	Dec 20 12:37:55 PM PST 23	246883980 ps
T141	/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.4200540617			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:55 PM PST 23	84856294 ps
T87	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4025885571			Dec 20 12:36:31 PM PST 23	Dec 20 12:36:59 PM PST 23	1275197515 ps
T84	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3458651714			Dec 20 12:36:27 PM PST 23	Dec 20 12:36:33 PM PST 23	63864029 ps
T142	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.355024180			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:54 PM PST 23	49315484 ps
T143	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4133661355			Dec 20 12:37:09 PM PST 23	Dec 20 12:37:55 PM PST 23	400767410 ps
T144	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1531094658			Dec 20 12:37:29 PM PST 23	Dec 20 12:38:45 PM PST 23	253091844 ps
T85	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1320948584			Dec 20 12:37:13 PM PST 23	Dec 20 12:38:21 PM PST 23	4595090270 ps
T145	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3455022623			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:53 PM PST 23	852338996 ps
T146	/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1100399242			Dec 20 12:37:15 PM PST 23	Dec 20 12:38:08 PM PST 23	52346761 ps
T147	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.348662232			Dec 20 12:37:09 PM PST 23	Dec 20 12:37:54 PM PST 23	99069852 ps
T74	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1018597563			Dec 20 12:36:59 PM PST 23	Dec 20 12:37:39 PM PST 23	144821509 ps
T75	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3537091611			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:36 PM PST 23	99453415 ps
T148	/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2278281686			Dec 20 12:36:34 PM PST 23	Dec 20 12:36:44 PM PST 23	198248817 ps
T149	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1684221723			Dec 20 12:37:20 PM PST 23	Dec 20 12:38:25 PM PST 23	126216178 ps
T150	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1526618886			Dec 20 12:37:25 PM PST 23	Dec 20 12:38:41 PM PST 23	364088828 ps
T92	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2208597897			Dec 20 12:37:11 PM PST 23	Dec 20 12:38:18 PM PST 23	1481147385 ps
T151	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.4025879609			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:56 PM PST 23	539214384 ps
T152	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1969908680			Dec 20 12:37:22 PM PST 23	Dec 20 12:38:30 PM PST 23	73913717 ps
T153	/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4207173570			Dec 20 12:37:11 PM PST 23	Dec 20 12:37:57 PM PST 23	624171156 ps
T154	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1732632286			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:56 PM PST 23	39252541 ps
T155	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2263733660			Dec 20 12:37:01 PM PST 23	Dec 20 12:37:42 PM PST 23	35868918 ps
T156	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1199997648			Dec 20 12:37:04 PM PST 23	Dec 20 12:37:56 PM PST 23	1034587980 ps
T157	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3249146536			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:39 PM PST 23	341105429 ps
T93	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.398038311			Dec 20 12:36:35 PM PST 23	Dec 20 12:36:55 PM PST 23	1229532478 ps
T158	/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1364611387			Dec 20 12:37:02 PM PST 23	Dec 20 12:37:42 PM PST 23	170332904 ps
T159	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2969052222			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:34 PM PST 23	580366279 ps
T160	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3607155054			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:07 PM PST 23	72576736 ps
T161	/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3149425012			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:08 PM PST 23	960582426 ps
T162	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3424823676			Dec 20 12:36:29 PM PST 23	Dec 20 12:36:36 PM PST 23	190402143 ps
T91	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2482704140			Dec 20 12:37:34 PM PST 23	Dec 20 12:39:08 PM PST 23	1184423855 ps
T163	/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3275874629			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:36 PM PST 23	51828847 ps
T164	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2641370117			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:35 PM PST 23	40610177 ps
T76	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.26056192			Dec 20 12:36:32 PM PST 23	Dec 20 12:36:39 PM PST 23	401225249 ps
T165	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2724456284			Dec 20 12:36:56 PM PST 23	Dec 20 12:37:34 PM PST 23	531519317 ps
T166	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1811188312			Dec 20 12:37:18 PM PST 23	Dec 20 12:38:15 PM PST 23	35517700 ps
T77	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2639885750			Dec 20 12:37:08 PM PST 23	Dec 20 12:37:54 PM PST 23	1135231476 ps
T60	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2776096872			Dec 20 12:37:14 PM PST 23	Dec 20 12:38:08 PM PST 23	337480202 ps
T167	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2883010567			Dec 20 12:36:55 PM PST 23	Dec 20 12:37:32 PM PST 23	39724572 ps
T61	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2366174348			Dec 20 12:37:37 PM PST 23	Dec 20 12:38:57 PM PST 23	211483233 ps
T63	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2285401568			Dec 20 12:37:00 PM PST 23	Dec 20 12:37:39 PM PST 23	73012608 ps
T168	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3103596694			Dec 20 12:37:26 PM PST 23	Dec 20 12:38:41 PM PST 23	194075736 ps
T169	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.884019907			Dec 20 12:37:31 PM PST 23	Dec 20 12:38:47 PM PST 23	68233789 ps
T170	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3810613363			Dec 20 12:37:10 PM PST 23	Dec 20 12:37:59 PM PST 23	1930640036 ps
T171	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1755676463			Dec 20 12:37:08 PM PST 23	Dec 20 12:38:00 PM PST 23	1222743403 ps
T172	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3374274637			Dec 20 12:36:52 PM PST 23	Dec 20 12:37:27 PM PST 23	126313481 ps
T173	/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3886210371			Dec 20 12:36:46 PM PST 23	Dec 20 12:37:14 PM PST 23	47388491 ps
T174	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2180478652			Dec 20 12:36:58 PM PST 23	Dec 20 12:37:40 PM PST 23	151956266 ps
T62	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.21799182			Dec 20 12:36:57 PM PST 23	Dec 20 12:37:35 PM PST 23	163968708 ps

---

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.4023027772
Short name	T4
Test name
Test status
Simulation time	137712472 ps
CPU time	2.16 seconds
Started	Dec 20 12:37:01 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	237992 kb
Host	smart-c0c17563-f1e7-49ec-870b-842f3bfc3c4d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023027772 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.4023027772
Directory	/workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.502978893
Short name	T12
Test name
Test status
Simulation time	18310141429 ps
CPU time	37.59 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:38 PM PST 23
Peak memory	238016 kb
Host	smart-c52a130a-c57b-4e1a-b1da-3475a47cef87
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502978893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_in tg_err.502978893
Directory	/workspace/12.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1780662739
Short name	T16
Test name
Test status
Simulation time	548922287 ps
CPU time	6.04 seconds
Started	Dec 20 12:37:23 PM PST 23
Finished	Dec 20 12:38:34 PM PST 23
Peak memory	237636 kb
Host	smart-2eb39b7c-c796-4518-b6c8-10b4e2fd9547
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780662739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1780662739
Directory	/workspace/17.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.717893768
Short name	T10
Test name
Test status
Simulation time	72614750 ps
CPU time	1.48 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	229544 kb
Host	smart-3f349faa-7740-484c-b3ce-28310e221f23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717893768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.717893768
Directory	/workspace/38.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.774605593
Short name	T31
Test name
Test status
Simulation time	71459196 ps
CPU time	1.69 seconds
Started	Dec 20 12:37:37 PM PST 23
Finished	Dec 20 12:38:55 PM PST 23
Peak memory	229704 kb
Host	smart-4e2b7e68-dd21-4756-8964-6d06dc7b9fb0
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774605593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_re set.774605593
Directory	/workspace/1.otp_ctrl_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1995692120
Short name	T22
Test name
Test status
Simulation time	18294088247 ps
CPU time	39.99 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:37:31 PM PST 23
Peak memory	229864 kb
Host	smart-3e88d37c-0586-4fdf-b96c-2be92898545d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995692120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i ntg_err.1995692120
Directory	/workspace/15.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.545050540
Short name	T3
Test name
Test status
Simulation time	203106382 ps
CPU time	2.55 seconds
Started	Dec 20 12:37:25 PM PST 23
Finished	Dec 20 12:38:39 PM PST 23
Peak memory	229744 kb
Host	smart-0eebe1d8-fa73-451e-9808-1833cf3a4492
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545050540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_c trl_same_csr_outstanding.545050540
Directory	/workspace/19.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1950817925
Short name	T55
Test name
Test status
Simulation time	136059838 ps
CPU time	2.08 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	229664 kb
Host	smart-394eee89-d1c4-4446-b3ea-e6d06f77427a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950817925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r eset.1950817925
Directory	/workspace/3.otp_ctrl_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3098609704
Short name	T2
Test name
Test status
Simulation time	2390935909 ps
CPU time	9.56 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:40 PM PST 23
Peak memory	238048 kb
Host	smart-4f8d0a73-74b5-4cbe-8dba-cf4977097056
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098609704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3098609704
Directory	/workspace/19.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2938240984
Short name	T88
Test name
Test status
Simulation time	3558142959 ps
CPU time	20.1 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:51 PM PST 23
Peak memory	230108 kb
Host	smart-87895d2d-e622-4858-ab02-867c6ea2de7c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938240984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i ntg_err.2938240984
Directory	/workspace/13.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2754045712
Short name	T95
Test name
Test status
Simulation time	72801014 ps
CPU time	1.33 seconds
Started	Dec 20 12:36:45 PM PST 23
Finished	Dec 20 12:37:14 PM PST 23
Peak memory	229628 kb
Host	smart-8345b4c4-ec52-46b9-af89-26bd1a66673e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754045712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2754045712
Directory	/workspace/11.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2366174348
Short name	T61
Test name
Test status
Simulation time	211483233 ps
CPU time	4.05 seconds
Started	Dec 20 12:37:37 PM PST 23
Finished	Dec 20 12:38:57 PM PST 23
Peak memory	229552 kb
Host	smart-37d99418-f07a-45e1-b4c6-a5472482aa3f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366174348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia sing.2366174348
Directory	/workspace/0.otp_ctrl_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1112468607
Short name	T13
Test name
Test status
Simulation time	198313236 ps
CPU time	4.55 seconds
Started	Dec 20 12:36:26 PM PST 23
Finished	Dec 20 12:36:32 PM PST 23
Peak memory	237872 kb
Host	smart-d1e5d236-582d-4c32-8ae2-b5b3aae78778
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112468607 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.1112468607
Directory	/workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1051835865
Short name	T82
Test name
Test status
Simulation time	975782919 ps
CPU time	2.62 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:05 PM PST 23
Peak memory	229520 kb
Host	smart-8511ef75-a2de-403f-91d9-6f7f60a31b8e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051835865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r eset.1051835865
Directory	/workspace/2.otp_ctrl_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.280952255
Short name	T127
Test name
Test status
Simulation time	913540262 ps
CPU time	6.16 seconds
Started	Dec 20 12:37:01 PM PST 23
Finished	Dec 20 12:37:47 PM PST 23
Peak memory	229496 kb
Host	smart-ab248475-c947-4518-be1d-33115fde2035
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280952255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b ash.280952255
Directory	/workspace/0.otp_ctrl_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1526618886
Short name	T150
Test name
Test status
Simulation time	364088828 ps
CPU time	5.14 seconds
Started	Dec 20 12:37:25 PM PST 23
Finished	Dec 20 12:38:41 PM PST 23
Peak memory	237868 kb
Host	smart-f3a5c9b5-42cb-4144-9994-bbaaa2e4bb52
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526618886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1526618886
Directory	/workspace/5.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2776096872
Short name	T60
Test name
Test status
Simulation time	337480202 ps
CPU time	2.21 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:08 PM PST 23
Peak memory	229576 kb
Host	smart-55748d0f-9dd7-4529-9d83-61223971ecc3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776096872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r eset.2776096872
Directory	/workspace/0.otp_ctrl_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.1018597563
Short name	T74
Test name
Test status
Simulation time	144821509 ps
CPU time	2.62 seconds
Started	Dec 20 12:36:59 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	237656 kb
Host	smart-c02e486f-7e38-450d-80fe-591b36aadeb4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018597563 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.1018597563
Directory	/workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2949864537
Short name	T128
Test name
Test status
Simulation time	62057400 ps
CPU time	1.48 seconds
Started	Dec 20 12:37:35 PM PST 23
Finished	Dec 20 12:38:51 PM PST 23
Peak memory	229560 kb
Host	smart-32e775d8-dce8-4921-a021-bd189a68eee6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949864537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2949864537
Directory	/workspace/0.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.2230127541
Short name	T69
Test name
Test status
Simulation time	142925764 ps
CPU time	1.45 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:32 PM PST 23
Peak memory	229316 kb
Host	smart-7e41f711-cfca-400b-810b-445cde06b436
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230127541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2230127541
Directory	/workspace/0.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3246758421
Short name	T96
Test name
Test status
Simulation time	498971938 ps
CPU time	1.72 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:38 PM PST 23
Peak memory	229344 kb
Host	smart-00ac9454-7bc4-48f1-bf8c-1f9820f1f32f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246758421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr l_mem_partial_access.3246758421
Directory	/workspace/0.otp_ctrl_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3374274637
Short name	T172
Test name
Test status
Simulation time	126313481 ps
CPU time	1.37 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:27 PM PST 23
Peak memory	229348 kb
Host	smart-7367195a-3bbf-47fe-89d7-328587e07644
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374274637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk .3374274637
Directory	/workspace/0.otp_ctrl_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4207173570
Short name	T153
Test name
Test status
Simulation time	624171156 ps
CPU time	1.93 seconds
Started	Dec 20 12:37:11 PM PST 23
Finished	Dec 20 12:37:57 PM PST 23
Peak memory	229692 kb
Host	smart-123ad9ca-4470-4a2f-8112-8f10c6fd8a72
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207173570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c trl_same_csr_outstanding.4207173570
Directory	/workspace/0.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4133661355
Short name	T143
Test name
Test status
Simulation time	400767410 ps
CPU time	3.42 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	237720 kb
Host	smart-7764e568-1ef3-4d62-9475-ddb3937a21ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133661355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.4133661355
Directory	/workspace/0.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.10415415
Short name	T105
Test name
Test status
Simulation time	2361727199 ps
CPU time	9.68 seconds
Started	Dec 20 12:36:53 PM PST 23
Finished	Dec 20 12:37:37 PM PST 23
Peak memory	229892 kb
Host	smart-ea6fe1de-4165-4bce-affa-fd43c7d2ce8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10415415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg _err.10415415
Directory	/workspace/0.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3601423536
Short name	T30
Test name
Test status
Simulation time	156283818 ps
CPU time	2.62 seconds
Started	Dec 20 12:37:03 PM PST 23
Finished	Dec 20 12:37:44 PM PST 23
Peak memory	229476 kb
Host	smart-773dcf82-7676-4995-be87-ec436a1f51e0
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601423536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia sing.3601423536
Directory	/workspace/1.otp_ctrl_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1223887603
Short name	T8
Test name
Test status
Simulation time	3699776434 ps
CPU time	5.76 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:25 PM PST 23
Peak memory	229556 kb
Host	smart-0de306b3-5d63-42df-8b25-4dcfdd8a0020
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223887603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_ bash.1223887603
Directory	/workspace/1.otp_ctrl_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.4192365510
Short name	T98
Test name
Test status
Simulation time	228894207 ps
CPU time	3.95 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:09 PM PST 23
Peak memory	237752 kb
Host	smart-f85a08c1-a91e-49ed-b8cb-888e2bc0324b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192365510 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.4192365510
Directory	/workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.3476502774
Short name	T56
Test name
Test status
Simulation time	39156703 ps
CPU time	1.49 seconds
Started	Dec 20 12:37:26 PM PST 23
Finished	Dec 20 12:38:40 PM PST 23
Peak memory	229308 kb
Host	smart-1dbf27a5-f36a-48d8-88ae-7b6428904b9d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476502774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.3476502774
Directory	/workspace/1.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2861445742
Short name	T78
Test name
Test status
Simulation time	76476994 ps
CPU time	1.36 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:06 PM PST 23
Peak memory	229516 kb
Host	smart-5939a24c-d1dc-4808-a9c1-19b7b3bcf407
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861445742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2861445742
Directory	/workspace/1.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2878279922
Short name	T111
Test name
Test status
Simulation time	127310312 ps
CPU time	1.31 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:52 PM PST 23
Peak memory	229276 kb
Host	smart-dc208fe9-56a9-491a-8e23-dcff1daad849
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878279922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr l_mem_partial_access.2878279922
Directory	/workspace/1.otp_ctrl_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2263733660
Short name	T155
Test name
Test status
Simulation time	35868918 ps
CPU time	1.23 seconds
Started	Dec 20 12:37:01 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	229212 kb
Host	smart-77284585-51a0-4852-a001-b94a48e161d4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263733660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk .2263733660
Directory	/workspace/1.otp_ctrl_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.3149425012
Short name	T161
Test name
Test status
Simulation time	960582426 ps
CPU time	2.1 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:08 PM PST 23
Peak memory	229444 kb
Host	smart-afbb576f-5044-4c69-9c66-ac696581c664
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149425012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c trl_same_csr_outstanding.3149425012
Directory	/workspace/1.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1969908680
Short name	T152
Test name
Test status
Simulation time	73913717 ps
CPU time	4.91 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:30 PM PST 23
Peak memory	237896 kb
Host	smart-cbb5d38f-0b8e-4022-a01d-dce2d6e43b69
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969908680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1969908680
Directory	/workspace/1.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1755676463
Short name	T171
Test name
Test status
Simulation time	1222743403 ps
CPU time	9.98 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:38:00 PM PST 23
Peak memory	229932 kb
Host	smart-2585dc44-3c91-4e9b-a5b4-040baae25dd5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755676463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in tg_err.1755676463
Directory	/workspace/1.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3577565034
Short name	T59
Test name
Test status
Simulation time	135294203 ps
CPU time	1.44 seconds
Started	Dec 20 12:36:40 PM PST 23
Finished	Dec 20 12:36:55 PM PST 23
Peak memory	229640 kb
Host	smart-122512c8-34f8-4475-b78b-d8e7964cc061
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577565034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3577565034
Directory	/workspace/10.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.173813320
Short name	T109
Test name
Test status
Simulation time	136509890 ps
CPU time	1.38 seconds
Started	Dec 20 12:36:37 PM PST 23
Finished	Dec 20 12:36:50 PM PST 23
Peak memory	229468 kb
Host	smart-5a1550da-bc6e-4d1e-8ced-265972379484
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173813320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.173813320
Directory	/workspace/10.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1405226651
Short name	T72
Test name
Test status
Simulation time	235361013 ps
CPU time	2 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:31 PM PST 23
Peak memory	229648 kb
Host	smart-5723851d-fb8f-440c-8639-c4a2ac4c23cf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405226651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ ctrl_same_csr_outstanding.1405226651
Directory	/workspace/10.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3458651714
Short name	T84
Test name
Test status
Simulation time	63864029 ps
CPU time	3.06 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:33 PM PST 23
Peak memory	237920 kb
Host	smart-a3c19b9f-68f0-4ce7-9eb6-4572a1ec3203
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458651714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3458651714
Directory	/workspace/10.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.163209738
Short name	T120
Test name
Test status
Simulation time	9748882832 ps
CPU time	23.96 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:58 PM PST 23
Peak memory	229744 kb
Host	smart-6a186028-130b-4b57-a689-d3afd8050ef4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163209738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_in tg_err.163209738
Directory	/workspace/10.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1204683270
Short name	T18
Test name
Test status
Simulation time	124516598 ps
CPU time	2.1 seconds
Started	Dec 20 12:36:35 PM PST 23
Finished	Dec 20 12:36:44 PM PST 23
Peak memory	237756 kb
Host	smart-89d5c1a0-4db1-4e72-9b28-8e7a759c0111
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204683270 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1204683270
Directory	/workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2765321906
Short name	T54
Test name
Test status
Simulation time	46509014 ps
CPU time	1.6 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	229436 kb
Host	smart-1e08ef8e-20fb-4ad4-ac98-b984b1762c7d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765321906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2765321906
Directory	/workspace/11.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.64612152
Short name	T43
Test name
Test status
Simulation time	81253275 ps
CPU time	1.65 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:54 PM PST 23
Peak memory	229552 kb
Host	smart-59b9c71e-66d1-4808-aa91-2c49050cd72c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64612152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ct rl_same_csr_outstanding.64612152
Directory	/workspace/11.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4266997310
Short name	T80
Test name
Test status
Simulation time	89921206 ps
CPU time	3.15 seconds
Started	Dec 20 12:36:30 PM PST 23
Finished	Dec 20 12:36:38 PM PST 23
Peak memory	237888 kb
Host	smart-0459f876-922a-472e-96ee-102bc61d5a9b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266997310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.4266997310
Directory	/workspace/11.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3069343876
Short name	T86
Test name
Test status
Simulation time	4943648947 ps
CPU time	18.8 seconds
Started	Dec 20 12:36:24 PM PST 23
Finished	Dec 20 12:36:45 PM PST 23
Peak memory	230092 kb
Host	smart-786067e4-2960-48a2-9f46-7e26144a0beb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069343876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i ntg_err.3069343876
Directory	/workspace/11.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1258891223
Short name	T49
Test name
Test status
Simulation time	131834732 ps
CPU time	4.22 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:30 PM PST 23
Peak memory	237884 kb
Host	smart-1b1c3135-7cc0-4947-876d-aca1591f6d0c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258891223 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1258891223
Directory	/workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1458856681
Short name	T27
Test name
Test status
Simulation time	42508099 ps
CPU time	1.46 seconds
Started	Dec 20 12:37:24 PM PST 23
Finished	Dec 20 12:38:37 PM PST 23
Peak memory	229456 kb
Host	smart-41f75ad1-69e8-4ac0-98e8-243f9d019c0f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458856681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1458856681
Directory	/workspace/12.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3482108369
Short name	T21
Test name
Test status
Simulation time	66771957 ps
CPU time	1.37 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:23 PM PST 23
Peak memory	229660 kb
Host	smart-94e2545d-d4d9-4ce0-ab8f-88003c8f4cdc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482108369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3482108369
Directory	/workspace/12.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1531094658
Short name	T144
Test name
Test status
Simulation time	253091844 ps
CPU time	2.13 seconds
Started	Dec 20 12:37:29 PM PST 23
Finished	Dec 20 12:38:45 PM PST 23
Peak memory	229548 kb
Host	smart-2075da80-eb05-4bdb-a455-5391cd06ed81
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531094658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ ctrl_same_csr_outstanding.1531094658
Directory	/workspace/12.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.4152251028
Short name	T138
Test name
Test status
Simulation time	1470277666 ps
CPU time	4.96 seconds
Started	Dec 20 12:36:42 PM PST 23
Finished	Dec 20 12:37:06 PM PST 23
Peak memory	237820 kb
Host	smart-fd63449e-dc70-4442-868d-61ec74d065c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152251028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.4152251028
Directory	/workspace/12.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.2639885750
Short name	T77
Test name
Test status
Simulation time	1135231476 ps
CPU time	3.7 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:54 PM PST 23
Peak memory	237896 kb
Host	smart-999b9956-d1a6-4d67-ac13-bef76f7a19f8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639885750 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.2639885750
Directory	/workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2698178512
Short name	T26
Test name
Test status
Simulation time	39757910 ps
CPU time	1.49 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:34 PM PST 23
Peak memory	229592 kb
Host	smart-569d2b95-53e8-4e73-8b6c-98e005d69ba7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698178512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.2698178512
Directory	/workspace/13.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1100399242
Short name	T146
Test name
Test status
Simulation time	52346761 ps
CPU time	1.4 seconds
Started	Dec 20 12:37:15 PM PST 23
Finished	Dec 20 12:38:08 PM PST 23
Peak memory	229480 kb
Host	smart-f459fe77-808c-489d-ab7f-de092d7d1888
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100399242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1100399242
Directory	/workspace/13.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1437678511
Short name	T112
Test name
Test status
Simulation time	50143587 ps
CPU time	2.11 seconds
Started	Dec 20 12:37:42 PM PST 23
Finished	Dec 20 12:39:04 PM PST 23
Peak memory	229612 kb
Host	smart-22600818-ae68-4172-879d-0eba11407e0c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437678511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ ctrl_same_csr_outstanding.1437678511
Directory	/workspace/13.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2307985971
Short name	T136
Test name
Test status
Simulation time	192476852 ps
CPU time	3.91 seconds
Started	Dec 20 12:36:50 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	241796 kb
Host	smart-3c231b3d-f177-4728-aac2-df55596f421b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307985971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2307985971
Directory	/workspace/13.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2977574961
Short name	T122
Test name
Test status
Simulation time	75339111 ps
CPU time	2.31 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:47 PM PST 23
Peak memory	237960 kb
Host	smart-ce3b5958-e082-4d4d-bd71-2c959da994fa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977574961 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2977574961
Directory	/workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.4025879609
Short name	T151
Test name
Test status
Simulation time	539214384 ps
CPU time	1.59 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	229608 kb
Host	smart-351bace5-7744-409b-bcb5-ce7cda8833a3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025879609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.4025879609
Directory	/workspace/14.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.4200540617
Short name	T141
Test name
Test status
Simulation time	84856294 ps
CPU time	1.26 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	229292 kb
Host	smart-f4a1a648-238e-4ed6-a60f-af05b3922258
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200540617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.4200540617
Directory	/workspace/14.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.3439694076
Short name	T25
Test name
Test status
Simulation time	101176209 ps
CPU time	2.42 seconds
Started	Dec 20 12:37:38 PM PST 23
Finished	Dec 20 12:38:56 PM PST 23
Peak memory	229508 kb
Host	smart-8ea0a040-2b31-4a79-9780-e9a961624681
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439694076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ ctrl_same_csr_outstanding.3439694076
Directory	/workspace/14.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2180478652
Short name	T174
Test name
Test status
Simulation time	151956266 ps
CPU time	4.38 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:40 PM PST 23
Peak memory	237928 kb
Host	smart-2aeae2b2-2095-481b-955f-0ec96aefd252
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180478652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2180478652
Directory	/workspace/14.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.896053946
Short name	T115
Test name
Test status
Simulation time	1274123271 ps
CPU time	17.51 seconds
Started	Dec 20 12:36:38 PM PST 23
Finished	Dec 20 12:37:07 PM PST 23
Peak memory	229608 kb
Host	smart-dd895f6d-afed-4894-9341-e04a7d8176d9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896053946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in tg_err.896053946
Directory	/workspace/14.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.360392138
Short name	T71
Test name
Test status
Simulation time	104806040 ps
CPU time	2.57 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:44 PM PST 23
Peak memory	237656 kb
Host	smart-69f29a19-d489-49f4-843c-dd55f69a5248
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360392138 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.360392138
Directory	/workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.4030524720
Short name	T130
Test name
Test status
Simulation time	40842045 ps
CPU time	1.38 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:52 PM PST 23
Peak memory	229484 kb
Host	smart-9d4308dc-5873-428e-9e07-a98a99e43826
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030524720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.4030524720
Directory	/workspace/15.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.3346694905
Short name	T33
Test name
Test status
Simulation time	129586809 ps
CPU time	1.48 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:35 PM PST 23
Peak memory	229492 kb
Host	smart-eda504b1-6499-4eb5-b3c4-73d94499475c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346694905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.3346694905
Directory	/workspace/15.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2872078148
Short name	T39
Test name
Test status
Simulation time	112764608 ps
CPU time	2.71 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:53 PM PST 23
Peak memory	229396 kb
Host	smart-a9106163-a88b-4a71-95f8-6ce8fd715de3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872078148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ ctrl_same_csr_outstanding.2872078148
Directory	/workspace/15.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.1199032540
Short name	T6
Test name
Test status
Simulation time	780983627 ps
CPU time	6.77 seconds
Started	Dec 20 12:37:04 PM PST 23
Finished	Dec 20 12:37:50 PM PST 23
Peak memory	237704 kb
Host	smart-bbdac4c0-4a2e-4c1b-a57c-d4c94e9e0ba8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199032540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.1199032540
Directory	/workspace/15.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.4160561346
Short name	T23
Test name
Test status
Simulation time	195325983 ps
CPU time	3.15 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:08 PM PST 23
Peak memory	237892 kb
Host	smart-07973c52-97c1-4c8f-ba84-1c4e1fa66eb1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160561346 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.4160561346
Directory	/workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1016822443
Short name	T126
Test name
Test status
Simulation time	41183712 ps
CPU time	1.56 seconds
Started	Dec 20 12:37:06 PM PST 23
Finished	Dec 20 12:37:47 PM PST 23
Peak memory	229424 kb
Host	smart-3a859609-186c-474d-bea1-f57093e2cb72
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016822443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1016822443
Directory	/workspace/16.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1158632349
Short name	T35
Test name
Test status
Simulation time	41622699 ps
CPU time	1.25 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:27 PM PST 23
Peak memory	228916 kb
Host	smart-56fadd93-05e2-4cd8-938f-642e15feb6b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158632349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1158632349
Directory	/workspace/16.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.3559650554
Short name	T40
Test name
Test status
Simulation time	46646846 ps
CPU time	1.6 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:02 PM PST 23
Peak memory	229372 kb
Host	smart-a01c03ec-72f4-474e-b705-c1d4a47d3f83
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559650554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ ctrl_same_csr_outstanding.3559650554
Directory	/workspace/16.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1639878308
Short name	T14
Test name
Test status
Simulation time	516277182 ps
CPU time	5.19 seconds
Started	Dec 20 12:36:53 PM PST 23
Finished	Dec 20 12:37:32 PM PST 23
Peak memory	237920 kb
Host	smart-38bfd4dd-ec02-46c5-a80d-8b55f75cdd50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639878308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1639878308
Directory	/workspace/16.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1955818470
Short name	T5
Test name
Test status
Simulation time	1126755107 ps
CPU time	16.26 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:43 PM PST 23
Peak memory	229896 kb
Host	smart-876ccf6b-f15d-4da7-91b7-99d10437b73f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955818470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i ntg_err.1955818470
Directory	/workspace/16.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.318933642
Short name	T38
Test name
Test status
Simulation time	83528837 ps
CPU time	1.66 seconds
Started	Dec 20 12:37:29 PM PST 23
Finished	Dec 20 12:38:44 PM PST 23
Peak memory	229616 kb
Host	smart-8b1c441d-f846-4a83-9702-f55b1579c2f9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318933642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.318933642
Directory	/workspace/17.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.355024180
Short name	T142
Test name
Test status
Simulation time	49315484 ps
CPU time	1.35 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:54 PM PST 23
Peak memory	229444 kb
Host	smart-59ad2e64-c85a-48c9-86d5-3362f43c048b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355024180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.355024180
Directory	/workspace/17.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.4077617827
Short name	T51
Test name
Test status
Simulation time	228898532 ps
CPU time	2.24 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:28 PM PST 23
Peak memory	229616 kb
Host	smart-46cd1460-651a-4a1c-9ec6-c4ba132134bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077617827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ ctrl_same_csr_outstanding.4077617827
Directory	/workspace/17.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2208597897
Short name	T92
Test name
Test status
Simulation time	1481147385 ps
CPU time	19.2 seconds
Started	Dec 20 12:37:11 PM PST 23
Finished	Dec 20 12:38:18 PM PST 23
Peak memory	229708 kb
Host	smart-2822d4fa-b165-4495-937a-43659297b7ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208597897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i ntg_err.2208597897
Directory	/workspace/17.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1591926187
Short name	T116
Test name
Test status
Simulation time	136781754 ps
CPU time	2.28 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:03 PM PST 23
Peak memory	237728 kb
Host	smart-79f1b490-1561-4094-9de4-18e25a837523
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591926187 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1591926187
Directory	/workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.1693876058
Short name	T134
Test name
Test status
Simulation time	42442835 ps
CPU time	1.57 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:40 PM PST 23
Peak memory	229532 kb
Host	smart-375c6d1c-a3a3-4fc7-8d5b-9d254e5ab830
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693876058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.1693876058
Directory	/workspace/18.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.1966903533
Short name	T50
Test name
Test status
Simulation time	136349702 ps
CPU time	1.39 seconds
Started	Dec 20 12:36:44 PM PST 23
Finished	Dec 20 12:37:09 PM PST 23
Peak memory	229268 kb
Host	smart-2355c727-5f89-4bc3-8f69-8f1763a928f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966903533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.1966903533
Directory	/workspace/18.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.136102971
Short name	T24
Test name
Test status
Simulation time	161428230 ps
CPU time	1.82 seconds
Started	Dec 20 12:36:33 PM PST 23
Finished	Dec 20 12:36:40 PM PST 23
Peak memory	229704 kb
Host	smart-16ab6fd9-63af-4b59-93d9-229c254aaeec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136102971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_c trl_same_csr_outstanding.136102971
Directory	/workspace/18.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1803027377
Short name	T121
Test name
Test status
Simulation time	105798770 ps
CPU time	3.4 seconds
Started	Dec 20 12:36:42 PM PST 23
Finished	Dec 20 12:37:03 PM PST 23
Peak memory	237856 kb
Host	smart-b418cddb-a9b7-4482-8156-287b420819df
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803027377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1803027377
Directory	/workspace/18.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2674341935
Short name	T70
Test name
Test status
Simulation time	2684931998 ps
CPU time	9.1 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:09 PM PST 23
Peak memory	229800 kb
Host	smart-e6d2a064-28aa-43c8-b0bf-a656aa2bd7ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674341935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i ntg_err.2674341935
Directory	/workspace/18.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.26056192
Short name	T76
Test name
Test status
Simulation time	401225249 ps
CPU time	2.63 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	237952 kb
Host	smart-5230b52e-f2ab-48fc-b39b-70fb8e5e75fe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26056192 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.26056192
Directory	/workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1353421455
Short name	T58
Test name
Test status
Simulation time	583148930 ps
CPU time	2.05 seconds
Started	Dec 20 12:36:32 PM PST 23
Finished	Dec 20 12:36:40 PM PST 23
Peak memory	229544 kb
Host	smart-94690351-ed3e-4243-a4a8-00d75afd5dfa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353421455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1353421455
Directory	/workspace/19.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3772489962
Short name	T123
Test name
Test status
Simulation time	67908017 ps
CPU time	1.3 seconds
Started	Dec 20 12:36:34 PM PST 23
Finished	Dec 20 12:36:42 PM PST 23
Peak memory	229256 kb
Host	smart-ba5ee2c1-1de9-4b16-acff-d1048c01d5ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772489962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3772489962
Directory	/workspace/19.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1877042349
Short name	T94
Test name
Test status
Simulation time	2420234428 ps
CPU time	9.9 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:39 PM PST 23
Peak memory	229800 kb
Host	smart-a478ab98-60a7-4b0c-8904-5ec010246875
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877042349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i ntg_err.1877042349
Directory	/workspace/19.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3810613363
Short name	T170
Test name
Test status
Simulation time	1930640036 ps
CPU time	4.38 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:59 PM PST 23
Peak memory	229468 kb
Host	smart-a89f1951-f4a4-404a-9858-5b6e072a16ee
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810613363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia sing.3810613363
Directory	/workspace/2.otp_ctrl_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3538641455
Short name	T41
Test name
Test status
Simulation time	1241271339 ps
CPU time	4.73 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:51 PM PST 23
Peak memory	229512 kb
Host	smart-ff52895a-0395-4792-8cdf-2ddd6709d1bd
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538641455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_ bash.3538641455
Directory	/workspace/2.otp_ctrl_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.266980099
Short name	T20
Test name
Test status
Simulation time	79536882 ps
CPU time	1.73 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:30 PM PST 23
Peak memory	237884 kb
Host	smart-754928d6-f0ca-452c-94d0-88af3681fe9c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266980099 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.266980099
Directory	/workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2015098935
Short name	T57
Test name
Test status
Simulation time	145717871 ps
CPU time	1.82 seconds
Started	Dec 20 12:37:30 PM PST 23
Finished	Dec 20 12:38:46 PM PST 23
Peak memory	229584 kb
Host	smart-6d0d825f-3f7c-4411-b478-b08fedab287b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015098935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2015098935
Directory	/workspace/2.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2672345872
Short name	T137
Test name
Test status
Simulation time	84939644 ps
CPU time	1.29 seconds
Started	Dec 20 12:37:40 PM PST 23
Finished	Dec 20 12:38:54 PM PST 23
Peak memory	229148 kb
Host	smart-603934e6-2773-4191-b11e-429a50602af5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672345872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2672345872
Directory	/workspace/2.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.3316681697
Short name	T48
Test name
Test status
Simulation time	131283386 ps
CPU time	1.26 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:24 PM PST 23
Peak memory	229212 kb
Host	smart-c4df5127-e1db-4462-83c0-4cb57bce0fba
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316681697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr l_mem_partial_access.3316681697
Directory	/workspace/2.otp_ctrl_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1811188312
Short name	T166
Test name
Test status
Simulation time	35517700 ps
CPU time	1.3 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:15 PM PST 23
Peak memory	229212 kb
Host	smart-f5649d49-c9b7-4aa0-a574-f6f70277d98c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811188312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk .1811188312
Directory	/workspace/2.otp_ctrl_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2278281686
Short name	T148
Test name
Test status
Simulation time	198248817 ps
CPU time	2.18 seconds
Started	Dec 20 12:36:34 PM PST 23
Finished	Dec 20 12:36:44 PM PST 23
Peak memory	229688 kb
Host	smart-5cc8ec06-5313-40ea-bd26-9eef61b5efd5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278281686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c trl_same_csr_outstanding.2278281686
Directory	/workspace/2.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2787045954
Short name	T83
Test name
Test status
Simulation time	126992241 ps
CPU time	5.3 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:33 PM PST 23
Peak memory	245852 kb
Host	smart-6ab22b8e-65ab-4e2a-a84e-b29e636e4049
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787045954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2787045954
Directory	/workspace/2.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2482704140
Short name	T91
Test name
Test status
Simulation time	1184423855 ps
CPU time	18.36 seconds
Started	Dec 20 12:37:34 PM PST 23
Finished	Dec 20 12:39:08 PM PST 23
Peak memory	229864 kb
Host	smart-d8546b4e-b28b-48f0-a1e1-60803001a78b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482704140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in tg_err.2482704140
Directory	/workspace/2.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.749998459
Short name	T118
Test name
Test status
Simulation time	88928796 ps
CPU time	1.36 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:35 PM PST 23
Peak memory	229420 kb
Host	smart-dbba9db5-109e-4adf-b58e-1ae5df01f58d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749998459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.749998459
Directory	/workspace/20.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3386563997
Short name	T114
Test name
Test status
Simulation time	71745363 ps
CPU time	1.29 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	229252 kb
Host	smart-ebaebb0d-6904-475e-8fc5-a4c0538f219a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386563997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3386563997
Directory	/workspace/21.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1347931057
Short name	T100
Test name
Test status
Simulation time	547284886 ps
CPU time	1.38 seconds
Started	Dec 20 12:36:36 PM PST 23
Finished	Dec 20 12:36:49 PM PST 23
Peak memory	229484 kb
Host	smart-4c99cb06-504d-4f70-8e45-5996734d58a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347931057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1347931057
Directory	/workspace/22.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.3607155054
Short name	T160
Test name
Test status
Simulation time	72576736 ps
CPU time	1.41 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:07 PM PST 23
Peak memory	229264 kb
Host	smart-f5b3563a-e6b0-4345-9611-d7863349fb06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607155054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3607155054
Directory	/workspace/23.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2641370117
Short name	T164
Test name
Test status
Simulation time	40610177 ps
CPU time	1.32 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:35 PM PST 23
Peak memory	229512 kb
Host	smart-733280e6-5fcf-49dc-8f41-750004e06b4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641370117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2641370117
Directory	/workspace/24.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.3988575188
Short name	T65
Test name
Test status
Simulation time	74421724 ps
CPU time	1.42 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:35 PM PST 23
Peak memory	229500 kb
Host	smart-470bf894-8f63-4459-a84d-949460c366a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988575188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3988575188
Directory	/workspace/25.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3275874629
Short name	T163
Test name
Test status
Simulation time	51828847 ps
CPU time	1.41 seconds
Started	Dec 20 12:36:58 PM PST 23
Finished	Dec 20 12:37:36 PM PST 23
Peak memory	229280 kb
Host	smart-04ceefa9-e37b-4451-8695-614a6a81fea6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275874629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3275874629
Directory	/workspace/26.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2175370442
Short name	T15
Test name
Test status
Simulation time	71526809 ps
CPU time	1.37 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:18 PM PST 23
Peak memory	229216 kb
Host	smart-d1d7f69a-9b8c-4ca6-ac69-cb91e732b334
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175370442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2175370442
Directory	/workspace/27.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2821247083
Short name	T1
Test name
Test status
Simulation time	50942388 ps
CPU time	1.4 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:27 PM PST 23
Peak memory	229104 kb
Host	smart-8b5da9a6-26c0-4424-96b9-468267bf4354
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821247083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2821247083
Directory	/workspace/28.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.3886210371
Short name	T173
Test name
Test status
Simulation time	47388491 ps
CPU time	1.34 seconds
Started	Dec 20 12:36:46 PM PST 23
Finished	Dec 20 12:37:14 PM PST 23
Peak memory	229440 kb
Host	smart-a1bda916-7f36-4259-ac6a-d649abf792b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886210371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.3886210371
Directory	/workspace/29.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3424823676
Short name	T162
Test name
Test status
Simulation time	190402143 ps
CPU time	2.43 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:36 PM PST 23
Peak memory	229528 kb
Host	smart-debefbfd-6547-4346-a391-d442ff624c84
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424823676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia sing.3424823676
Directory	/workspace/3.otp_ctrl_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1887999069
Short name	T45
Test name
Test status
Simulation time	161456038 ps
CPU time	3.95 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:34 PM PST 23
Peak memory	229592 kb
Host	smart-7e6dd79a-9a3b-44e5-b6b9-01fcd611b0f4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887999069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_ bash.1887999069
Directory	/workspace/3.otp_ctrl_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2755807823
Short name	T133
Test name
Test status
Simulation time	207345883 ps
CPU time	4.57 seconds
Started	Dec 20 12:36:29 PM PST 23
Finished	Dec 20 12:36:38 PM PST 23
Peak memory	237916 kb
Host	smart-027abcbc-5032-4154-bfa9-e34bc0a13c73
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755807823 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.2755807823
Directory	/workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2285401568
Short name	T63
Test name
Test status
Simulation time	73012608 ps
CPU time	1.49 seconds
Started	Dec 20 12:37:00 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	229672 kb
Host	smart-df879ddc-7d31-467f-92a4-48abdc4f1405
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285401568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2285401568
Directory	/workspace/3.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1025591457
Short name	T131
Test name
Test status
Simulation time	138507823 ps
CPU time	1.4 seconds
Started	Dec 20 12:36:34 PM PST 23
Finished	Dec 20 12:36:42 PM PST 23
Peak memory	229292 kb
Host	smart-48ca1232-d957-4155-b62b-44eabc45b86e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025591457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1025591457
Directory	/workspace/3.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.3123734390
Short name	T97
Test name
Test status
Simulation time	81422158 ps
CPU time	1.27 seconds
Started	Dec 20 12:36:39 PM PST 23
Finished	Dec 20 12:36:53 PM PST 23
Peak memory	229260 kb
Host	smart-45dff9d7-3fb4-4fab-b853-bff3eb546886
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123734390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr l_mem_partial_access.3123734390
Directory	/workspace/3.otp_ctrl_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3959165416
Short name	T46
Test name
Test status
Simulation time	555491317 ps
CPU time	1.3 seconds
Started	Dec 20 12:36:35 PM PST 23
Finished	Dec 20 12:36:45 PM PST 23
Peak memory	229316 kb
Host	smart-d092707d-c89a-475f-92e9-5afae1b7fa78
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959165416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk .3959165416
Directory	/workspace/3.otp_ctrl_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4189782448
Short name	T29
Test name
Test status
Simulation time	197623879 ps
CPU time	2.83 seconds
Started	Dec 20 12:36:30 PM PST 23
Finished	Dec 20 12:36:38 PM PST 23
Peak memory	229716 kb
Host	smart-cce7e1d6-12e2-4bdc-9cb7-e4cd02e7a558
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189782448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c trl_same_csr_outstanding.4189782448
Directory	/workspace/3.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1265516393
Short name	T135
Test name
Test status
Simulation time	378687212 ps
CPU time	4.25 seconds
Started	Dec 20 12:36:28 PM PST 23
Finished	Dec 20 12:36:37 PM PST 23
Peak memory	237808 kb
Host	smart-3e82f233-78d5-4ce9-8395-32cd9d77e255
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265516393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1265516393
Directory	/workspace/3.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.398038311
Short name	T93
Test name
Test status
Simulation time	1229532478 ps
CPU time	10.57 seconds
Started	Dec 20 12:36:35 PM PST 23
Finished	Dec 20 12:36:55 PM PST 23
Peak memory	239924 kb
Host	smart-0821e245-e91b-4f6f-941c-64fc647d5276
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398038311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_int g_err.398038311
Directory	/workspace/3.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.2969052222
Short name	T159
Test name
Test status
Simulation time	580366279 ps
CPU time	1.99 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:34 PM PST 23
Peak memory	229468 kb
Host	smart-91c1525d-1240-428f-a7e6-ca2255c7b148
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969052222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.2969052222
Directory	/workspace/30.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2322090532
Short name	T36
Test name
Test status
Simulation time	82197288 ps
CPU time	1.36 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:27 PM PST 23
Peak memory	229600 kb
Host	smart-543ee8fd-9e4b-47a8-b479-0c2beb4b03eb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322090532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.2322090532
Directory	/workspace/31.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2696876633
Short name	T34
Test name
Test status
Simulation time	75634221 ps
CPU time	1.38 seconds
Started	Dec 20 12:36:49 PM PST 23
Finished	Dec 20 12:37:21 PM PST 23
Peak memory	229472 kb
Host	smart-10ebd99e-9eed-4396-922c-b4dc79b94da3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696876633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2696876633
Directory	/workspace/32.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.369860584
Short name	T103
Test name
Test status
Simulation time	75585162 ps
CPU time	1.36 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:13 PM PST 23
Peak memory	229284 kb
Host	smart-351c2b39-479e-4d4c-b5fd-fcb729cb5819
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369860584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.369860584
Directory	/workspace/33.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.2785638700
Short name	T99
Test name
Test status
Simulation time	533866691 ps
CPU time	1.42 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:18 PM PST 23
Peak memory	229312 kb
Host	smart-761bcd4a-73cf-4614-8c7c-4213402a8b57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785638700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.2785638700
Directory	/workspace/34.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2578191507
Short name	T47
Test name
Test status
Simulation time	36611864 ps
CPU time	1.25 seconds
Started	Dec 20 12:37:11 PM PST 23
Finished	Dec 20 12:37:58 PM PST 23
Peak memory	229320 kb
Host	smart-ea360a85-5689-4e4c-b9ba-1c74c9eaac8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578191507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2578191507
Directory	/workspace/35.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.2601605529
Short name	T129
Test name
Test status
Simulation time	38194155 ps
CPU time	1.36 seconds
Started	Dec 20 12:37:04 PM PST 23
Finished	Dec 20 12:37:44 PM PST 23
Peak memory	229272 kb
Host	smart-e972c9e4-94eb-45da-b44e-ffd3dcecf943
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601605529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.2601605529
Directory	/workspace/36.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2773447670
Short name	T117
Test name
Test status
Simulation time	69570564 ps
CPU time	1.27 seconds
Started	Dec 20 12:36:54 PM PST 23
Finished	Dec 20 12:37:30 PM PST 23
Peak memory	229556 kb
Host	smart-1e52a0d5-6a07-449b-96b6-8c7b7d807383
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773447670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2773447670
Directory	/workspace/37.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2608627125
Short name	T104
Test name
Test status
Simulation time	38594288 ps
CPU time	1.32 seconds
Started	Dec 20 12:37:06 PM PST 23
Finished	Dec 20 12:37:50 PM PST 23
Peak memory	229620 kb
Host	smart-f78db9ba-e45f-4b6f-938a-c65033a4a8a6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608627125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2608627125
Directory	/workspace/39.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3249146536
Short name	T157
Test name
Test status
Simulation time	341105429 ps
CPU time	4.68 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:39 PM PST 23
Peak memory	229668 kb
Host	smart-7f1ce686-e863-4de4-b8d6-d89b4d1c9006
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249146536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia sing.3249146536
Directory	/workspace/4.otp_ctrl_csr_aliasing/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1820302760
Short name	T44
Test name
Test status
Simulation time	1495772203 ps
CPU time	10.33 seconds
Started	Dec 20 12:37:28 PM PST 23
Finished	Dec 20 12:38:51 PM PST 23
Peak memory	229416 kb
Host	smart-6bbc3fe3-7a8c-47c6-b00c-bb7f5603f918
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820302760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_ bash.1820302760
Directory	/workspace/4.otp_ctrl_csr_bit_bash/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4207539119
Short name	T81
Test name
Test status
Simulation time	1458203003 ps
CPU time	3.12 seconds
Started	Dec 20 12:37:19 PM PST 23
Finished	Dec 20 12:38:23 PM PST 23
Peak memory	229624 kb
Host	smart-2a57e7a9-b830-4fa8-a73a-023f83ba4dfb
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207539119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r eset.4207539119
Directory	/workspace/4.otp_ctrl_csr_hw_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.147301594
Short name	T73
Test name
Test status
Simulation time	144858900 ps
CPU time	1.98 seconds
Started	Dec 20 12:36:54 PM PST 23
Finished	Dec 20 12:37:32 PM PST 23
Peak memory	237776 kb
Host	smart-3550dd1b-e443-44dd-85a8-9000ac57d91d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147301594 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.147301594
Directory	/workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2024229788
Short name	T53
Test name
Test status
Simulation time	594087384 ps
CPU time	1.88 seconds
Started	Dec 20 12:37:00 PM PST 23
Finished	Dec 20 12:37:40 PM PST 23
Peak memory	229424 kb
Host	smart-d29a9cd4-b07f-41e3-bafc-5797b3525c57
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024229788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2024229788
Directory	/workspace/4.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1789641504
Short name	T113
Test name
Test status
Simulation time	39998523 ps
CPU time	1.33 seconds
Started	Dec 20 12:36:45 PM PST 23
Finished	Dec 20 12:37:14 PM PST 23
Peak memory	229388 kb
Host	smart-d1ba80c8-7ee2-4334-b0f6-004393783cc6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789641504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1789641504
Directory	/workspace/4.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2486859727
Short name	T37
Test name
Test status
Simulation time	64072535 ps
CPU time	1.3 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:27 PM PST 23
Peak memory	229128 kb
Host	smart-0955a32b-7ada-4af8-b511-b862c138ff33
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486859727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr l_mem_partial_access.2486859727
Directory	/workspace/4.otp_ctrl_mem_partial_access/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2724456284
Short name	T165
Test name
Test status
Simulation time	531519317 ps
CPU time	1.42 seconds
Started	Dec 20 12:36:56 PM PST 23
Finished	Dec 20 12:37:34 PM PST 23
Peak memory	229428 kb
Host	smart-48c7d924-11e3-4ef8-aa93-53c937689a35
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724456284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk .2724456284
Directory	/workspace/4.otp_ctrl_mem_walk/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.884019907
Short name	T169
Test name
Test status
Simulation time	68233789 ps
CPU time	2.02 seconds
Started	Dec 20 12:37:31 PM PST 23
Finished	Dec 20 12:38:47 PM PST 23
Peak memory	229696 kb
Host	smart-ea55eccf-3ad1-4608-9382-db6c60a9ddb4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884019907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct rl_same_csr_outstanding.884019907
Directory	/workspace/4.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3538317391
Short name	T110
Test name
Test status
Simulation time	340962927 ps
CPU time	5.48 seconds
Started	Dec 20 12:37:14 PM PST 23
Finished	Dec 20 12:38:10 PM PST 23
Peak memory	237924 kb
Host	smart-05e67e7b-9497-4061-8937-e50548d34df3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538317391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3538317391
Directory	/workspace/4.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3912183377
Short name	T90
Test name
Test status
Simulation time	1219358169 ps
CPU time	16.46 seconds
Started	Dec 20 12:36:31 PM PST 23
Finished	Dec 20 12:36:52 PM PST 23
Peak memory	237928 kb
Host	smart-ad88fd8e-d2ca-4d9f-ac20-d022d2ad6282
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912183377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in tg_err.3912183377
Directory	/workspace/4.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.2444726822
Short name	T32
Test name
Test status
Simulation time	40712438 ps
CPU time	1.32 seconds
Started	Dec 20 12:37:07 PM PST 23
Finished	Dec 20 12:37:48 PM PST 23
Peak memory	229276 kb
Host	smart-ea65f67a-1315-4d96-8240-4af92e36a055
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444726822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.2444726822
Directory	/workspace/40.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.509845061
Short name	T68
Test name
Test status
Simulation time	538424656 ps
CPU time	1.47 seconds
Started	Dec 20 12:37:22 PM PST 23
Finished	Dec 20 12:38:28 PM PST 23
Peak memory	229076 kb
Host	smart-8f6ec0dd-f8af-4225-b7f1-c4e3b68652e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509845061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.509845061
Directory	/workspace/41.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1390994269
Short name	T119
Test name
Test status
Simulation time	72175010 ps
CPU time	1.33 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:52 PM PST 23
Peak memory	229292 kb
Host	smart-f1da9517-d782-4ff8-b717-8a5494dfd087
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390994269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1390994269
Directory	/workspace/42.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1280847326
Short name	T101
Test name
Test status
Simulation time	615116298 ps
CPU time	1.53 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	229224 kb
Host	smart-d5eb0ad0-f023-4f93-ae1e-0b0ac8b981b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280847326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1280847326
Directory	/workspace/43.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2697992570
Short name	T132
Test name
Test status
Simulation time	567149766 ps
CPU time	1.92 seconds
Started	Dec 20 12:36:52 PM PST 23
Finished	Dec 20 12:37:29 PM PST 23
Peak memory	229296 kb
Host	smart-7c006753-4cbf-4100-8483-bda52301836e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697992570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2697992570
Directory	/workspace/44.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.966896777
Short name	T107
Test name
Test status
Simulation time	42584079 ps
CPU time	1.41 seconds
Started	Dec 20 12:37:20 PM PST 23
Finished	Dec 20 12:38:22 PM PST 23
Peak memory	229328 kb
Host	smart-c7f85f62-7aa6-4044-b877-bb195f9cb95b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966896777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.966896777
Directory	/workspace/45.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.3549409599
Short name	T9
Test name
Test status
Simulation time	81065146 ps
CPU time	1.25 seconds
Started	Dec 20 12:37:01 PM PST 23
Finished	Dec 20 12:37:41 PM PST 23
Peak memory	229116 kb
Host	smart-9b5a7df7-960b-4501-b754-1df9a09d7fca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549409599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3549409599
Directory	/workspace/46.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.311757273
Short name	T79
Test name
Test status
Simulation time	68294723 ps
CPU time	1.3 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	229288 kb
Host	smart-6cf2f31d-d6c8-4c54-a852-9f7432eebe2a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311757273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.311757273
Directory	/workspace/47.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2884497565
Short name	T7
Test name
Test status
Simulation time	37649708 ps
CPU time	1.36 seconds
Started	Dec 20 12:37:15 PM PST 23
Finished	Dec 20 12:38:11 PM PST 23
Peak memory	229492 kb
Host	smart-cb85a249-7ced-4384-bf53-f395688dfde9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884497565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2884497565
Directory	/workspace/48.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3089304489
Short name	T125
Test name
Test status
Simulation time	55252651 ps
CPU time	1.39 seconds
Started	Dec 20 12:37:17 PM PST 23
Finished	Dec 20 12:38:12 PM PST 23
Peak memory	229376 kb
Host	smart-b5f86d11-9e88-4ae0-8473-86d4eb00d35c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089304489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3089304489
Directory	/workspace/49.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2579350935
Short name	T66
Test name
Test status
Simulation time	66127585 ps
CPU time	2.09 seconds
Started	Dec 20 12:37:05 PM PST 23
Finished	Dec 20 12:37:47 PM PST 23
Peak memory	237732 kb
Host	smart-bf2b215e-046a-495f-a7fd-da34add6f838
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579350935 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2579350935
Directory	/workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.21799182
Short name	T62
Test name
Test status
Simulation time	163968708 ps
CPU time	1.6 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:35 PM PST 23
Peak memory	229396 kb
Host	smart-99bde50a-25e5-4125-9611-f324b9bb31cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21799182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.21799182
Directory	/workspace/5.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3800900741
Short name	T67
Test name
Test status
Simulation time	125256449 ps
CPU time	1.38 seconds
Started	Dec 20 12:37:30 PM PST 23
Finished	Dec 20 12:38:50 PM PST 23
Peak memory	229428 kb
Host	smart-5af11459-f07d-49e3-af93-1d21989925c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800900741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3800900741
Directory	/workspace/5.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.279192483
Short name	T42
Test name
Test status
Simulation time	83844676 ps
CPU time	2.41 seconds
Started	Dec 20 12:37:15 PM PST 23
Finished	Dec 20 12:38:12 PM PST 23
Peak memory	229700 kb
Host	smart-70e68629-c6c9-4922-8054-d9cc5069fae4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279192483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ct rl_same_csr_outstanding.279192483
Directory	/workspace/5.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2699006110
Short name	T89
Test name
Test status
Simulation time	1211086556 ps
CPU time	8.62 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:11 PM PST 23
Peak memory	229592 kb
Host	smart-999fcf13-1e41-410b-81eb-31baadd78b7c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699006110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in tg_err.2699006110
Directory	/workspace/5.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1732632286
Short name	T154
Test name
Test status
Simulation time	39252541 ps
CPU time	1.42 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	229612 kb
Host	smart-9eb8fc79-18b3-44b2-8f00-3e3508e48a1e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732632286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.1732632286
Directory	/workspace/6.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3860463143
Short name	T106
Test name
Test status
Simulation time	593102788 ps
CPU time	1.49 seconds
Started	Dec 20 12:37:27 PM PST 23
Finished	Dec 20 12:38:42 PM PST 23
Peak memory	229332 kb
Host	smart-9e44feaf-2ee2-419f-b7e8-1575efef94ec
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860463143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3860463143
Directory	/workspace/6.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3103596694
Short name	T168
Test name
Test status
Simulation time	194075736 ps
CPU time	2.13 seconds
Started	Dec 20 12:37:26 PM PST 23
Finished	Dec 20 12:38:41 PM PST 23
Peak memory	229224 kb
Host	smart-5388e24d-4adb-4d88-a5d7-1eabd2160091
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103596694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c trl_same_csr_outstanding.3103596694
Directory	/workspace/6.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2928497841
Short name	T17
Test name
Test status
Simulation time	112410188 ps
CPU time	3.7 seconds
Started	Dec 20 12:37:24 PM PST 23
Finished	Dec 20 12:38:40 PM PST 23
Peak memory	241760 kb
Host	smart-126bc0ff-a4e8-4552-becb-9648a6394b75
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928497841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2928497841
Directory	/workspace/6.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1320948584
Short name	T85
Test name
Test status
Simulation time	4595090270 ps
CPU time	19.32 seconds
Started	Dec 20 12:37:13 PM PST 23
Finished	Dec 20 12:38:21 PM PST 23
Peak memory	229812 kb
Host	smart-61c54c22-b158-4ef3-81c0-ac44c8b4213a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320948584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in tg_err.1320948584
Directory	/workspace/6.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1684221723
Short name	T149
Test name
Test status
Simulation time	126216178 ps
CPU time	2.44 seconds
Started	Dec 20 12:37:20 PM PST 23
Finished	Dec 20 12:38:25 PM PST 23
Peak memory	237724 kb
Host	smart-19483f76-4928-4db7-8d7e-aedca609ca7c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684221723 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1684221723
Directory	/workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.127516463
Short name	T64
Test name
Test status
Simulation time	41700239 ps
CPU time	1.48 seconds
Started	Dec 20 12:36:51 PM PST 23
Finished	Dec 20 12:37:26 PM PST 23
Peak memory	229544 kb
Host	smart-5f42b3d5-71b3-4038-8dea-1232b60304df
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127516463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.127516463
Directory	/workspace/7.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.717873891
Short name	T124
Test name
Test status
Simulation time	73350634 ps
CPU time	1.27 seconds
Started	Dec 20 12:36:59 PM PST 23
Finished	Dec 20 12:37:37 PM PST 23
Peak memory	229272 kb
Host	smart-f258b6fd-43c4-4426-a47f-b4bc64b866b7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717873891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.717873891
Directory	/workspace/7.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1033005767
Short name	T28
Test name
Test status
Simulation time	116232824 ps
CPU time	2.75 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:54 PM PST 23
Peak memory	229660 kb
Host	smart-6435daf6-f824-4144-bdbb-7cdc363c4085
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033005767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c trl_same_csr_outstanding.1033005767
Directory	/workspace/7.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3455022623
Short name	T145
Test name
Test status
Simulation time	852338996 ps
CPU time	3.98 seconds
Started	Dec 20 12:37:08 PM PST 23
Finished	Dec 20 12:37:53 PM PST 23
Peak memory	237828 kb
Host	smart-9b85abaf-1e8f-458b-ba80-244f41fc8c7f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455022623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3455022623
Directory	/workspace/7.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.1199997648
Short name	T156
Test name
Test status
Simulation time	1034587980 ps
CPU time	11.15 seconds
Started	Dec 20 12:37:04 PM PST 23
Finished	Dec 20 12:37:56 PM PST 23
Peak memory	229628 kb
Host	smart-23f81291-83ee-4b80-9c68-37687787c70a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199997648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in tg_err.1199997648
Directory	/workspace/7.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.4131040861
Short name	T139
Test name
Test status
Simulation time	74226429 ps
CPU time	2.28 seconds
Started	Dec 20 12:37:18 PM PST 23
Finished	Dec 20 12:38:18 PM PST 23
Peak memory	237688 kb
Host	smart-6b42cfb5-c5e8-43e1-8e62-2d62f838d7cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131040861 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.4131040861
Directory	/workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2210277873
Short name	T52
Test name
Test status
Simulation time	70750241 ps
CPU time	1.48 seconds
Started	Dec 20 12:37:12 PM PST 23
Finished	Dec 20 12:38:04 PM PST 23
Peak memory	229496 kb
Host	smart-f0ca0da3-3a1b-417d-afdf-955adb3552f8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210277873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2210277873
Directory	/workspace/8.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.968934181
Short name	T102
Test name
Test status
Simulation time	74570832 ps
CPU time	1.39 seconds
Started	Dec 20 12:37:21 PM PST 23
Finished	Dec 20 12:38:27 PM PST 23
Peak memory	229316 kb
Host	smart-c122c59f-775f-47e7-9635-5cf47a8e6b4d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968934181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.968934181
Directory	/workspace/8.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2171464453
Short name	T140
Test name
Test status
Simulation time	246883980 ps
CPU time	2.13 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:55 PM PST 23
Peak memory	229492 kb
Host	smart-48a678a7-d6f9-43af-bf98-b4694892f1c7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171464453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c trl_same_csr_outstanding.2171464453
Directory	/workspace/8.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.484494015
Short name	T19
Test name
Test status
Simulation time	3066313948 ps
CPU time	8.04 seconds
Started	Dec 20 12:37:34 PM PST 23
Finished	Dec 20 12:39:08 PM PST 23
Peak memory	237836 kb
Host	smart-3e21ee09-dab3-4eec-a5cb-c1c1dbb85263
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484494015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.484494015
Directory	/workspace/8.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.597105160
Short name	T11
Test name
Test status
Simulation time	2256683413 ps
CPU time	15.59 seconds
Started	Dec 20 12:37:10 PM PST 23
Finished	Dec 20 12:38:09 PM PST 23
Peak memory	230048 kb
Host	smart-1795827b-0225-425d-83b1-3f0b5bcee449
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597105160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_int g_err.597105160
Directory	/workspace/8.otp_ctrl_tl_intg_err/latest

---

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3537091611
Short name	T75
Test name
Test status
Simulation time	99453415 ps
CPU time	2.65 seconds
Started	Dec 20 12:36:57 PM PST 23
Finished	Dec 20 12:37:36 PM PST 23
Peak memory	237900 kb
Host	smart-2f5852ab-dac8-4686-a9ee-33e44b33876f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537091611 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.3537091611
Directory	/workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

---

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2883010567
Short name	T167
Test name
Test status
Simulation time	39724572 ps
CPU time	1.63 seconds
Started	Dec 20 12:36:55 PM PST 23
Finished	Dec 20 12:37:32 PM PST 23
Peak memory	229556 kb
Host	smart-c8656fa9-0a1f-482b-9db0-f3c5bdbafd5a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883010567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2883010567
Directory	/workspace/9.otp_ctrl_csr_rw/latest

---

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1017398277
Short name	T108
Test name
Test status
Simulation time	40171015 ps
CPU time	1.37 seconds
Started	Dec 20 12:36:27 PM PST 23
Finished	Dec 20 12:36:29 PM PST 23
Peak memory	229480 kb
Host	smart-2f6b04a5-d0a9-4b91-b7d8-79943c1cded4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017398277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1017398277
Directory	/workspace/9.otp_ctrl_intr_test/latest

---

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1364611387
Short name	T158
Test name
Test status
Simulation time	170332904 ps
CPU time	1.88 seconds
Started	Dec 20 12:37:02 PM PST 23
Finished	Dec 20 12:37:42 PM PST 23
Peak memory	229484 kb
Host	smart-e2eea693-0f9b-4a80-8e4f-64496eab915c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364611387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c trl_same_csr_outstanding.1364611387
Directory	/workspace/9.otp_ctrl_same_csr_outstanding/latest

---

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.348662232
Short name	T147
Test name
Test status
Simulation time	99069852 ps
CPU time	2.82 seconds
Started	Dec 20 12:37:09 PM PST 23
Finished	Dec 20 12:37:54 PM PST 23
Peak memory	237872 kb
Host	smart-2813705a-bbef-41cd-9b4f-d4f7f5159e82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348662232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.348662232
Directory	/workspace/9.otp_ctrl_tl_errors/latest

---

Test location	/workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4025885571
Short name	T87
Test name
Test status
Simulation time	1275197515 ps
CPU time	15.45 seconds
Started	Dec 20 12:36:31 PM PST 23
Finished	Dec 20 12:36:59 PM PST 23
Peak memory	229820 kb
Host	smart-677b0952-3eef-45a9-bc41-018e7d2cc563
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025885571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in tg_err.4025885571
Directory	/workspace/9.otp_ctrl_tl_intg_err/latest