Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_err_code_cg_wrap::unbuf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
85.71	80.95	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]	71.43	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]	85.71	1	100	1	64	64
unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	85.71	1	100	1	64	64

---

Group Instance : unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	2	5	71.43

Variables for Group Instance unbuf_err_code_cg_wrap[OtpVendorTestErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	2	5	71.43	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpCreatorSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

---

Group Instance : unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

---

Summary for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	1	6	85.71

Variables for Group Instance unbuf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	2	5	71.43

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
ecc_uncorr_err	0	1	1
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	111857	1			T2	51		T3	89		T8	337
check_fail	13	1			T128	1		T129	1		T130	1
access_err	67953	1			T5	107		T6	338		T75	24
ecc_corr_err	1378	1			T89	31		T54	74		T107	2
no_err	390440	1			T1	22		T2	53		T3	91

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	111280	1			T2	51		T3	89		T8	337
check_fail	14	1			T128	1		T133	1		T134	1
access_err	66685	1			T1	6		T5	63		T6	201
ecc_uncorr_err	573	1			T9	1		T107	5		T131	1
ecc_corr_err	1272	1			T89	56		T54	26		T107	25
no_err	391814	1			T1	16		T2	53		T3	91

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	111285	1			T2	51		T3	89		T9	1
check_fail	18	1			T128	1		T133	1		T134	1
access_err	66993	1			T8	2		T4	6		T5	108
ecc_uncorr_err	565	1			T124	59		T135	1		T119	47
ecc_corr_err	1243	1			T89	64		T54	51		T107	22
no_err	391535	1			T1	22		T2	53		T3	91