Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8769301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15854489

1

T21

1

T108

303

T109

297

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7665982	1			T21	1		T108	556		T109	534
values[0x0]	6468999	1			T108	13		T109	13		T110	263
values[0x1]	10488809	1			T108	16		T109	16		T110	313

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4589382	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

20034408

1

T21

1

T108

355

T109

349

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	95623	1			T204	4		T188	2		T180	2
valid_sources[0x01]	96104	1			T108	5		T204	4		T188	5
valid_sources[0x02]	94008	1			T108	2		T109	16		T114	8
valid_sources[0x03]	96210	1			T108	2		T114	2		T204	5
valid_sources[0x04]	92267	1			T108	2		T114	5		T204	8
valid_sources[0x05]	93896	1			T114	11		T204	3		T188	2
valid_sources[0x06]	95356	1			T108	1		T204	4		T205	5
valid_sources[0x07]	97219	1			T108	1		T112	1		T176	2
valid_sources[0x08]	95590	1			T108	4		T109	7		T204	6
valid_sources[0x09]	93515	1			T108	1		T114	2		T176	2
valid_sources[0x0a]	91840	1			T108	2		T204	3		T205	5
valid_sources[0x0b]	96465	1			T108	2		T114	4		T176	12
valid_sources[0x0c]	101571	1			T108	1		T114	5		T176	11
valid_sources[0x0d]	94485	1			T108	4		T114	4		T204	2
valid_sources[0x0e]	98129	1			T108	4		T204	1		T188	4
valid_sources[0x0f]	110034	1			T108	4		T109	7		T112	1
valid_sources[0x10]	99996	1			T108	5		T204	2		T188	1
valid_sources[0x11]	91671	1			T108	1		T112	2		T204	4
valid_sources[0x12]	92054	1			T108	3		T114	2		T204	2
valid_sources[0x13]	98884	1			T108	6		T109	34		T114	12
valid_sources[0x14]	93625	1			T108	1		T114	4		T176	8
valid_sources[0x15]	102534	1			T108	6		T176	1		T204	3
valid_sources[0x16]	96428	1			T108	3		T109	1		T114	4
valid_sources[0x17]	95214	1			T108	5		T114	4		T204	3
valid_sources[0x18]	94867	1			T108	1		T114	2		T176	2
valid_sources[0x19]	98961	1			T108	4		T114	5		T204	2
valid_sources[0x1a]	96710	1			T108	2		T109	16		T188	1
valid_sources[0x1b]	92806	1			T108	4		T204	3		T188	2
valid_sources[0x1c]	94664	1			T108	2		T114	5		T204	2
valid_sources[0x1d]	98284	1			T108	1		T109	7		T112	5
valid_sources[0x1e]	93297	1			T114	9		T204	1		T188	4
valid_sources[0x1f]	99138	1			T108	1		T114	1		T204	6
valid_sources[0x20]	93844	1			T108	3		T204	1		T205	10
valid_sources[0x21]	98188	1			T108	3		T114	3		T204	5
valid_sources[0x22]	94853	1			T108	3		T114	1		T204	3
valid_sources[0x23]	98174	1			T108	2		T114	1		T175	1
valid_sources[0x24]	95990	1			T114	3		T112	2		T204	3
valid_sources[0x25]	94855	1			T108	2		T114	2		T204	6
valid_sources[0x26]	91610	1			T108	9		T204	5		T188	2
valid_sources[0x27]	95292	1			T108	2		T114	3		T204	2
valid_sources[0x28]	93815	1			T108	4		T109	22		T114	1
valid_sources[0x29]	99835	1			T109	11		T114	7		T204	2
valid_sources[0x2a]	91814	1			T108	1		T114	2		T204	4
valid_sources[0x2b]	96680	1			T108	1		T114	5		T204	4
valid_sources[0x2c]	95079	1			T108	6		T114	4		T175	1
valid_sources[0x2d]	93791	1			T108	4		T114	8		T204	2
valid_sources[0x2e]	92598	1			T108	1		T114	4		T204	5
valid_sources[0x2f]	91814	1			T108	1		T114	13		T204	6
valid_sources[0x30]	94812	1			T108	3		T114	5		T204	2
valid_sources[0x31]	96390	1			T108	1		T114	7		T204	7
valid_sources[0x32]	93033	1			T108	2		T109	7		T114	1
valid_sources[0x33]	93379	1			T108	3		T204	2		T188	3
valid_sources[0x34]	98231	1			T108	5		T204	7		T188	2
valid_sources[0x35]	108205	1			T108	1		T114	2		T204	1
valid_sources[0x36]	92659	1			T114	5		T176	7		T204	2
valid_sources[0x37]	91874	1			T108	2		T114	1		T204	1
valid_sources[0x38]	93685	1			T176	10		T204	4		T188	1
valid_sources[0x39]	97778	1			T175	2		T204	6		T205	18
valid_sources[0x3a]	96423	1			T114	8		T176	7		T204	2
valid_sources[0x3b]	96069	1			T108	4		T204	4		T189	1
valid_sources[0x3c]	92779	1			T108	1		T112	1		T176	5
valid_sources[0x3d]	95372	1			T108	1		T114	6		T204	6
valid_sources[0x3e]	99751	1			T114	6		T204	1		T178	1
valid_sources[0x3f]	93397	1			T109	2		T176	4		T204	1
valid_sources[0x40]	92063	1			T108	1		T114	6		T204	3
valid_sources[0x41]	106126	1			T108	2		T176	6		T204	1
valid_sources[0x42]	92165	1			T108	7		T204	4		T188	1
valid_sources[0x43]	93801	1			T108	2		T114	3		T204	7
valid_sources[0x44]	99880	1			T108	1		T114	7		T175	1
valid_sources[0x45]	95723	1			T108	2		T109	10		T114	4
valid_sources[0x46]	93186	1			T108	6		T204	1		T180	1
valid_sources[0x47]	94261	1			T108	3		T204	2		T188	2
valid_sources[0x48]	94873	1			T108	3		T204	1		T187	1
valid_sources[0x49]	95714	1			T109	22		T204	3		T188	2
valid_sources[0x4a]	96206	1			T108	2		T114	1		T176	2
valid_sources[0x4b]	92575	1			T108	1		T109	15		T114	6
valid_sources[0x4c]	93831	1			T108	2		T114	11		T204	4
valid_sources[0x4d]	100010	1			T108	3		T175	1		T204	6
valid_sources[0x4e]	96945	1			T108	1		T114	2		T204	1
valid_sources[0x4f]	97088	1			T108	1		T114	3		T112	1
valid_sources[0x50]	93426	1			T108	1		T114	4		T176	9
valid_sources[0x51]	101518	1			T108	2		T175	3		T204	3
valid_sources[0x52]	93413	1			T108	2		T114	2		T204	1
valid_sources[0x53]	97012	1			T108	2		T176	6		T204	1
valid_sources[0x54]	90787	1			T114	9		T204	2		T187	1
valid_sources[0x55]	95697	1			T204	2		T188	2		T180	1
valid_sources[0x56]	96533	1			T114	7		T204	4		T205	16
valid_sources[0x57]	92689	1			T108	2		T109	7		T175	1
valid_sources[0x58]	91810	1			T108	4		T114	5		T175	2
valid_sources[0x59]	94621	1			T108	3		T114	8		T176	12
valid_sources[0x5a]	104923	1			T108	1		T109	6		T114	1
valid_sources[0x5b]	94137	1			T109	27		T114	5		T204	3
valid_sources[0x5c]	94144	1			T108	1		T109	3		T114	2
valid_sources[0x5d]	97923	1			T114	6		T204	1		T188	1
valid_sources[0x5e]	120841	1			T108	1		T114	1		T204	3
valid_sources[0x5f]	93103	1			T108	3		T204	4		T205	10
valid_sources[0x60]	90677	1			T108	7		T109	13		T114	5
valid_sources[0x61]	95924	1			T108	2		T114	7		T176	5
valid_sources[0x62]	93631	1			T108	4		T114	1		T204	5
valid_sources[0x63]	93991	1			T108	4		T114	2		T204	4
valid_sources[0x64]	94382	1			T108	2		T204	2		T180	3
valid_sources[0x65]	91806	1			T108	2		T114	3		T204	1
valid_sources[0x66]	95912	1			T108	3		T114	1		T112	1
valid_sources[0x67]	99653	1			T108	2		T114	5		T204	2
valid_sources[0x68]	92838	1			T108	2		T114	6		T175	3
valid_sources[0x69]	111360	1			T108	4		T204	6		T180	1
valid_sources[0x6a]	92650	1			T108	1		T109	7		T176	7
valid_sources[0x6b]	98513	1			T108	2		T114	2		T175	1
valid_sources[0x6c]	95221	1			T108	3		T114	16		T204	2
valid_sources[0x6d]	98780	1			T108	3		T109	5		T112	2
valid_sources[0x6e]	96400	1			T108	1		T204	4		T188	2
valid_sources[0x6f]	95351	1			T108	1		T114	14		T112	2
valid_sources[0x70]	91038	1			T108	1		T114	5		T111	40
valid_sources[0x71]	100031	1			T108	1		T204	3		T113	1
valid_sources[0x72]	97748	1			T114	4		T176	1		T204	6
valid_sources[0x73]	103662	1			T108	5		T204	5		T178	3
valid_sources[0x74]	93720	1			T108	2		T204	3		T188	1
valid_sources[0x75]	96940	1			T108	2		T114	2		T204	1
valid_sources[0x76]	91167	1			T108	3		T114	4		T204	3
valid_sources[0x77]	96197	1			T109	21		T114	6		T176	5
valid_sources[0x78]	96036	1			T108	2		T204	1		T205	7
valid_sources[0x79]	106783	1			T114	5		T204	4		T188	1
valid_sources[0x7a]	102818	1			T108	1		T114	4		T176	13
valid_sources[0x7b]	91901	1			T108	1		T114	5		T176	13
valid_sources[0x7c]	97985	1			T188	1		T229	1		T228	4
valid_sources[0x7d]	99531	1			T108	3		T114	2		T204	3
valid_sources[0x7e]	95993	1			T108	1		T114	1		T204	2
valid_sources[0x7f]	91759	1			T108	2		T176	1		T178	1
valid_sources[0x80]	93660	1			T108	3		T109	32		T204	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4368981

1

T21

1

T108

277

T109

274

values[0x0]

all_enables

biggest_size

5784651

1

T108

12

T109

11

T110

163

values[0x1]

all_enables

biggest_size

5700857

1

T108

14

T109

12

T110

174

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	803364	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29462087

1

T108

153

T109

136

T110

612

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7420545	1			T108	296		T109	272		T110	512
values[0x0]	11085455	1			T108	4		T109	2		T110	266
values[0x1]	11759451	1			T108	4		T109	6		T110	246

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	276361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29989090

1

T108

186

T109

164

T110

699

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	117446	1			T114	4		T204	4		T205	8
valid_sources[0x01]	119160	1			T109	3		T114	3		T177	1
valid_sources[0x02]	116338	1			T109	2		T114	4		T115	2
valid_sources[0x03]	117342	1			T108	2		T109	2		T114	5
valid_sources[0x04]	120037	1			T108	1		T110	66		T114	4
valid_sources[0x05]	123431	1			T108	3		T114	3		T204	1
valid_sources[0x06]	117861	1			T114	1		T178	4		T228	3
valid_sources[0x07]	117488	1			T114	5		T205	4		T188	1
valid_sources[0x08]	116306	1			T108	6		T114	2		T205	3
valid_sources[0x09]	118907	1			T108	1		T114	6		T188	4
valid_sources[0x0a]	118550	1			T109	8		T114	5		T204	2
valid_sources[0x0b]	117679	1			T108	3		T114	3		T178	4
valid_sources[0x0c]	117847	1			T114	3		T176	21		T204	1
valid_sources[0x0d]	116693	1			T114	4		T205	1		T183	1
valid_sources[0x0e]	117941	1			T108	5		T114	6		T204	4
valid_sources[0x0f]	117824	1			T108	1		T109	12		T114	1
valid_sources[0x10]	124766	1			T114	1		T191	1		T228	1
valid_sources[0x11]	125961	1			T108	1		T114	3		T178	3
valid_sources[0x12]	119719	1			T110	3		T177	6		T188	2
valid_sources[0x13]	115331	1			T114	1		T178	2		T188	2
valid_sources[0x14]	121712	1			T114	3		T176	6		T188	1
valid_sources[0x15]	118851	1			T108	1		T114	3		T178	1
valid_sources[0x16]	111335	1			T108	1		T109	5		T114	3
valid_sources[0x17]	109497	1			T114	3		T204	12		T205	6
valid_sources[0x18]	115957	1			T108	2		T114	4		T188	2
valid_sources[0x19]	111640	1			T108	3		T110	29		T205	1
valid_sources[0x1a]	117576	1			T114	3		T178	1		T228	6
valid_sources[0x1b]	118345	1			T109	1		T114	1		T204	13
valid_sources[0x1c]	120737	1			T114	3		T180	1		T228	7
valid_sources[0x1d]	116238	1			T114	1		T177	2		T178	7
valid_sources[0x1e]	117639	1			T114	6		T204	14		T177	3
valid_sources[0x1f]	120698	1			T108	3		T114	1		T178	4
valid_sources[0x20]	116704	1			T114	3		T205	7		T228	2
valid_sources[0x21]	116750	1			T108	1		T114	1		T175	18
valid_sources[0x22]	120401	1			T108	3		T114	1		T204	17
valid_sources[0x23]	122215	1			T114	3		T205	2		T177	2
valid_sources[0x24]	112586	1			T177	3		T188	1		T180	1
valid_sources[0x25]	120994	1			T108	1		T109	3		T114	2
valid_sources[0x26]	121991	1			T108	3		T110	63		T204	2
valid_sources[0x27]	120650	1			T114	5		T205	11		T178	10
valid_sources[0x28]	123224	1			T108	2		T114	5		T204	2
valid_sources[0x29]	117970	1			T109	8		T114	2		T205	12
valid_sources[0x2a]	118032	1			T114	2		T205	1		T188	1
valid_sources[0x2b]	116725	1			T114	5		T175	19		T204	11
valid_sources[0x2c]	125051	1			T108	2		T114	6		T204	4
valid_sources[0x2d]	114173	1			T204	1		T188	1		T228	4
valid_sources[0x2e]	115053	1			T114	3		T177	6		T228	1
valid_sources[0x2f]	115718	1			T108	1		T205	3		T188	3
valid_sources[0x30]	112930	1			T109	5		T114	4		T204	1
valid_sources[0x31]	113228	1			T108	7		T114	2		T204	16
valid_sources[0x32]	118522	1			T108	1		T114	1		T178	4
valid_sources[0x33]	120724	1			T108	1		T110	75		T114	3
valid_sources[0x34]	116540	1			T108	1		T114	4		T205	26
valid_sources[0x35]	114271	1			T114	2		T204	22		T205	7
valid_sources[0x36]	119313	1			T114	3		T205	4		T178	2
valid_sources[0x37]	119701	1			T108	2		T228	2		T231	3
valid_sources[0x38]	122084	1			T204	9		T205	11		T180	1
valid_sources[0x39]	116629	1			T108	1		T114	1		T188	1
valid_sources[0x3a]	116540	1			T114	2		T188	1		T180	1
valid_sources[0x3b]	117346	1			T114	9		T205	1		T178	1
valid_sources[0x3c]	115277	1			T108	1		T205	3		T178	1
valid_sources[0x3d]	119075	1			T114	4		T228	1		T235	1
valid_sources[0x3e]	117773	1			T108	2		T109	5		T114	4
valid_sources[0x3f]	116302	1			T114	3		T177	1		T188	3
valid_sources[0x40]	115126	1			T108	1		T114	4		T204	1
valid_sources[0x41]	118060	1			T114	4		T205	21		T178	2
valid_sources[0x42]	118990	1			T114	4		T176	11		T178	2
valid_sources[0x43]	120946	1			T108	2		T114	1		T204	2
valid_sources[0x44]	120421	1			T108	1		T114	3		T177	2
valid_sources[0x45]	116516	1			T114	1		T178	5		T180	2
valid_sources[0x46]	123053	1			T108	2		T114	1		T229	13
valid_sources[0x47]	120443	1			T114	2		T204	1		T205	32
valid_sources[0x48]	118454	1			T108	2		T109	2		T204	2
valid_sources[0x49]	118155	1			T114	1		T178	4		T188	1
valid_sources[0x4a]	122594	1			T108	2		T114	5		T178	1
valid_sources[0x4b]	122749	1			T114	1		T178	2		T191	1
valid_sources[0x4c]	112191	1			T108	6		T114	4		T205	2
valid_sources[0x4d]	118511	1			T114	5		T176	34		T205	6
valid_sources[0x4e]	115411	1			T114	2		T231	3		T235	1
valid_sources[0x4f]	118052	1			T114	5		T204	10		T180	1
valid_sources[0x50]	116613	1			T109	16		T114	2		T204	4
valid_sources[0x51]	119428	1			T114	3		T177	1		T188	3
valid_sources[0x52]	120871	1			T114	1		T177	2		T178	16
valid_sources[0x53]	117326	1			T108	2		T114	1		T204	17
valid_sources[0x54]	125175	1			T114	1		T204	3		T178	1
valid_sources[0x55]	115073	1			T108	2		T109	11		T114	1
valid_sources[0x56]	117707	1			T205	4		T178	11		T188	1
valid_sources[0x57]	112041	1			T108	4		T114	3		T204	11
valid_sources[0x58]	115118	1			T108	2		T114	1		T205	6
valid_sources[0x59]	117159	1			T108	2		T109	11		T204	1
valid_sources[0x5a]	115560	1			T108	6		T114	1		T204	1
valid_sources[0x5b]	112182	1			T114	4		T188	1		T228	2
valid_sources[0x5c]	117703	1			T114	4		T178	20		T180	2
valid_sources[0x5d]	121892	1			T108	6		T114	1		T177	1
valid_sources[0x5e]	116411	1			T108	2		T114	4		T177	1
valid_sources[0x5f]	121115	1			T108	4		T114	3		T177	3
valid_sources[0x60]	123301	1			T108	1		T114	6		T204	1
valid_sources[0x61]	115753	1			T114	2		T204	8		T178	3
valid_sources[0x62]	119409	1			T108	2		T114	1		T205	2
valid_sources[0x63]	118769	1			T114	4		T177	5		T188	1
valid_sources[0x64]	116026	1			T204	11		T177	3		T178	1
valid_sources[0x65]	117743	1			T108	2		T114	1		T182	1
valid_sources[0x66]	117403	1			T108	1		T114	1		T115	1
valid_sources[0x67]	118268	1			T108	1		T114	2		T205	4
valid_sources[0x68]	115995	1			T109	1		T114	2		T204	28
valid_sources[0x69]	115815	1			T108	1		T114	2		T178	12
valid_sources[0x6a]	120179	1			T108	9		T114	4		T115	2
valid_sources[0x6b]	121808	1			T108	2		T205	1		T177	1
valid_sources[0x6c]	120229	1			T108	2		T114	2		T204	1
valid_sources[0x6d]	123463	1			T108	2		T109	2		T114	4
valid_sources[0x6e]	117613	1			T114	1		T204	5		T188	1
valid_sources[0x6f]	122541	1			T108	3		T109	4		T114	3
valid_sources[0x70]	119583	1			T114	1		T188	2		T180	3
valid_sources[0x71]	119427	1			T176	8		T228	1		T182	6
valid_sources[0x72]	121110	1			T108	1		T114	1		T176	6
valid_sources[0x73]	121484	1			T110	91		T114	2		T204	1
valid_sources[0x74]	120039	1			T114	3		T176	3		T178	6
valid_sources[0x75]	118080	1			T108	2		T109	7		T114	4
valid_sources[0x76]	119326	1			T110	15		T114	1		T178	8
valid_sources[0x77]	120792	1			T114	1		T178	9		T188	2
valid_sources[0x78]	112656	1			T108	4		T114	2		T204	4
valid_sources[0x79]	117067	1			T108	3		T114	1		T204	14
valid_sources[0x7a]	119565	1			T108	1		T109	3		T114	1
valid_sources[0x7b]	125521	1			T114	2		T204	10		T205	8
valid_sources[0x7c]	115579	1			T114	4		T188	1		T180	1
valid_sources[0x7d]	119283	1			T109	3		T114	2		T177	1
valid_sources[0x7e]	118861	1			T108	2		T114	1		T178	4
valid_sources[0x7f]	114043	1			T108	2		T114	3		T188	1
valid_sources[0x80]	122330	1			T114	3		T177	3		T188	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7406900

1

T108

148

T109

130

T110

241

values[0x0]

all_enables

biggest_size

11029854

1

T108

3

T109

2

T110

217

values[0x1]

all_enables

biggest_size

11025333

1

T108

2

T109

4

T110

154