Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

65443865

1

T108

282

T109

266

T110

534

full_word

19547797

1

T21

1

T108

303

T109

297

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84991332	1			T21	1		T108	585		T109	563
auto[TlIntgErrCmd]	97	1			T114	5		T204	6		T205	4
auto[TlIntgErrData]	114	1			T114	8		T204	3		T205	6
auto[TlIntgErrBoth]	119	1			T114	7		T204	11		T205	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12094447

1

T21

1

T108

556

T109

534

auto[1]

72897215

1

T108

29

T109

29

T110

576

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7275947	1			T108	279		T109	260		T110	295
auto[TlIntgErrNone]	partial	auto[1]	58167606	1			T108	3		T109	6		T110	239
auto[TlIntgErrNone]	full_word	auto[0]	4818365	1			T21	1		T108	277		T109	274
auto[TlIntgErrNone]	full_word	auto[1]	14729414	1			T108	26		T109	23		T110	337
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T114	1		T204	3		T205	1
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T114	4		T204	3		T205	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T309	2		T310	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T231	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	53	1			T114	2		T204	1		T205	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T114	6		T204	2		T205	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T308	1		T311	1		T312	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T228	1		T261	1		T311	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T114	4		T204	4		T205	4
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T114	3		T204	7		T205	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T309	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T308	1		T307	1		T313	1