Unified Coverage Report :: Module :: prim_packer_fifo

Module : prim_packer_fifo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
73.33	100.00	93.33			100.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_edn_req.u_prim_packer_fifo	74.14	100.00	96.55			100.00	0.00

---

Module Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.14	100.00	96.55			100.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
74.14	100.00	96.55			100.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_prim_edn_req

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_packer_fifo

	Line No.	Total	Covered	Percent
TOTAL		17	17	100.00
ALWAYS	81	7	7	100.00
CONT_ASSIGN	93	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	116	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1
88	1	1
93		unreachable
95	1	1
100	1	1
101	1	1
102	1	1
103	1	1
105	1	1
109	1	1
114	1	1
115	1	1
116	1	1

---

Cond Coverage for Module : prim_packer_fifo

	Total	Covered	Percent
Conditions	30	28	93.33
Logical	30	28	93.33
Non-Logical	0	0
Event	0	0

 LINE       101
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       101
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       102
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       103
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       105
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + 1)) : depth_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (load_data ? ((depth_q + 1)) : depth_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       109
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       114
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       114
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       116
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       116
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	105	3	3	100.00
TERNARY	109	3	3	100.00
IF	81	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	105	(clear_status) ? 
-2-:	105	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(clear_data) ? 
-2-:	109	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_packer_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	0	0.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	0	0.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	2147483647	0	0	1158
ValidOPairedWithReadyI_A	2147483647	0	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	1158

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

Line Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

	Line No.	Total	Covered	Percent
TOTAL		17	17	100.00
ALWAYS	81	7	7	100.00
CONT_ASSIGN	93	0	0
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	116	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
81	1	1
82	1	1
83	1	1
84	1	1
86	1	1
87	1	1
88	1	1
93		unreachable
95	1	1
100	1	1
101	1	1
102	1	1
103	1	1
105	1	1
109	1	1
114	1	1
115	1	1
116	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

	Total	Covered	Percent
Conditions	29	28	96.55
Logical	29	28	96.55
Non-Logical	0	0
Event	0	0

 LINE       101
 EXPRESSION ((rready_i && rvalid_o) || clr_q)
             -----------1----------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6

 LINE       101
 SUB-EXPRESSION (rready_i && rvalid_o)
                 ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       102
 EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
             ---------------1---------------    --2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       103
 EXPRESSION (wvalid_i && wready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       105
 EXPRESSION (clear_status ? '0 : (load_data ? ((depth_q + 1)) : depth_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       105
 SUB-EXPRESSION (load_data ? ((depth_q + 1)) : depth_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       109
 EXPRESSION (clear_data ? '0 : (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       109
 SUB-EXPRESSION (load_data ? ((gen_pack_mode.wdata_shifted | ((depth_q == 2'b0) ? '0 : data_q))) : data_q)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       114
 EXPRESSION (( ! (depth_q == FullDepth) ) && ((!clr_q)))
             --------------1-------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION ( ! (depth_q == FullDepth) )
                    -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       114
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       116
 EXPRESSION ((depth_q == FullDepth) && ((!clr_q)))
             -----------1----------    -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T4,T5,T6

 LINE       116
 SUB-EXPRESSION (depth_q == FullDepth)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	105	3	3	100.00
TERNARY	109	3	3	100.00
IF	81	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	105	(clear_status) ? 
-2-:	105	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	109	(clear_data) ? 
-2-:	109	(load_data) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_edn_req.u_prim_packer_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	0	0.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	0	0.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataOStableWhenPending_A	2147483647	0	0	1158
ValidOPairedWithReadyI_A	2147483647	0	0	0

DataOStableWhenPending_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	1158

ValidOPairedWithReadyI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0