Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	20902283	0	0
check_regwen_rd_A	2147483647	5445	0	0
check_timeout_rd_A	2147483647	3935	0	0
check_trigger_regwen_rd_A	2147483647	5125	0	0
consistency_check_period_rd_A	2147483647	5478	0	0
creator_sw_cfg_read_lock_rd_A	2147483647	4191	0	0
direct_access_address_rd_A	2147483647	3329	0	0
direct_access_wdata_0_rd_A	2147483647	2298	0	0
direct_access_wdata_1_rd_A	2147483647	2574	0	0
integrity_check_period_rd_A	2147483647	5281	0	0
intr_enable_rd_A	2147483647	5806	0	0
owner_sw_cfg_read_lock_rd_A	2147483647	3576	0	0
vendor_test_read_lock_rd_A	2147483647	3809	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20902283	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T113	4222	0	0	0
T114	129593	6	0	0
T115	3454	0	0	0
T175	3782	0	0	0
T176	13153	0	0	0
T177	10077	246	0	0
T178	0	162	0	0
T179	0	205	0	0
T180	0	45	0	0
T181	0	4	0	0
T182	0	67	0	0
T204	133122	5	0	0
T205	124111	6	0	0
T228	0	4	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5445	0	0
T108	7854	122	0	0
T109	8069	83	0	0
T110	26584	219	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	62	0	0
T115	3454	0	0	0
T175	3782	0	0	0
T176	13153	29	0	0
T191	0	8	0	0
T204	133122	0	0	0
T229	0	27	0	0
T231	0	38	0	0
T236	0	115	0	0
T261	0	55	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3935	0	0
T14	0	27	0	0
T19	0	164	0	0
T108	7854	154	0	0
T109	8069	49	0	0
T110	26584	0	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	0	0	0
T115	3454	0	0	0
T117	0	9	0	0
T175	3782	0	0	0
T176	13153	89	0	0
T204	133122	0	0	0
T229	0	41	0	0
T236	0	82	0	0
T262	0	6	0	0
T263	0	40	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5125	0	0
T108	7854	126	0	0
T109	8069	78	0	0
T110	26584	231	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	86	0	0
T115	3454	0	0	0
T175	3782	0	0	0
T176	13153	24	0	0
T191	0	12	0	0
T204	133122	0	0	0
T229	0	26	0	0
T231	0	50	0	0
T236	0	72	0	0
T261	0	87	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5478	0	0
T108	7854	147	0	0
T109	8069	65	0	0
T110	26584	224	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	66	0	0
T115	3454	0	0	0
T175	3782	0	0	0
T176	13153	36	0	0
T191	0	12	0	0
T204	133122	0	0	0
T229	0	8	0	0
T231	0	42	0	0
T236	0	79	0	0
T261	0	68	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4191	0	0
T14	0	15	0	0
T19	0	185	0	0
T108	7854	163	0	0
T109	8069	73	0	0
T110	26584	0	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	0	0	0
T115	3454	0	0	0
T117	0	8	0	0
T175	3782	0	0	0
T176	13153	12	0	0
T204	133122	0	0	0
T229	0	3	0	0
T236	0	97	0	0
T262	0	13	0	0
T263	0	48	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3329	0	0
T14	0	41	0	0
T19	0	188	0	0
T117	9002	10	0	0
T122	0	67	0	0
T206	0	45	0	0
T216	0	118	0	0
T247	3673	0	0	0
T256	0	34	0	0
T262	9577	11	0	0
T264	0	152	0	0
T265	0	64	0	0
T266	12671	0	0	0
T267	50764	0	0	0
T268	3686	0	0	0
T269	4084	0	0	0
T270	3689	0	0	0
T271	6349	0	0	0
T272	3411	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2298	0	0
T14	160757	11	0	0
T19	369023	133	0	0
T42	13551	0	0	0
T69	12657	0	0	0
T122	0	44	0	0
T206	0	26	0	0
T216	0	71	0	0
T256	0	71	0	0
T264	0	55	0	0
T265	0	53	0	0
T273	0	61	0	0
T274	0	65	0	0
T275	16883	0	0	0
T276	19672	0	0	0
T277	47065	0	0	0
T278	15811	0	0	0
T279	88049	0	0	0
T280	6238	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2574	0	0
T14	160757	16	0	0
T19	369023	135	0	0
T42	13551	0	0	0
T69	12657	0	0	0
T122	0	19	0	0
T206	0	67	0	0
T216	0	114	0	0
T256	0	50	0	0
T264	0	34	0	0
T265	0	64	0	0
T273	0	41	0	0
T274	0	93	0	0
T275	16883	0	0	0
T276	19672	0	0	0
T277	47065	0	0	0
T278	15811	0	0	0
T279	88049	0	0	0
T280	6238	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5281	0	0
T108	7854	149	0	0
T109	8069	93	0	0
T110	26584	222	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	79	0	0
T115	3454	0	0	0
T175	3782	0	0	0
T176	13153	26	0	0
T191	0	7	0	0
T204	133122	0	0	0
T229	0	18	0	0
T231	0	39	0	0
T236	0	86	0	0
T261	0	63	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5806	0	0
T108	7854	139	0	0
T109	8069	78	0	0
T110	26584	225	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T113	0	7	0	0
T114	129593	117	0	0
T115	3454	0	0	0
T175	3782	0	0	0
T176	13153	47	0	0
T190	0	6	0	0
T191	0	18	0	0
T204	133122	0	0	0
T229	0	53	0	0
T231	0	44	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3576	0	0
T14	0	29	0	0
T19	0	148	0	0
T108	7854	186	0	0
T109	8069	96	0	0
T110	26584	0	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	0	0	0
T115	3454	0	0	0
T117	0	15	0	0
T175	3782	0	0	0
T176	13153	44	0	0
T204	133122	0	0	0
T229	0	14	0	0
T236	0	81	0	0
T262	0	2	0	0
T263	0	47	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3809	0	0
T14	0	54	0	0
T19	0	179	0	0
T108	7854	150	0	0
T109	8069	99	0	0
T110	26584	0	0	0
T111	3098	0	0	0
T112	3661	0	0	0
T114	129593	0	0	0
T115	3454	0	0	0
T117	0	1	0	0
T175	3782	0	0	0
T176	13153	42	0	0
T204	133122	0	0	0
T229	0	9	0	0
T236	0	77	0	0
T262	0	5	0	0
T263	0	59	0	0