Unified Coverage Report :: Module :: prim_mubi8_sender

Module : prim_mubi8_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock	83.33	50.00				100.00	100.00
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre	83.33	50.00				100.00	100.00
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre	83.33	50.00				100.00	100.00
tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.92	71.76	78.57		95.24	72.22	81.82	gen_partitions[7].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	50.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.17	37.50				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.92	71.76	78.57		95.24	72.22	81.82	gen_partitions[7].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.00	97.62	95.56		87.50	93.18	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.00	97.62	95.56		87.50	93.18	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.00	97.62	95.56		87.50	93.18	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.00	82.50	90.00		96.55	78.57	82.35	gen_partitions[3].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.00	82.50	90.00		96.55	78.57	82.35	gen_partitions[3].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.00	82.50	90.00		96.55	78.57	82.35	gen_partitions[3].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.61	91.88	87.50		94.44	84.93	94.29	gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.61	91.88	87.50		94.44	84.93	94.29	gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.61	91.88	87.50		94.44	84.93	94.29	gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.61	91.88	87.50		94.44	84.93	94.29	gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prim_buf.u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi8_sender

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Module : prim_mubi8_sender

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_mubi8_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	398286	357084	0	0
T2	697914	686070	0	0
T3	541044	529746	0	0
T4	852852	833532	0	0
T5	9002196	9002154	0	0
T8	491232	479472	0	0
T9	569268	558054	0	0
T10	432936	422394	0	0
T11	541506	532518	0	0
T12	316848	313320	0	0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[3].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[4].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[5].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[7].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	3	50.00
CONT_ASSIGN	34	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	0	1
48	0	1
55	1	1
56	1	1
58	1	1
85	0	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[0].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[1].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[2].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_bufs[6].u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_write_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_prim_mubi8_sender_read_lock_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_write_lock.u_prim_mubi8_sender_write_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
ALWAYS	55	3	3	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
48	1	1
55	1	1
56	1	1
58	1	1
85	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	55	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sender.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.gen_digest_read_lock.u_prim_mubi8_sender_read_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0