Unified Coverage Report :: Module :: otp_ctrl_lfsr_timer

Module : otp_ctrl_lfsr_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.23	100.00	96.15		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_ctrl_lfsr_timer	99.23	100.00	96.15		100.00	100.00	100.00

---

Module Instance : tb.dut.u_otp_ctrl_lfsr_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.23	100.00	96.15		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.21	100.00	96.25	87.02	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count_cnsty	93.60			93.60
u_prim_count_integ	93.60			93.60
u_prim_double_lfsr	94.28	100.00	100.00	77.11			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	114	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	142	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00
CONT_ASSIGN	191	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
ALWAYS	244	52	52	100.00
ALWAYS	365	3	3	100.00
ALWAYS	368	13	13	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
72	1	1
77	1	1
78	1	1
87	1	1
114	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
138	1	1
139	1	1
141	1	1
142	1	1
143	1	1
144	1	1
187	1	1
188	1	1
189	1	1
191	1	1
199	1	1
200	1	1
241	1	1
244	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
255	1	1
256	1	1
259	1	1
260	1	1
261	1	1
264	1	1
265	1	1
267	1	1
272	1	1
273	1	1
274	1	1
			MISSING_ELSE
281	1	1
282	1	1
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
288	1	1
289	1	1
290	1	1
			MISSING_ELSE
298	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
305	1	1
306	1	1
			MISSING_ELSE
314	1	1
320	1	1
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
327	1	1
328	1	1
			MISSING_ELSE
335	1	1
336	1	1
337	1	1
338	1	1
			MISSING_ELSE
354	1	1
356	1	1
357	1	1
			MISSING_ELSE
365	3	3
368	1	1
369	1	1
370	1	1
371	1	1
372	1	1
373	1	1
374	1	1
376	1	1
377	1	1
378	1	1
379	1	1
380	1	1
381	1	1

---

Cond Coverage for Module : otp_ctrl_lfsr_timer

	Total	Covered	Percent
Conditions	78	75	96.15
Logical	78	75	96.15
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (reseed_en ? '0 : (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)))
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7

 LINE       72
 SUB-EXPRESSION (edn_req_o ? reseed_cnt_q : (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q))
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7

 LINE       72
 SUB-EXPRESSION (lfsr_en ? ((reseed_cnt_q + 1'b1)) : reseed_cnt_q)
                 ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7
1	1	Covered	T7

 LINE       87
 EXPRESSION (reseed_en ? edn_data_i[(otp_ctrl_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7

 LINE       101
 EXPRESSION (reseed_en || lfsr_en)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7

 LINE       132
 EXPRESSION (timeout_i == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       133
 EXPRESSION (integ_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       134
 EXPRESSION (cnsty_period_msk_i == '0)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       135
 EXPRESSION (integ_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       136
 EXPRESSION (cnsty_cnt == '0)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (integ_set_period || integ_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       139
 EXPRESSION (cnsty_set_period || cnsty_set_timeout)
             --------1-------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T4
1	0	Covered	T3,T8,T4

 LINE       143
 EXPRESSION (integ_set_period ? ((lfsr_state & integ_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       144
 EXPRESSION (cnsty_set_period ? ((lfsr_state & cnsty_mask)) : (40'(timeout_i)))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T4

 LINE       166
 EXPRESSION (((!cnsty_cnt_zero)) && ((!cnsty_cnt_pause)))
             ---------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90,T17,T96
1	1	Covered	T3,T8,T4

 LINE       189
 EXPRESSION (set_all_integ_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((integ_chk_req_q & (~integ_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       191
 EXPRESSION (set_all_cnsty_reqs ? ({otp_ctrl_reg_pkg::NumPart {1'b1}}) : ((cnsty_chk_req_q & (~cnsty_chk_ack_i))))
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T8,T4

 LINE       199
 EXPRESSION ((integ_chk_trig_q & ((~clr_integ_chk_trig))) | integ_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       199
 SUB-EXPRESSION (integ_chk_trig_q & ((~clr_integ_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       200
 EXPRESSION ((cnsty_chk_trig_q & ((~clr_cnsty_chk_trig))) | cnsty_chk_trig_i)
             ----------------------1---------------------   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T5,T6,T54

 LINE       200
 SUB-EXPRESSION (cnsty_chk_trig_q & ((~clr_cnsty_chk_trig)))
                 --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8
1	1	Covered	T5,T6,T54

 LINE       260
 EXPRESSION (cnsty_chk_trig_q || integ_chk_trig_q)
             --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T8

 LINE       281
 EXPRESSION ((((!integ_msk_zero)) && integ_cnt_zero) || integ_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T90,T17

 LINE       281
 SUB-EXPRESSION (((!integ_msk_zero)) && integ_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T90,T17
1	1	Covered	T5,T90,T17

 LINE       286
 EXPRESSION ((((!cnsty_msk_zero)) && cnsty_cnt_zero) || cnsty_chk_trig_q)
             -------------------1-------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T4
1	0	Covered	T90,T17,T13

 LINE       286
 SUB-EXPRESSION (((!cnsty_msk_zero)) && cnsty_cnt_zero)
                 ---------1---------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T90,T17,T13
1	1	Covered	T90,T17,T13

 LINE       299
 EXPRESSION (((!timeout_zero)) && integ_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T89,T90,T17
1	0	Covered	T1,T2,T4
1	1	Covered	T5,T90,T17

 LINE       302
 EXPRESSION (integ_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       321
 EXPRESSION (((!timeout_zero)) && cnsty_cnt_zero)
             --------1--------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T75,T90,T106
1	0	Covered	T3,T8,T4
1	1	Covered	T90,T17,T76

 LINE       324
 EXPRESSION (cnsty_chk_req_q == '0)
            -----------1-----------

-1-	Status	Tests
0	Covered	T3,T8,T4
1	Covered	T3,T8,T4

---

FSM Coverage for Module : otp_ctrl_lfsr_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	9	9	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyWaitSt	287	Covered	T21
ErrorSt	300	Covered	T21
IdleSt	273	Covered	T21
IntegWaitSt	282	Covered	T21
ResetSt	271	Covered	T21

transitions	Line No.	Covered	Tests
CnstyWaitSt->ErrorSt	322	Covered	T21
CnstyWaitSt->IdleSt	325	Covered	T21
IdleSt->CnstyWaitSt	287	Covered	T21
IdleSt->ErrorSt	356	Covered	T21
IdleSt->IntegWaitSt	282	Covered	T21
IntegWaitSt->ErrorSt	300	Covered	T21
IntegWaitSt->IdleSt	303	Covered	T21
ResetSt->ErrorSt	356	Covered	T21
ResetSt->IdleSt	273	Covered	T21

---

Branch Coverage for Module : otp_ctrl_lfsr_timer

	Line No.	Total	Covered	Percent
Branches		34	34	100.00
TERNARY	72	4	4	100.00
TERNARY	87	2	2	100.00
TERNARY	143	2	2	100.00
TERNARY	144	2	2	100.00
TERNARY	189	2	2	100.00
TERNARY	191	2	2	100.00
CASE	267	14	14	100.00
IF	354	2	2	100.00
IF	365	2	2	100.00
IF	368	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_lfsr_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	72	(reseed_en) ? 
-2-:	72	(edn_req_o) ? 
-3-:	72	(lfsr_en) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7
0	1	-	Covered	T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	143	(integ_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	144	(cnsty_set_period) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	189	(set_all_integ_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	191	(set_all_cnsty_reqs) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	267	case (state_q)
-2-:	272	if (timer_en_i)
-3-:	281	if ((((!integ_msk_zero) && integ_cnt_zero) || integ_chk_trig_q))
-4-:	286	if ((((!cnsty_msk_zero) && cnsty_cnt_zero) || cnsty_chk_trig_q))
-5-:	299	if (((!timeout_zero) && integ_cnt_zero))
-6-:	302	if ((integ_chk_req_q == '0))
-7-:	321	if (((!timeout_zero) && cnsty_cnt_zero))
-8-:	324	if ((cnsty_chk_req_q == '0))
-9-:	337	if ((!chk_timeout_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	1	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	0	1	-	-	-	-	-	Covered	T3,T8,T4
IdleSt	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
IntegWaitSt	-	-	-	1	-	-	-	-	Covered	T5,T90,T17
IntegWaitSt	-	-	-	0	1	-	-	-	Covered	T1,T2,T4
IntegWaitSt	-	-	-	0	0	-	-	-	Covered	T1,T2,T4
CnstyWaitSt	-	-	-	-	-	1	-	-	Covered	T90,T17,T76
CnstyWaitSt	-	-	-	-	-	0	1	-	Covered	T3,T8,T4
CnstyWaitSt	-	-	-	-	-	0	0	-	Covered	T3,T8,T4
ErrorSt	-	-	-	-	-	-	-	1	Covered	T2,T3,T8
ErrorSt	-	-	-	-	-	-	-	0	Covered	T5,T90,T17
default	-	-	-	-	-	-	-	-	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	354	if ((((lfsr_err || integ_cnt_err) || cnsty_cnt_err) || lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i)))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	365	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	368	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_lfsr_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ChkPendingKnown_A	2147483647	2147483647	0	0
ChkTimeoutKnown_A	2147483647	2147483647	0	0
CnstyChkReqKnown_A	2147483647	2147483647	0	0
EdnIsWideEnough_A	1158	1158	0	0
EdnReqKnown_A	2147483647	2147483647	0	0
IntegChkReqKnown_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

ChkPendingKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

ChkTimeoutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

CnstyChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

EdnIsWideEnough_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

EdnReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

IntegChkReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9483	8502	0	0
T2	16617	16335	0	0
T3	12882	12613	0	0
T4	20306	19846	0	0
T5	214338	214337	0	0
T8	11696	11416	0	0
T9	13554	13287	0	0
T10	10308	10057	0	0
T11	12893	12679	0	0
T12	7544	7460	0	0