Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8403682	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14764556

1

T15

296

T101

21

T102

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7399746	1			T15	124		T101	20		T102	11
values[0x0]	6028343	1			T15	151		T101	12		T102	5
values[0x1]	9740149	1			T15	140		T101	8		T102	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4464684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18703554

1

T15

329

T101

25

T102

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	86537	1			T104	4		T174	2		T176	6
valid_sources[0x01]	91288	1			T103	1		T176	15		T177	1
valid_sources[0x02]	92034	1			T174	2		T176	10		T225	2
valid_sources[0x03]	92143	1			T176	9		T177	1		T225	3
valid_sources[0x04]	90241	1			T176	9		T225	2		T224	1
valid_sources[0x05]	91760	1			T104	7		T176	10		T177	1
valid_sources[0x06]	97032	1			T173	1		T104	3		T176	16
valid_sources[0x07]	91756	1			T104	2		T176	15		T225	1
valid_sources[0x08]	85949	1			T104	1		T176	12		T177	2
valid_sources[0x09]	87099	1			T173	1		T104	2		T176	14
valid_sources[0x0a]	87963	1			T173	2		T104	4		T176	7
valid_sources[0x0b]	92587	1			T101	3		T176	8		T225	1
valid_sources[0x0c]	84940	1			T104	5		T176	10		T226	2
valid_sources[0x0d]	89795	1			T101	2		T104	1		T176	10
valid_sources[0x0e]	88653	1			T174	1		T176	15		T177	1
valid_sources[0x0f]	85945	1			T173	1		T103	1		T176	8
valid_sources[0x10]	90334	1			T15	48		T103	1		T176	16
valid_sources[0x11]	88242	1			T176	4		T224	8		T228	10
valid_sources[0x12]	87140	1			T103	2		T176	8		T224	4
valid_sources[0x13]	85378	1			T173	1		T103	2		T176	11
valid_sources[0x14]	89943	1			T104	1		T174	3		T176	15
valid_sources[0x15]	84531	1			T176	10		T106	1		T225	2
valid_sources[0x16]	94662	1			T176	13		T177	2		T225	2
valid_sources[0x17]	88712	1			T104	2		T176	11		T106	1
valid_sources[0x18]	116022	1			T103	1		T176	6		T225	4
valid_sources[0x19]	88081	1			T103	2		T104	6		T176	7
valid_sources[0x1a]	86438	1			T104	9		T176	11		T225	2
valid_sources[0x1b]	88459	1			T104	3		T176	4		T177	1
valid_sources[0x1c]	93458	1			T103	20		T104	5		T176	12
valid_sources[0x1d]	93343	1			T103	3		T104	1		T176	10
valid_sources[0x1e]	88460	1			T15	13		T104	1		T176	10
valid_sources[0x1f]	106054	1			T104	9		T176	13		T106	1
valid_sources[0x20]	90998	1			T104	13		T176	10		T225	2
valid_sources[0x21]	85509	1			T104	2		T176	10		T177	1
valid_sources[0x22]	92928	1			T15	10		T102	1		T103	1
valid_sources[0x23]	94343	1			T173	1		T103	4		T104	4
valid_sources[0x24]	90060	1			T103	18		T104	3		T176	9
valid_sources[0x25]	88499	1			T104	3		T176	9		T177	1
valid_sources[0x26]	96547	1			T104	2		T176	9		T177	1
valid_sources[0x27]	147293	1			T103	4		T104	4		T174	6
valid_sources[0x28]	86049	1			T101	1		T103	2		T104	13
valid_sources[0x29]	86305	1			T103	1		T104	8		T176	9
valid_sources[0x2a]	84872	1			T104	9		T176	11		T177	1
valid_sources[0x2b]	97734	1			T176	4		T177	1		T225	1
valid_sources[0x2c]	91300	1			T103	2		T176	7		T225	4
valid_sources[0x2d]	85137	1			T176	5		T225	1		T226	2
valid_sources[0x2e]	87110	1			T103	2		T104	18		T176	9
valid_sources[0x2f]	87824	1			T103	2		T176	14		T226	1
valid_sources[0x30]	86103	1			T176	3		T224	6		T226	7
valid_sources[0x31]	89582	1			T103	11		T104	2		T176	13
valid_sources[0x32]	88973	1			T176	8		T177	1		T106	1
valid_sources[0x33]	90815	1			T173	2		T104	7		T176	1
valid_sources[0x34]	89900	1			T104	21		T176	11		T178	21
valid_sources[0x35]	87837	1			T15	28		T104	14		T174	3
valid_sources[0x36]	91238	1			T104	2		T174	2		T176	6
valid_sources[0x37]	91226	1			T104	12		T176	2		T177	2
valid_sources[0x38]	88951	1			T104	2		T176	13		T177	3
valid_sources[0x39]	87734	1			T104	4		T174	3		T176	11
valid_sources[0x3a]	87866	1			T174	5		T176	4		T225	2
valid_sources[0x3b]	90835	1			T176	8		T177	2		T106	1
valid_sources[0x3c]	85181	1			T103	5		T104	1		T176	7
valid_sources[0x3d]	88884	1			T101	4		T103	8		T176	5
valid_sources[0x3e]	87763	1			T104	4		T176	11		T177	1
valid_sources[0x3f]	91487	1			T103	1		T104	3		T176	4
valid_sources[0x40]	89646	1			T101	2		T104	6		T176	9
valid_sources[0x41]	86994	1			T176	8		T178	30		T106	1
valid_sources[0x42]	87513	1			T104	3		T175	8		T176	10
valid_sources[0x43]	87065	1			T173	4		T176	6		T177	1
valid_sources[0x44]	88871	1			T103	2		T176	9		T225	3
valid_sources[0x45]	86532	1			T103	2		T104	4		T174	5
valid_sources[0x46]	87035	1			T173	1		T104	4		T176	13
valid_sources[0x47]	87683	1			T174	2		T176	13		T177	1
valid_sources[0x48]	88533	1			T173	3		T103	2		T104	7
valid_sources[0x49]	89368	1			T103	7		T176	12		T177	2
valid_sources[0x4a]	93306	1			T104	11		T176	1		T106	1
valid_sources[0x4b]	87592	1			T103	2		T174	3		T176	13
valid_sources[0x4c]	94089	1			T173	1		T104	2		T176	11
valid_sources[0x4d]	89962	1			T103	1		T104	2		T176	5
valid_sources[0x4e]	91891	1			T176	5		T224	5		T226	2
valid_sources[0x4f]	94624	1			T104	10		T176	12		T177	1
valid_sources[0x50]	87506	1			T104	12		T176	7		T225	4
valid_sources[0x51]	89098	1			T104	3		T176	3		T177	1
valid_sources[0x52]	121247	1			T104	1		T176	15		T224	8
valid_sources[0x53]	88910	1			T104	1		T176	14		T225	3
valid_sources[0x54]	91150	1			T104	5		T176	5		T177	3
valid_sources[0x55]	87795	1			T103	6		T104	4		T176	2
valid_sources[0x56]	89079	1			T103	19		T176	3		T225	2
valid_sources[0x57]	100135	1			T104	3		T176	13		T225	2
valid_sources[0x58]	89448	1			T104	9		T176	9		T177	2
valid_sources[0x59]	89564	1			T104	4		T176	11		T177	1
valid_sources[0x5a]	87240	1			T103	11		T104	3		T176	14
valid_sources[0x5b]	93230	1			T173	1		T103	2		T104	9
valid_sources[0x5c]	87392	1			T173	2		T104	2		T176	5
valid_sources[0x5d]	91454	1			T173	1		T103	9		T104	6
valid_sources[0x5e]	88194	1			T104	6		T176	8		T226	5
valid_sources[0x5f]	84870	1			T101	1		T173	1		T103	2
valid_sources[0x60]	87829	1			T104	1		T176	4		T106	1
valid_sources[0x61]	86838	1			T103	7		T176	20		T225	5
valid_sources[0x62]	92018	1			T173	1		T103	9		T176	9
valid_sources[0x63]	96951	1			T101	5		T174	1		T176	5
valid_sources[0x64]	87050	1			T173	1		T103	4		T176	9
valid_sources[0x65]	85906	1			T103	3		T104	4		T176	11
valid_sources[0x66]	86389	1			T104	4		T176	4		T177	1
valid_sources[0x67]	88523	1			T104	1		T176	15		T177	1
valid_sources[0x68]	87520	1			T104	2		T176	8		T225	1
valid_sources[0x69]	98582	1			T103	1		T104	2		T176	10
valid_sources[0x6a]	88035	1			T176	3		T177	1		T225	5
valid_sources[0x6b]	85997	1			T104	5		T176	12		T225	2
valid_sources[0x6c]	92759	1			T15	20		T176	13		T225	1
valid_sources[0x6d]	86584	1			T173	2		T104	5		T176	5
valid_sources[0x6e]	92239	1			T176	5		T177	2		T225	1
valid_sources[0x6f]	88495	1			T173	1		T176	11		T225	1
valid_sources[0x70]	84740	1			T104	7		T176	4		T185	1
valid_sources[0x71]	95392	1			T104	4		T176	4		T177	1
valid_sources[0x72]	88135	1			T103	2		T104	5		T175	3
valid_sources[0x73]	97750	1			T173	1		T104	1		T176	7
valid_sources[0x74]	92154	1			T104	3		T176	12		T177	1
valid_sources[0x75]	89856	1			T104	3		T176	8		T177	1
valid_sources[0x76]	87080	1			T176	9		T226	10		T228	8
valid_sources[0x77]	98873	1			T104	3		T176	5		T177	1
valid_sources[0x78]	90530	1			T176	6		T225	3		T226	8
valid_sources[0x79]	86423	1			T101	6		T173	1		T104	8
valid_sources[0x7a]	86839	1			T173	2		T104	4		T174	3
valid_sources[0x7b]	89575	1			T103	1		T176	14		T106	1
valid_sources[0x7c]	88124	1			T176	8		T177	1		T106	1
valid_sources[0x7d]	86055	1			T173	1		T174	1		T176	8
valid_sources[0x7e]	154571	1			T176	5		T177	1		T224	8
valid_sources[0x7f]	91220	1			T104	11		T176	8		T177	1
valid_sources[0x80]	87261	1			T104	7		T176	9		T225	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4100115

1

T15

44

T101

14

T102

5

values[0x0]

all_enables

biggest_size

5372836

1

T15

132

T101

4

T102

1

values[0x1]

all_enables

biggest_size

5291605

1

T15

120

T101

3

T102

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	741556	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27396110

1

T15

82

T173

85

T103

84

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6901248	1			T15	231		T173	23		T103	203
values[0x0]	10306830	1			T15	41		T173	30		T103	44
values[0x1]	10929588	1			T15	43		T173	37		T103	40

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	255904	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27881762

1

T15

173

T173

89

T103

161

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	113030	1			T15	17		T103	2		T224	3
valid_sources[0x01]	108491	1			T103	6		T104	3		T174	7
valid_sources[0x02]	107261	1			T103	2		T174	1		T224	5
valid_sources[0x03]	113492	1			T104	4		T178	2		T224	2
valid_sources[0x04]	109333	1			T103	2		T104	10		T174	6
valid_sources[0x05]	113538	1			T104	5		T225	14		T226	4
valid_sources[0x06]	110287	1			T103	2		T104	10		T224	2
valid_sources[0x07]	109048	1			T104	3		T174	5		T224	1
valid_sources[0x08]	109286	1			T173	1		T178	2		T224	2
valid_sources[0x09]	116689	1			T104	9		T176	128		T178	3
valid_sources[0x0a]	110138	1			T15	19		T103	8		T178	1
valid_sources[0x0b]	113539	1			T103	1		T224	2		T226	1
valid_sources[0x0c]	111679	1			T173	1		T103	5		T226	4
valid_sources[0x0d]	110873	1			T178	1		T224	2		T226	5
valid_sources[0x0e]	112462	1			T103	2		T224	2		T228	10
valid_sources[0x0f]	106002	1			T103	4		T224	2		T226	5
valid_sources[0x10]	103298	1			T103	2		T104	3		T224	2
valid_sources[0x11]	106829	1			T173	1		T224	5		T226	3
valid_sources[0x12]	103628	1			T103	3		T178	1		T224	1
valid_sources[0x13]	105995	1			T225	6		T224	2		T226	2
valid_sources[0x14]	110822	1			T15	1		T173	1		T103	3
valid_sources[0x15]	110048	1			T103	1		T104	4		T224	1
valid_sources[0x16]	109949	1			T177	2		T178	1		T224	4
valid_sources[0x17]	114997	1			T103	2		T174	10		T177	12
valid_sources[0x18]	107200	1			T15	10		T173	1		T103	1
valid_sources[0x19]	108007	1			T103	1		T224	3		T228	9
valid_sources[0x1a]	108671	1			T173	1		T178	1		T224	3
valid_sources[0x1b]	109466	1			T224	6		T226	1		T228	9
valid_sources[0x1c]	108841	1			T177	8		T224	1		T226	2
valid_sources[0x1d]	105046	1			T103	2		T104	2		T176	128
valid_sources[0x1e]	109779	1			T173	1		T103	1		T224	1
valid_sources[0x1f]	107447	1			T224	1		T226	2		T228	11
valid_sources[0x20]	113226	1			T103	1		T224	5		T226	3
valid_sources[0x21]	108837	1			T173	1		T103	4		T174	1
valid_sources[0x22]	110079	1			T15	67		T174	3		T225	8
valid_sources[0x23]	111993	1			T103	2		T224	1		T226	1
valid_sources[0x24]	110093	1			T173	1		T224	3		T226	1
valid_sources[0x25]	111790	1			T173	1		T103	1		T104	2
valid_sources[0x26]	109047	1			T173	4		T103	1		T104	16
valid_sources[0x27]	109883	1			T103	2		T224	2		T226	1
valid_sources[0x28]	110912	1			T174	2		T224	1		T226	5
valid_sources[0x29]	106047	1			T104	6		T224	6		T226	3
valid_sources[0x2a]	111138	1			T103	1		T226	3		T228	11
valid_sources[0x2b]	105486	1			T173	1		T103	1		T224	3
valid_sources[0x2c]	113134	1			T173	1		T178	1		T224	1
valid_sources[0x2d]	110118	1			T173	1		T103	1		T224	1
valid_sources[0x2e]	106674	1			T224	4		T226	5		T228	7
valid_sources[0x2f]	110170	1			T173	2		T174	1		T224	4
valid_sources[0x30]	115697	1			T173	4		T103	1		T104	8
valid_sources[0x31]	110379	1			T173	1		T103	4		T224	2
valid_sources[0x32]	109613	1			T103	2		T174	5		T178	1
valid_sources[0x33]	110952	1			T103	4		T174	2		T178	2
valid_sources[0x34]	110011	1			T104	2		T174	9		T224	2
valid_sources[0x35]	107738	1			T174	4		T224	1		T226	3
valid_sources[0x36]	103128	1			T104	6		T224	2		T226	1
valid_sources[0x37]	107993	1			T224	2		T226	3		T228	7
valid_sources[0x38]	110393	1			T15	1		T173	1		T224	3
valid_sources[0x39]	111861	1			T103	2		T224	1		T228	14
valid_sources[0x3a]	106198	1			T173	2		T103	1		T104	6
valid_sources[0x3b]	110018	1			T103	2		T174	5		T224	4
valid_sources[0x3c]	110872	1			T173	2		T174	10		T224	4
valid_sources[0x3d]	104909	1			T174	1		T224	2		T228	11
valid_sources[0x3e]	109737	1			T104	7		T224	3		T228	8
valid_sources[0x3f]	106726	1			T103	1		T104	1		T224	2
valid_sources[0x40]	114774	1			T103	2		T174	2		T224	5
valid_sources[0x41]	107411	1			T173	1		T104	33		T174	1
valid_sources[0x42]	114218	1			T104	5		T174	1		T224	3
valid_sources[0x43]	107959	1			T15	7		T103	1		T178	1
valid_sources[0x44]	110798	1			T103	1		T104	1		T178	1
valid_sources[0x45]	105491	1			T104	5		T224	1		T228	11
valid_sources[0x46]	115384	1			T103	2		T224	2		T226	3
valid_sources[0x47]	107087	1			T103	2		T174	1		T224	2
valid_sources[0x48]	109987	1			T103	1		T174	6		T224	2
valid_sources[0x49]	108272	1			T15	28		T173	1		T103	3
valid_sources[0x4a]	105639	1			T15	7		T173	1		T103	2
valid_sources[0x4b]	111936	1			T173	1		T103	1		T178	1
valid_sources[0x4c]	117277	1			T103	2		T174	1		T226	5
valid_sources[0x4d]	117155	1			T104	3		T174	1		T225	4
valid_sources[0x4e]	104275	1			T15	7		T173	1		T104	10
valid_sources[0x4f]	110314	1			T173	1		T104	9		T174	10
valid_sources[0x50]	109579	1			T173	3		T103	1		T174	1
valid_sources[0x51]	107588	1			T173	1		T103	2		T104	16
valid_sources[0x52]	103116	1			T104	8		T224	4		T226	1
valid_sources[0x53]	109714	1			T104	10		T224	3		T226	1
valid_sources[0x54]	115122	1			T104	1		T224	1		T226	1
valid_sources[0x55]	107281	1			T224	2		T226	2		T228	9
valid_sources[0x56]	108510	1			T174	2		T224	3		T226	3
valid_sources[0x57]	107654	1			T173	1		T104	2		T174	2
valid_sources[0x58]	111766	1			T103	1		T178	1		T224	3
valid_sources[0x59]	109466	1			T103	1		T104	5		T174	8
valid_sources[0x5a]	110248	1			T225	1		T224	1		T226	2
valid_sources[0x5b]	110302	1			T173	1		T103	3		T104	4
valid_sources[0x5c]	112467	1			T178	1		T106	1		T224	2
valid_sources[0x5d]	114377	1			T224	1		T226	1		T228	8
valid_sources[0x5e]	114910	1			T224	1		T226	2		T228	5
valid_sources[0x5f]	106992	1			T174	4		T224	3		T226	3
valid_sources[0x60]	106278	1			T103	1		T178	2		T224	4
valid_sources[0x61]	114940	1			T103	1		T224	3		T226	4
valid_sources[0x62]	111167	1			T173	1		T226	1		T228	12
valid_sources[0x63]	114384	1			T224	3		T226	3		T228	11
valid_sources[0x64]	111288	1			T103	1		T224	3		T226	3
valid_sources[0x65]	116512	1			T173	2		T104	9		T177	6
valid_sources[0x66]	110279	1			T103	2		T224	3		T226	3
valid_sources[0x67]	103773	1			T225	8		T226	1		T228	5
valid_sources[0x68]	109748	1			T174	2		T224	3		T226	4
valid_sources[0x69]	110090	1			T103	2		T224	3		T226	2
valid_sources[0x6a]	112030	1			T103	1		T174	7		T224	1
valid_sources[0x6b]	108000	1			T15	15		T173	1		T224	4
valid_sources[0x6c]	117443	1			T178	1		T226	2		T228	6
valid_sources[0x6d]	108646	1			T103	5		T224	2		T226	2
valid_sources[0x6e]	106358	1			T103	5		T174	11		T225	10
valid_sources[0x6f]	104008	1			T103	1		T174	10		T224	3
valid_sources[0x70]	107487	1			T226	4		T228	8		T230	1
valid_sources[0x71]	108349	1			T104	15		T224	1		T228	16
valid_sources[0x72]	105214	1			T224	4		T228	6		T219	1
valid_sources[0x73]	108609	1			T103	2		T104	12		T106	2
valid_sources[0x74]	105396	1			T224	2		T226	3		T228	13
valid_sources[0x75]	113704	1			T104	3		T224	3		T226	2
valid_sources[0x76]	113381	1			T174	9		T226	3		T228	6
valid_sources[0x77]	107656	1			T103	2		T224	2		T226	1
valid_sources[0x78]	114324	1			T15	27		T103	3		T106	1
valid_sources[0x79]	102616	1			T104	4		T174	3		T224	4
valid_sources[0x7a]	110312	1			T173	4		T103	5		T104	3
valid_sources[0x7b]	112922	1			T103	1		T224	4		T228	5
valid_sources[0x7c]	112031	1			T104	8		T178	2		T224	2
valid_sources[0x7d]	112821	1			T103	3		T177	15		T224	1
valid_sources[0x7e]	111415	1			T224	2		T226	4		T228	4
valid_sources[0x7f]	113456	1			T103	1		T224	2		T228	7
valid_sources[0x80]	108357	1			T173	1		T225	7		T224	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6888337

1

T15

19

T173

23

T103

23

values[0x0]

all_enables

biggest_size

10255359

1

T15

35

T173

30

T103

35

values[0x1]

all_enables

biggest_size

10252414

1

T15

28

T173

32

T103

26