Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

60748969

1

T15

121

T101

19

T102

15

full_word

18172154

1

T15

296

T101

21

T102

7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	78920823	1			T15	407		T101	40		T102	22
auto[TlIntgErrCmd]	95	1			T15	4		T103	4		T104	9
auto[TlIntgErrData]	113	1			T15	3		T103	5		T104	4
auto[TlIntgErrBoth]	92	1			T15	3		T103	1		T104	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11490056

1

T15

124

T101

20

T102

11

auto[1]

67431067

1

T15

293

T101

20

T102

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6974989	1			T15	78		T101	6		T102	6
auto[TlIntgErrNone]	partial	auto[1]	53773708	1			T15	35		T101	13		T102	9
auto[TlIntgErrNone]	full_word	auto[0]	4514936	1			T15	43		T101	14		T102	5
auto[TlIntgErrNone]	full_word	auto[1]	13657190	1			T15	251		T101	7		T102	2
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T103	4		T104	4		T219	3
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T15	4		T104	4		T224	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T104	1		T224	1		T323	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T227	1		T286	2		T268	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T15	1		T103	4		T104	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T15	1		T103	1		T104	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T224	2		T219	1		T227	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T15	1		T321	2		T324	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T15	1		T104	4		T224	4
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T15	1		T103	1		T104	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T15	1		T226	1		T227	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T286	1		T323	1		-	-