Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.02	97.89	88.57	96.69		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	19300426	0	0
check_regwen_rd_A	2147483647	4352	0	0
check_timeout_rd_A	2147483647	4336	0	0
check_trigger_regwen_rd_A	2147483647	4419	0	0
consistency_check_period_rd_A	2147483647	4950	0	0
creator_sw_cfg_read_lock_rd_A	2147483647	4507	0	0
direct_access_address_rd_A	2147483647	4227	0	0
direct_access_wdata_0_rd_A	2147483647	2981	0	0
direct_access_wdata_1_rd_A	2147483647	3306	0	0
integrity_check_period_rd_A	2147483647	4671	0	0
intr_enable_rd_A	2147483647	5251	0	0
owner_sw_cfg_read_lock_rd_A	2147483647	3855	0	0
vendor_test_read_lock_rd_A	2147483647	3812	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19300426	0	0
T15	56075	1	0	0
T101	3583	0	0	0
T102	4135	0	0	0
T103	72479	5	0	0
T104	138433	3	0	0
T105	3396	0	0	0
T173	5292	193	0	0
T174	5159	103	0	0
T175	3686	0	0	0
T176	11820	0	0	0
T177	0	32	0	0
T178	0	16	0	0
T219	0	6	0	0
T224	0	7	0	0
T226	0	7	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4352	0	0
T103	72479	16	0	0
T104	138433	78	0	0
T106	5591	0	0	0
T174	5159	0	0	0
T175	3686	0	0	0
T176	11820	0	0	0
T177	9078	0	0	0
T178	6124	0	0	0
T179	0	6	0	0
T185	3614	0	0	0
T224	0	95	0	0
T233	0	31	0	0
T234	3414	0	0	0
T243	0	19	0	0
T265	0	15	0	0
T286	0	87	0	0
T287	0	12	0	0
T288	0	28	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4336	0	0
T11	0	173	0	0
T14	0	251	0	0
T107	6127	0	0	0
T179	6441	6	0	0
T180	6968	0	0	0
T181	14810	0	0	0
T182	4629	0	0	0
T230	3579	0	0	0
T231	3901	0	0	0
T233	0	28	0	0
T238	3412	0	0	0
T243	0	31	0	0
T284	3487	0	0	0
T287	0	8	0	0
T288	0	30	0	0
T289	0	9	0	0
T290	0	8	0	0
T291	0	96	0	0
T292	2959	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4419	0	0
T103	72479	6	0	0
T104	138433	82	0	0
T106	5591	0	0	0
T174	5159	0	0	0
T175	3686	0	0	0
T176	11820	0	0	0
T177	9078	0	0	0
T178	6124	0	0	0
T179	0	9	0	0
T185	3614	0	0	0
T224	0	71	0	0
T233	0	67	0	0
T234	3414	0	0	0
T243	0	45	0	0
T265	0	12	0	0
T286	0	69	0	0
T287	0	16	0	0
T288	0	24	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4950	0	0
T103	72479	21	0	0
T104	138433	70	0	0
T106	5591	0	0	0
T174	5159	0	0	0
T175	3686	0	0	0
T176	11820	0	0	0
T177	9078	0	0	0
T178	6124	0	0	0
T179	0	1	0	0
T185	3614	0	0	0
T224	0	61	0	0
T233	0	24	0	0
T234	3414	0	0	0
T243	0	35	0	0
T265	0	19	0	0
T286	0	93	0	0
T287	0	11	0	0
T288	0	27	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4507	0	0
T11	0	154	0	0
T14	0	281	0	0
T104	138433	3	0	0
T106	5591	0	0	0
T174	5159	0	0	0
T175	3686	0	0	0
T176	11820	0	0	0
T177	9078	0	0	0
T178	6124	0	0	0
T179	0	8	0	0
T185	3614	0	0	0
T225	10013	0	0	0
T233	0	45	0	0
T234	3414	0	0	0
T243	0	14	0	0
T260	0	260	0	0
T287	0	7	0	0
T288	0	7	0	0
T291	0	40	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4227	0	0
T11	0	195	0	0
T14	0	207	0	0
T107	6127	0	0	0
T169	0	104	0	0
T170	0	261	0	0
T179	6441	8	0	0
T180	6968	0	0	0
T181	14810	0	0	0
T182	4629	0	0	0
T202	0	127	0	0
T230	3579	0	0	0
T231	3901	0	0	0
T238	3412	0	0	0
T260	0	197	0	0
T284	3487	0	0	0
T287	0	5	0	0
T292	2959	0	0	0
T293	0	47	0	0
T294	0	127	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2981	0	0
T11	256225	137	0	0
T14	313070	124	0	0
T17	0	89	0	0
T24	12669	0	0	0
T48	9435	0	0	0
T64	14973	0	0	0
T65	13796	0	0	0
T97	24450	0	0	0
T115	11831	0	0	0
T116	5036	0	0	0
T161	96610	0	0	0
T169	0	41	0	0
T170	0	224	0	0
T172	0	44	0	0
T202	0	132	0	0
T260	0	162	0	0
T293	0	19	0	0
T294	0	82	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3306	0	0
T11	256225	118	0	0
T14	313070	138	0	0
T17	0	92	0	0
T24	12669	0	0	0
T48	9435	0	0	0
T64	14973	0	0	0
T65	13796	0	0	0
T97	24450	0	0	0
T115	11831	0	0	0
T116	5036	0	0	0
T161	96610	0	0	0
T169	0	60	0	0
T170	0	164	0	0
T172	0	33	0	0
T202	0	120	0	0
T260	0	229	0	0
T293	0	24	0	0
T294	0	91	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4671	0	0
T103	72479	26	0	0
T104	138433	72	0	0
T106	5591	0	0	0
T174	5159	0	0	0
T175	3686	0	0	0
T176	11820	0	0	0
T177	9078	0	0	0
T178	6124	0	0	0
T179	0	8	0	0
T185	3614	0	0	0
T224	0	71	0	0
T233	0	25	0	0
T234	3414	0	0	0
T243	0	26	0	0
T265	0	14	0	0
T286	0	65	0	0
T287	0	3	0	0
T288	0	48	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5251	0	0
T101	3583	17	0	0
T102	4135	4	0	0
T103	72479	23	0	0
T104	138433	98	0	0
T105	3396	0	0	0
T173	5292	0	0	0
T174	5159	0	0	0
T175	3686	14	0	0
T176	11820	0	0	0
T177	9078	0	0	0
T179	0	15	0	0
T224	0	125	0	0
T234	0	10	0	0
T236	0	11	0	0
T248	0	19	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3855	0	0
T11	0	102	0	0
T14	0	185	0	0
T107	6127	0	0	0
T179	6441	2	0	0
T180	6968	0	0	0
T181	14810	0	0	0
T182	4629	0	0	0
T230	3579	0	0	0
T231	3901	0	0	0
T233	0	18	0	0
T238	3412	0	0	0
T243	0	4	0	0
T260	0	180	0	0
T284	3487	0	0	0
T287	0	8	0	0
T288	0	22	0	0
T291	0	69	0	0
T292	2959	0	0	0
T295	0	2	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3812	0	0
T11	0	111	0	0
T14	0	183	0	0
T107	6127	0	0	0
T179	6441	9	0	0
T180	6968	0	0	0
T181	14810	0	0	0
T182	4629	0	0	0
T202	0	130	0	0
T230	3579	0	0	0
T231	3901	0	0	0
T233	0	53	0	0
T238	3412	0	0	0
T243	0	23	0	0
T260	0	226	0	0
T284	3487	0	0	0
T287	0	7	0	0
T288	0	41	0	0
T291	0	82	0	0
T292	2959	0	0	0