Unified Coverage Report :: Module :: otp_ctrl_ecc_reg

Module : otp_ctrl_ecc_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	91.67	100.00	66.67			100.00	100.00
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	91.67	100.00	66.67			100.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	91.67	100.00	66.67			100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	91.67	100.00	66.67			100.00	100.00
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg	91.67	100.00	66.67			100.00	100.00
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg	100.00	100.00	100.00			100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg	100.00	100.00	100.00			100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.08	100.00	66.67	93.73		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.56	80.62	88.00		89.66	77.14	82.35	gen_partitions[3].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.18	100.00	66.67	94.23		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[4].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.07	100.00	66.67	93.69		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.61	91.88	87.50		94.44	84.93	94.29	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.07	100.00	66.67	93.69		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.16	91.88	87.50		97.22	84.93	94.29	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.11	100.00	66.67	73.88		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.92	71.76	78.57		95.24	72.22	81.82	gen_partitions[7].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	73.97			73.97
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	71.23			71.23
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	72.60			72.60
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	75.34			75.34
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	76.03			76.03
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	72.60			72.60
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	83.56			83.56
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	63.70			63.70
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	73.97			73.97
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	58.90			58.90
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	66.44			66.44
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	100.00	100.00	97.87		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.17	97.62	95.56		83.33	93.18	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	100.00	100.00	97.87		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	100.00	100.00	97.87		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
u_prim_secded_inv_72_64_enc	100.00			100.00

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=1,Aw=1,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	45	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=10,Aw=4,EccWidth=8 + Width=64,Depth=5,Aw=3,EccWidth=8 + Width=64,Depth=11,Aw=4,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
91.67	100.00

tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
91.67	100.00

tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
91.67	100.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
91.67	100.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
91.67	100.00

tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	55	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
56	1	1
57	1	1
59	1	1
60	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Module : otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	9264	9264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	115688	113696	0	0
T2	310416	303576	0	0
T3	573224	562448	0	0
T4	531872	520528	0	0
T5	142832	140440	0	0
T6	720160	712448	0	0
T7	125232	123256	0	0
T8	251592	248064	0	0
T9	237256	235256	0	0
T10	379136	372264	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	115688	113696	0	0
T2	310416	303576	0	0
T3	573224	562448	0	0
T4	531872	520528	0	0
T5	142832	140440	0	0
T6	720160	712448	0	0
T7	125232	123256	0	0
T8	251592	248064	0	0
T9	237256	235256	0	0
T10	379136	372264	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	115688	113696	0	0
T2	310416	303576	0	0
T3	573224	562448	0	0
T4	531872	520528	0	0
T5	142832	140440	0	0
T6	720160	712448	0	0
T7	125232	123256	0	0
T8	251592	248064	0	0
T9	237256	235256	0	0
T10	379136	372264	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	115688	113696	0	0
T2	310416	303576	0	0
T3	573224	562448	0	0
T4	531872	520528	0	0
T5	142832	140440	0	0
T6	720160	712448	0	0
T7	125232	123256	0	0
T8	251592	248064	0	0
T9	237256	235256	0	0
T10	379136	372264	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9264	9264	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T5	8	8	0	0
T6	8	8	0	0
T7	8	8	0	0
T8	8	8	0	0
T9	8	8	0	0
T10	8	8	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	55	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
56	1	1
57	1	1
59	1	1
60	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	55	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
56	1	1
57	1	1
59	1	1
60	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	55	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
56	1	1
57	1	1
59	1	1
60	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	55	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
56	1	1
57	1	1
59	1	1
60	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	55	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55	1	1
56	1	1
57	1	1
59	1	1
60	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	3	2	66.67
Logical	3	2	66.67
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	45	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	45	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
ALWAYS	45	5	5	100.00
CONT_ASSIGN	78	1	1	100.00
ALWAYS	81	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
46	1	1
47	1	1
49	1	1
50	1	1
			MISSING_ELSE
78	1	1
81	1	1
82	1	1
83	1	1
85	1	1
86	1	1

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       49
 EXPRESSION (wren_i && (32'(addr_i) < Depth))
             ---1--    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	81	2	2	100.00
IF	49	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	81	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((wren_i && (32'(addr_i) < Depth)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	1158	1158	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14461	14212	0	0
T2	38802	37947	0	0
T3	71653	70306	0	0
T4	66484	65066	0	0
T5	17854	17555	0	0
T6	90020	89056	0	0
T7	15654	15407	0	0
T8	31449	31008	0	0
T9	29657	29407	0	0
T10	47392	46533	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1158	1158	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0