Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.07	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if	10.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if	20.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
10.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	9	1	10.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	9	1	10.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
20.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	8	2	20.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	8	2	20.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	9	1	10.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1
true	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

14361

1

T65

1

T98

1

T99

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	8	2	20.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

10283

1

T65

1

T98

1

T99

1

true

16598

1

T65

1

T98

1

T99

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	118	1			T8	2		T22	2		T77	2
others[1]	86	1			T7	2		T8	2		T308	2
others[2]	110	1			T8	4		T22	2		T87	2
others[3]	92	1			T8	2		T22	4		T160	2
others[4]	120	1			T22	2		T77	2		T79	2
others[5]	102	1			T22	4		T90	2		T81	2
others[6]	90	1			T7	2		T22	2		T76	2
others[7]	112	1			T5	4		T7	2		T8	2
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	94	1			T22	2		T81	4		T19	2
others[1]	86	1			T22	2		T335	2		T166	2
others[2]	100	1			T7	2		T8	2		T308	2
others[3]	86	1			T22	2		T76	2		T36	2
others[4]	112	1			T22	6		T83	2		T161	2
others[5]	68	1			T22	2		T78	2		T86	2
others[6]	100	1			T8	4		T22	6		T336	2
others[7]	142	1			T7	2		T22	12		T85	2
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	88	1			T22	4		T77	2		T85	2
others[1]	106	1			T8	2		T22	4		T309	2
others[2]	98	1			T8	2		T79	2		T19	2
others[3]	86	1			T5	2		T8	4		T22	2
others[4]	74	1			T22	2		T77	2		T79	2
others[5]	80	1			T22	4		T337	2		T207	2
others[6]	84	1			T81	2		T308	2		T338	2
others[7]	120	1			T8	2		T22	2		T80	2
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	88	1			T22	4		T339	2		T309	2
others[1]	80	1			T77	2		T82	2		T84	2
others[2]	76	1			T22	2		T308	2		T337	2
others[3]	116	1			T8	4		T19	2		T83	2
others[4]	112	1			T7	2		T8	2		T22	2
others[5]	100	1			T22	2		T79	2		T19	2
others[6]	72	1			T8	2		T22	6		T164	2
others[7]	112	1			T22	2		T308	2		T339	2
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	90	1			T8	4		T22	2		T78	2
others[1]	106	1			T77	2		T340	2		T339	2
others[2]	92	1			T5	2		T8	2		T341	2
others[3]	82	1			T36	2		T207	2		T339	2
others[4]	100	1			T337	2		T338	2		T340	2
others[5]	96	1			T5	2		T22	2		T86	2
others[6]	52	1			T336	2		T342	2		T343	2
others[7]	114	1			T22	6		T81	2		T87	2
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	88	1			T80	2		T344	2		T345	2
others[1]	86	1			T8	2		T83	2		T337	2
others[2]	130	1			T7	2		T76	2		T78	2
others[3]	84	1			T8	2		T77	2		T19	2
others[4]	82	1			T7	2		T8	4		T22	2
others[5]	82	1			T22	4		T337	4		T338	2
others[6]	100	1			T8	2		T22	2		T82	2
others[7]	120	1			T5	2		T22	2		T87	2
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	72	1			T8	4		T81	2		T346	2
others[1]	108	1			T22	4		T80	2		T19	2
others[2]	74	1			T337	2		T309	2		T336	2
others[3]	102	1			T7	2		T8	2		T85	4
others[4]	82	1			T22	2		T77	4		T176	2
others[5]	102	1			T87	2		T161	2		T308	2
others[6]	84	1			T22	2		T77	2		T36	2
others[7]	82	1			T77	2		T164	2		T167	4
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30	1			T81	2		T165	2		T347	4
others[1]	28	1			T161	2		T165	2		T348	2
others[2]	34	1			T167	2		T169	2		T349	2
others[3]	36	1			T350	2		T134	2		T351	2
others[4]	36	1			T163	2		T168	4		T349	2
others[5]	26	1			T166	2		T167	2		T347	8
others[6]	30	1			T165	2		T348	2		T347	2
others[7]	28	1			T162	2		T164	2		T348	2
false	14361	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	42	1			T6	1		T189	1		T352	1
others[1]	27	1			T108	1		T249	1		T250	1
others[2]	38	1			T3	1		T12	1		T91	1
others[3]	42	1			T340	2		T352	1		T249	2
others[4]	45	1			T22	2		T91	1		T203	2
others[5]	36	1			T6	1		T91	1		T189	1
others[6]	34	1			T6	1		T108	1		T353	1
others[7]	46	1			T91	1		T203	1		T94	2
false	14361	1			T65	1		T98	1		T99	1
true	2441	1			T1	1		T3	2		T5	3

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35	1			T22	2		T249	1		T354	1
others[1]	46	1			T12	1		T91	2		T94	1
others[2]	25	1			T189	1		T94	1		T354	1
others[3]	43	1			T92	1		T108	1		T203	1
others[4]	40	1			T6	1		T93	1		T250	1
others[5]	37	1			T6	1		T91	1		T189	1
others[6]	29	1			T3	1		T203	2		T352	1
others[7]	54	1			T6	1		T91	1		T108	2
false	11604	1			T65	1		T98	1		T99	1
true	19021	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	90	1			T7	2		T22	2		T77	2
others[1]	104	1			T160	2		T87	2		T309	4
others[2]	90	1			T22	4		T81	2		T82	2
others[3]	124	1			T8	2		T22	2		T81	2
others[4]	102	1			T5	2		T8	4		T90	2
others[5]	106	1			T5	2		T8	4		T22	4
others[6]	108	1			T7	2		T8	2		T22	2
others[7]	106	1			T7	2		T22	4		T76	2
false	7401	1			T65	1		T98	1		T99	1
true	16649	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	82	1			T7	2		T22	2		T81	2
others[1]	124	1			T22	6		T36	2		T83	2
others[2]	106	1			T22	6		T76	2		T337	2
others[3]	76	1			T8	2		T22	8		T344	2
others[4]	88	1			T22	6		T86	2		T337	2
others[5]	104	1			T22	2		T78	2		T81	4
others[6]	76	1			T342	2		T355	2		T356	2
others[7]	132	1			T7	2		T8	4		T22	2
false	6935	1			T65	1		T98	1		T99	1
true	16457	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35	1			T92	1		T108	2		T357	1
others[1]	41	1			T108	1		T203	1		T94	1
others[2]	45	1			T91	1		T189	1		T203	1
others[3]	43	1			T3	1		T6	2		T92	1
others[4]	27	1			T77	2		T91	1		T203	1
others[5]	36	1			T190	2		T250	2		T266	1
others[6]	46	1			T22	2		T12	1		T108	1
others[7]	64	1			T6	2		T189	1		T93	2
false	11541	1			T65	1		T98	1		T99	1
true	19018	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	94	1			T22	2		T291	2		T339	2
others[1]	102	1			T22	2		T77	2		T80	2
others[2]	84	1			T22	4		T337	2		T207	2
others[3]	90	1			T8	2		T22	2		T79	2
others[4]	84	1			T81	2		T207	2		T309	6
others[5]	88	1			T5	2		T8	4		T22	4
others[6]	86	1			T8	2		T161	2		T338	2
others[7]	108	1			T8	2		T22	4		T77	2
false	7639	1			T65	1		T98	1		T99	1
true	16626	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	84	1			T8	2		T22	2		T338	2
others[1]	80	1			T7	2		T82	2		T339	2
others[2]	114	1			T8	2		T22	4		T81	2
others[3]	78	1			T22	4		T79	2		T308	2
others[4]	88	1			T22	6		T308	2		T309	2
others[5]	118	1			T8	2		T19	4		T161	2
others[6]	88	1			T22	2		T77	2		T342	4
others[7]	106	1			T8	2		T337	2		T207	2
false	7057	1			T65	1		T98	1		T99	1
true	16452	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	96	1			T8	2		T22	2		T78	2
others[1]	106	1			T336	2		T358	2		T165	2
others[2]	84	1			T8	2		T22	2		T81	2
others[3]	86	1			T8	2		T22	4		T87	2
others[4]	76	1			T77	2		T341	2		T164	2
others[5]	92	1			T5	2		T22	2		T36	2
others[6]	86	1			T5	2		T338	2		T340	2
others[7]	106	1			T83	2		T86	2		T161	2
false	7057	1			T65	1		T98	1		T99	1
true	16452	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	118	1			T7	2		T8	2		T78	2
others[1]	86	1			T85	2		T176	2		T359	2
others[2]	114	1			T8	2		T86	2		T342	2
others[3]	88	1			T5	2		T7	2		T8	2
others[4]	88	1			T8	4		T76	2		T77	2
others[5]	94	1			T22	2		T80	2		T83	2
others[6]	92	1			T344	2		T337	2		T340	2
others[7]	92	1			T22	4		T87	2		T338	2
false	6405	1			T65	1		T98	1		T99	1
true	16441	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	82	1			T84	2		T176	2		T207	2
others[1]	96	1			T22	2		T85	2		T161	2
others[2]	78	1			T8	4		T83	2		T337	2
others[3]	92	1			T8	2		T81	2		T176	2
others[4]	84	1			T22	2		T77	4		T19	2
others[5]	80	1			T7	2		T309	2		T345	2
others[6]	96	1			T77	2		T80	2		T19	2
others[7]	98	1			T22	4		T77	2		T36	2
false	6405	1			T65	1		T98	1		T99	1
true	16441	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	56	1			T81	2		T337	2		T342	2
others[1]	64	1			T22	4		T79	2		T339	2
others[2]	54	1			T78	2		T81	2		T85	2
others[3]	68	1			T8	2		T161	2		T338	2
others[4]	44	1			T77	2		T207	2		T339	2
others[5]	68	1			T176	2		T358	2		T167	4
others[6]	76	1			T344	2		T336	4		T167	2
others[7]	92	1			T22	2		T308	2		T309	2
false	6861	1			T65	1		T98	1		T99	1
true	17886	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	68	1			T77	2		T292	2		T165	2
others[1]	76	1			T22	2		T176	2		T336	2
others[2]	68	1			T8	2		T81	2		T165	2
others[3]	70	1			T22	6		T309	2		T345	2
others[4]	56	1			T7	2		T22	2		T161	2
others[5]	58	1			T8	2		T338	2		T335	2
others[6]	64	1			T22	2		T309	4		T358	2
others[7]	108	1			T7	2		T8	2		T78	2
false	6861	1			T65	1		T98	1		T99	1
true	17886	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	44	1			T6	1		T91	1		T92	1
others[1]	36	1			T91	1		T108	1		T357	1
others[2]	39	1			T92	1		T249	1		T354	1
others[3]	37	1			T91	1		T108	1		T357	1
others[4]	43	1			T3	1		T12	1		T93	2
others[5]	31	1			T91	1		T92	2		T203	1
others[6]	44	1			T91	1		T92	2		T189	1
others[7]	47	1			T6	2		T8	2		T91	1
false	11690	1			T65	1		T98	1		T99	1
true	19105	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34	1			T162	2		T165	2		T167	2
others[1]	28	1			T163	2		T165	2		T349	2
others[2]	42	1			T348	2		T196	2		T347	4
others[3]	28	1			T81	2		T165	2		T349	2
others[4]	30	1			T166	2		T168	2		T360	2
others[5]	28	1			T169	2		T348	2		T350	2
others[6]	34	1			T350	2		T361	4		T362	2
others[7]	24	1			T161	2		T164	2		T167	2
false	10321	1			T65	1		T98	1		T99	1
true	16782	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	39	1			T6	2		T91	1		T92	2
others[1]	39	1			T108	2		T203	2		T249	1
others[2]	56	1			T6	1		T22	2		T91	1
others[3]	37	1			T6	1		T12	1		T189	1
others[4]	32	1			T108	1		T94	3		T352	2
others[5]	43	1			T77	2		T93	1		T344	2
others[6]	35	1			T108	1		T203	1		T357	1
others[7]	55	1			T3	1		T93	1		T108	1
false	14361	1			T65	1		T98	1		T99	1
true	2507	1			T105	1		T3	2		T5	5

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	48	1			T22	2		T161	2		T167	2
others[1]	36	1			T79	2		T176	2		T167	2
others[2]	70	1			T22	2		T81	2		T164	2
others[3]	86	1			T81	2		T339	2		T336	2
others[4]	74	1			T22	2		T344	2		T336	4
others[5]	90	1			T8	2		T77	2		T78	2
others[6]	70	1			T176	2		T308	2		T337	2
others[7]	48	1			T207	2		T309	2		T167	2
false	14295	1			T65	1		T98	1		T99	1
true	16995	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	68	1			T8	2		T22	2		T358	2
others[1]	78	1			T8	2		T22	2		T335	2
others[2]	70	1			T335	2		T346	2		T342	2
others[3]	64	1			T7	2		T22	2		T161	2
others[4]	60	1			T338	2		T336	2		T162	2
others[5]	74	1			T22	2		T78	2		T309	2
others[6]	68	1			T7	2		T77	2		T339	2
others[7]	86	1			T8	2		T22	4		T81	2
false	14295	1			T65	1		T98	1		T99	1
true	16976	1			T65	1		T98	1		T99	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	42	1			T12	1		T91	1		T92	1
others[1]	32	1			T92	1		T249	1		T354	1
others[2]	38	1			T8	2		T92	1		T189	1
others[3]	49	1			T6	1		T93	1		T108	1
others[4]	44	1			T91	2		T92	1		T108	1
others[5]	29	1			T92	1		T93	1		T108	3
others[6]	34	1			T6	1		T92	1		T250	1
others[7]	54	1			T3	1		T6	1		T91	3
false	14361	1			T65	1		T98	1		T99	1
true	2478	1			T105	1		T1	1		T3	2