Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 9077956 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 16588099 1 T65 54 T98 15 T99 27



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 7927055 1 T65 30 T98 19 T99 14
values[0x0] 6762978 1 T65 30 T98 8 T99 15
values[0x1] 10976022 1 T65 28 T98 11 T99 14



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4725180 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 20940875 1 T65 64 T98 17 T99 36



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 93829 1 T103 2 T187 10 T223 1
valid_sources[0x01] 95050 1 T102 4 T103 1 T104 3
valid_sources[0x02] 98170 1 T178 9 T103 2 T202 1
valid_sources[0x03] 104255 1 T100 1 T178 8 T103 1
valid_sources[0x04] 94466 1 T103 1 T104 1 T223 1
valid_sources[0x05] 96480 1 T104 3 T187 4 T223 6
valid_sources[0x06] 96002 1 T103 1 T223 4 T224 1
valid_sources[0x07] 95143 1 T178 9 T103 4 T233 1
valid_sources[0x08] 95381 1 T177 3 T103 2 T202 8
valid_sources[0x09] 98144 1 T103 1 T202 12 T233 2
valid_sources[0x0a] 97974 1 T103 1 T223 2 T222 7
valid_sources[0x0b] 95544 1 T177 1 T102 7 T202 4
valid_sources[0x0c] 96084 1 T100 2 T202 3 T233 1
valid_sources[0x0d] 98026 1 T98 3 T103 2 T187 2
valid_sources[0x0e] 95828 1 T99 1 T103 4 T187 1
valid_sources[0x0f] 95193 1 T65 4 T103 5 T187 10
valid_sources[0x10] 93622 1 T177 2 T103 2 T202 2
valid_sources[0x11] 126611 1 T103 2 T104 2 T202 2
valid_sources[0x12] 93332 1 T65 2 T103 1 T187 5
valid_sources[0x13] 98812 1 T187 11 T202 1 T223 5
valid_sources[0x14] 99489 1 T100 1 T178 7 T223 4
valid_sources[0x15] 93631 1 T104 1 T187 1 T223 1
valid_sources[0x16] 99011 1 T177 1 T100 1 T223 4
valid_sources[0x17] 95291 1 T103 2 T104 1 T202 2
valid_sources[0x18] 103558 1 T100 4 T103 2 T187 6
valid_sources[0x19] 98269 1 T98 1 T177 2 T100 2
valid_sources[0x1a] 103934 1 T99 1 T177 2 T223 4
valid_sources[0x1b] 97922 1 T100 1 T178 2 T103 4
valid_sources[0x1c] 95772 1 T202 10 T223 1 T224 1
valid_sources[0x1d] 97341 1 T99 1 T177 2 T103 1
valid_sources[0x1e] 97483 1 T102 3 T103 4 T187 3
valid_sources[0x1f] 100597 1 T103 4 T187 1 T223 4
valid_sources[0x20] 102420 1 T98 1 T177 4 T103 1
valid_sources[0x21] 96418 1 T177 1 T178 3 T103 1
valid_sources[0x22] 96167 1 T103 1 T104 1 T187 1
valid_sources[0x23] 98015 1 T177 1 T178 18 T103 2
valid_sources[0x24] 105990 1 T98 1 T177 1 T202 5
valid_sources[0x25] 97046 1 T103 2 T187 5 T202 6
valid_sources[0x26] 126309 1 T177 2 T103 3 T187 2
valid_sources[0x27] 98044 1 T98 1 T177 2 T103 2
valid_sources[0x28] 94790 1 T104 4 T187 3 T223 2
valid_sources[0x29] 102212 1 T103 1 T104 1 T223 4
valid_sources[0x2a] 96823 1 T177 1 T178 10 T103 2
valid_sources[0x2b] 96498 1 T177 3 T202 8 T223 2
valid_sources[0x2c] 99108 1 T178 1 T202 2 T223 4
valid_sources[0x2d] 96129 1 T99 3 T178 1 T187 1
valid_sources[0x2e] 96474 1 T65 1 T99 1 T177 1
valid_sources[0x2f] 96310 1 T178 2 T103 6 T202 2
valid_sources[0x30] 99375 1 T103 6 T223 1 T224 1
valid_sources[0x31] 96891 1 T98 1 T202 1 T224 1
valid_sources[0x32] 105082 1 T103 2 T180 3 T187 6
valid_sources[0x33] 95250 1 T177 1 T103 1 T104 1
valid_sources[0x34] 99463 1 T98 1 T99 1 T104 1
valid_sources[0x35] 99281 1 T103 1 T104 1 T187 5
valid_sources[0x36] 100245 1 T187 9 T222 3 T232 2
valid_sources[0x37] 96861 1 T99 1 T103 2 T187 9
valid_sources[0x38] 97447 1 T223 1 T224 5 T222 6
valid_sources[0x39] 98590 1 T177 2 T178 9 T103 4
valid_sources[0x3a] 96488 1 T103 4 T104 2 T223 1
valid_sources[0x3b] 96974 1 T102 4 T104 1 T202 1
valid_sources[0x3c] 103883 1 T177 2 T103 3 T104 1
valid_sources[0x3d] 102066 1 T65 1 T98 1 T100 1
valid_sources[0x3e] 94883 1 T65 1 T177 1 T102 2
valid_sources[0x3f] 98096 1 T65 1 T177 1 T103 9
valid_sources[0x40] 97368 1 T177 1 T100 1 T103 2
valid_sources[0x41] 95596 1 T177 1 T103 1 T223 2
valid_sources[0x42] 98512 1 T98 1 T103 1 T202 4
valid_sources[0x43] 95849 1 T178 2 T103 2 T187 16
valid_sources[0x44] 98497 1 T177 1 T104 3 T180 2
valid_sources[0x45] 97828 1 T100 1 T103 1 T233 1
valid_sources[0x46] 99916 1 T100 2 T178 4 T103 3
valid_sources[0x47] 95889 1 T103 3 T202 1 T224 1
valid_sources[0x48] 96704 1 T177 1 T103 1 T223 3
valid_sources[0x49] 95068 1 T177 1 T100 1 T103 3
valid_sources[0x4a] 98481 1 T98 1 T100 2 T103 3
valid_sources[0x4b] 106432 1 T178 16 T103 2 T224 1
valid_sources[0x4c] 101802 1 T177 1 T103 1 T223 2
valid_sources[0x4d] 94464 1 T177 1 T103 5 T187 1
valid_sources[0x4e] 119161 1 T65 1 T100 1 T103 1
valid_sources[0x4f] 151176 1 T177 1 T104 1 T187 6
valid_sources[0x50] 126120 1 T99 1 T178 3 T223 6
valid_sources[0x51] 146699 1 T177 2 T202 3 T223 1
valid_sources[0x52] 100129 1 T99 1 T103 1 T202 2
valid_sources[0x53] 95430 1 T178 7 T103 1 T104 3
valid_sources[0x54] 98174 1 T103 1 T104 2 T223 2
valid_sources[0x55] 105006 1 T103 2 T187 1 T202 5
valid_sources[0x56] 97974 1 T65 2 T100 2 T178 2
valid_sources[0x57] 96194 1 T177 1 T104 3 T223 3
valid_sources[0x58] 104249 1 T99 1 T177 1 T224 1
valid_sources[0x59] 95533 1 T100 1 T103 3 T233 1
valid_sources[0x5a] 104095 1 T102 2 T103 3 T187 2
valid_sources[0x5b] 125558 1 T103 1 T187 2 T202 1
valid_sources[0x5c] 95033 1 T65 1 T187 6 T202 2
valid_sources[0x5d] 94772 1 T65 2 T178 13 T103 2
valid_sources[0x5e] 95986 1 T177 1 T103 1 T202 1
valid_sources[0x5f] 101809 1 T177 2 T103 2 T104 1
valid_sources[0x60] 97907 1 T65 4 T177 1 T100 2
valid_sources[0x61] 101668 1 T177 1 T202 3 T223 1
valid_sources[0x62] 99509 1 T177 1 T103 3 T202 6
valid_sources[0x63] 105158 1 T65 7 T99 2 T177 2
valid_sources[0x64] 96218 1 T65 1 T103 1 T223 1
valid_sources[0x65] 103849 1 T177 1 T180 2 T187 2
valid_sources[0x66] 95775 1 T99 1 T178 4 T103 2
valid_sources[0x67] 92223 1 T177 1 T103 3 T104 1
valid_sources[0x68] 112625 1 T103 3 T202 2 T223 2
valid_sources[0x69] 97353 1 T65 4 T177 3 T104 2
valid_sources[0x6a] 95229 1 T177 1 T103 2 T202 4
valid_sources[0x6b] 97226 1 T98 1 T103 4 T187 9
valid_sources[0x6c] 96727 1 T178 9 T103 4 T202 17
valid_sources[0x6d] 98829 1 T99 3 T223 1 T222 6
valid_sources[0x6e] 147662 1 T100 2 T103 8 T187 1
valid_sources[0x6f] 95463 1 T65 1 T177 1 T100 1
valid_sources[0x70] 136861 1 T65 1 T100 1 T103 2
valid_sources[0x71] 99842 1 T65 1 T177 2 T103 2
valid_sources[0x72] 95620 1 T177 2 T103 2 T187 3
valid_sources[0x73] 101433 1 T177 1 T103 3 T233 1
valid_sources[0x74] 144783 1 T177 2 T100 1 T180 4
valid_sources[0x75] 110953 1 T177 3 T103 1 T202 2
valid_sources[0x76] 96565 1 T99 1 T103 4 T187 4
valid_sources[0x77] 95272 1 T99 2 T103 2 T202 3
valid_sources[0x78] 97777 1 T99 1 T177 1 T100 1
valid_sources[0x79] 94767 1 T177 1 T104 1 T202 3
valid_sources[0x7a] 92001 1 T98 1 T177 1 T223 1
valid_sources[0x7b] 108593 1 T99 1 T178 3 T103 4
valid_sources[0x7c] 96565 1 T65 2 T178 17 T103 1
valid_sources[0x7d] 94537 1 T99 1 T177 1 T178 21
valid_sources[0x7e] 95776 1 T103 4 T187 8 T223 6
valid_sources[0x7f] 96164 1 T177 1 T103 3 T104 1
valid_sources[0x80] 100867 1 T177 2 T223 3 T222 3



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 4551211 1 T65 7 T98 12 T99 4
values[0x0] all_enables biggest_size 6058455 1 T65 25 T98 2 T99 13
values[0x1] all_enables biggest_size 5978433 1 T65 22 T98 1 T99 10


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 839789 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 30978786 1 T65 19 T99 9 T177 268



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 7796329 1 T65 45 T99 14 T177 69
values[0x0] 11656579 1 T65 2 T99 3 T177 98
values[0x1] 12365667 1 T65 14 T99 5 T177 109



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 288849 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 31529726 1 T65 32 T99 11 T177 272



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 124855 1 T65 1 T177 1 T100 1
valid_sources[0x01] 122051 1 T177 2 T100 1 T103 2
valid_sources[0x02] 124436 1 T65 1 T177 1 T178 3
valid_sources[0x03] 124427 1 T177 1 T178 2 T187 1
valid_sources[0x04] 126426 1 T177 4 T103 1 T104 1
valid_sources[0x05] 128120 1 T177 1 T100 1 T178 2
valid_sources[0x06] 127564 1 T177 1 T178 2 T187 2
valid_sources[0x07] 124380 1 T65 1 T177 1 T202 1
valid_sources[0x08] 126976 1 T99 2 T177 1 T178 1
valid_sources[0x09] 122160 1 T65 1 T177 2 T103 1
valid_sources[0x0a] 125235 1 T103 2 T187 3 T223 1
valid_sources[0x0b] 122897 1 T177 2 T103 1 T104 1
valid_sources[0x0c] 122624 1 T103 3 T187 1 T202 1
valid_sources[0x0d] 122164 1 T65 2 T100 1 T178 3
valid_sources[0x0e] 127588 1 T65 1 T177 1 T178 3
valid_sources[0x0f] 119804 1 T177 3 T103 1 T187 3
valid_sources[0x10] 127491 1 T178 1 T187 3 T222 3
valid_sources[0x11] 126720 1 T177 1 T187 4 T202 1
valid_sources[0x12] 125184 1 T178 7 T103 3 T187 2
valid_sources[0x13] 127408 1 T177 4 T178 1 T103 1
valid_sources[0x14] 121958 1 T65 1 T177 7 T103 1
valid_sources[0x15] 125618 1 T177 4 T178 1 T202 1
valid_sources[0x16] 124014 1 T103 3 T187 1 T181 2
valid_sources[0x17] 120631 1 T103 2 T187 1 T202 1
valid_sources[0x18] 134179 1 T177 3 T103 1 T187 4
valid_sources[0x19] 123680 1 T178 1 T103 2 T104 1
valid_sources[0x1a] 128341 1 T177 1 T178 6 T103 1
valid_sources[0x1b] 125950 1 T65 2 T100 1 T104 1
valid_sources[0x1c] 124680 1 T177 4 T100 1 T103 1
valid_sources[0x1d] 125766 1 T103 1 T187 3 T222 9
valid_sources[0x1e] 122483 1 T178 2 T103 1 T104 1
valid_sources[0x1f] 124377 1 T65 1 T100 1 T178 4
valid_sources[0x20] 122067 1 T104 1 T187 1 T223 1
valid_sources[0x21] 120270 1 T202 4 T222 3 T181 1
valid_sources[0x22] 120933 1 T103 3 T222 4 T181 1
valid_sources[0x23] 122606 1 T99 3 T202 1 T179 1
valid_sources[0x24] 122415 1 T177 3 T100 1 T103 3
valid_sources[0x25] 125044 1 T187 1 T222 1 T181 1
valid_sources[0x26] 123526 1 T177 4 T100 1 T206 1
valid_sources[0x27] 126851 1 T100 1 T178 14 T187 1
valid_sources[0x28] 124873 1 T103 1 T187 3 T222 1
valid_sources[0x29] 125302 1 T177 2 T100 1 T187 1
valid_sources[0x2a] 127607 1 T177 2 T100 1 T103 2
valid_sources[0x2b] 123970 1 T65 1 T178 5 T103 1
valid_sources[0x2c] 123241 1 T177 8 T178 5 T103 1
valid_sources[0x2d] 124498 1 T103 2 T187 1 T202 4
valid_sources[0x2e] 120446 1 T177 1 T103 3 T187 2
valid_sources[0x2f] 124308 1 T103 1 T104 1 T181 1
valid_sources[0x30] 119487 1 T103 1 T104 1 T202 3
valid_sources[0x31] 122352 1 T178 5 T103 1 T187 1
valid_sources[0x32] 118382 1 T177 4 T100 1 T103 1
valid_sources[0x33] 118157 1 T177 2 T100 1 T103 1
valid_sources[0x34] 127015 1 T103 4 T187 4 T223 2
valid_sources[0x35] 126881 1 T177 2 T104 1 T187 1
valid_sources[0x36] 128484 1 T65 2 T177 5 T100 2
valid_sources[0x37] 123197 1 T100 1 T222 3 T181 1
valid_sources[0x38] 121930 1 T177 1 T178 3 T103 1
valid_sources[0x39] 122444 1 T177 4 T202 1 T222 3
valid_sources[0x3a] 127407 1 T177 2 T178 9 T103 1
valid_sources[0x3b] 125644 1 T177 5 T178 1 T103 1
valid_sources[0x3c] 122454 1 T178 9 T103 6 T187 1
valid_sources[0x3d] 124158 1 T65 2 T177 1 T103 2
valid_sources[0x3e] 127516 1 T65 1 T103 1 T187 1
valid_sources[0x3f] 122824 1 T177 1 T178 4 T187 3
valid_sources[0x40] 126274 1 T65 3 T177 1 T178 1
valid_sources[0x41] 127313 1 T65 1 T100 2 T103 1
valid_sources[0x42] 127183 1 T103 2 T187 3 T202 4
valid_sources[0x43] 121589 1 T177 1 T103 1 T104 1
valid_sources[0x44] 122055 1 T177 1 T222 2 T179 1
valid_sources[0x45] 122831 1 T177 1 T103 1 T104 1
valid_sources[0x46] 123180 1 T177 1 T100 1 T103 1
valid_sources[0x47] 121854 1 T103 2 T104 1 T187 2
valid_sources[0x48] 120855 1 T177 2 T103 2 T222 2
valid_sources[0x49] 118135 1 T177 1 T100 1 T178 3
valid_sources[0x4a] 123293 1 T100 1 T103 1 T187 1
valid_sources[0x4b] 126452 1 T177 4 T100 2 T178 3
valid_sources[0x4c] 124303 1 T177 1 T103 2 T104 2
valid_sources[0x4d] 122234 1 T177 1 T100 2 T103 2
valid_sources[0x4e] 121460 1 T177 1 T103 2 T202 2
valid_sources[0x4f] 129736 1 T177 1 T103 3 T104 1
valid_sources[0x50] 124044 1 T100 1 T103 1 T187 3
valid_sources[0x51] 125810 1 T104 1 T202 2 T222 3
valid_sources[0x52] 125001 1 T100 1 T178 4 T103 1
valid_sources[0x53] 122803 1 T177 1 T100 1 T103 1
valid_sources[0x54] 128050 1 T202 1 T223 1 T222 4
valid_sources[0x55] 120348 1 T177 1 T104 1 T187 1
valid_sources[0x56] 126791 1 T65 1 T177 1 T103 3
valid_sources[0x57] 119303 1 T178 4 T103 1 T104 1
valid_sources[0x58] 122371 1 T178 18 T103 1 T104 2
valid_sources[0x59] 125210 1 T103 1 T187 2 T202 2
valid_sources[0x5a] 121456 1 T65 1 T103 3 T202 2
valid_sources[0x5b] 123259 1 T178 5 T103 3 T187 4
valid_sources[0x5c] 124417 1 T177 3 T178 7 T103 6
valid_sources[0x5d] 123416 1 T65 1 T187 2 T223 2
valid_sources[0x5e] 130422 1 T177 3 T178 5 T187 4
valid_sources[0x5f] 123046 1 T100 1 T178 2 T103 3
valid_sources[0x60] 126060 1 T99 2 T177 1 T178 5
valid_sources[0x61] 123312 1 T65 1 T177 4 T100 1
valid_sources[0x62] 123071 1 T100 1 T103 1 T104 1
valid_sources[0x63] 126411 1 T104 1 T222 2 T181 1
valid_sources[0x64] 126164 1 T177 2 T103 1 T104 1
valid_sources[0x65] 122748 1 T223 1 T222 1 T181 1
valid_sources[0x66] 123121 1 T177 2 T104 4 T187 1
valid_sources[0x67] 126587 1 T178 2 T103 5 T187 2
valid_sources[0x68] 119460 1 T178 8 T187 1 T202 1
valid_sources[0x69] 116220 1 T103 1 T222 2 T181 1
valid_sources[0x6a] 124319 1 T65 1 T178 1 T103 3
valid_sources[0x6b] 124250 1 T177 6 T178 2 T103 1
valid_sources[0x6c] 124242 1 T103 1 T187 5 T202 1
valid_sources[0x6d] 125461 1 T178 4 T103 1 T187 1
valid_sources[0x6e] 122643 1 T177 1 T178 1 T103 1
valid_sources[0x6f] 121750 1 T177 1 T100 1 T103 3
valid_sources[0x70] 122595 1 T177 1 T178 8 T103 2
valid_sources[0x71] 118343 1 T177 1 T178 2 T103 1
valid_sources[0x72] 125258 1 T178 1 T104 1 T187 1
valid_sources[0x73] 127965 1 T65 1 T177 1 T178 8
valid_sources[0x74] 124437 1 T177 1 T103 1 T187 2
valid_sources[0x75] 121846 1 T177 2 T223 1 T222 4
valid_sources[0x76] 123582 1 T103 5 T187 1 T223 1
valid_sources[0x77] 121078 1 T177 1 T103 1 T224 3
valid_sources[0x78] 119618 1 T177 1 T178 2 T103 1
valid_sources[0x79] 125086 1 T65 1 T177 3 T187 2
valid_sources[0x7a] 127036 1 T65 1 T177 1 T178 6
valid_sources[0x7b] 130616 1 T65 1 T103 1 T223 2
valid_sources[0x7c] 126587 1 T103 2 T104 1 T187 2
valid_sources[0x7d] 123961 1 T103 2 T104 1 T187 1
valid_sources[0x7e] 124897 1 T65 1 T100 1 T178 3
valid_sources[0x7f] 124491 1 T178 2 T223 1 T222 8
valid_sources[0x80] 125990 1 T65 2 T178 1 T103 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7782320 1 T65 6 T99 5 T177 69
values[0x0] all_enables biggest_size 11598615 1 T99 1 T177 97 T100 7
values[0x1] all_enables biggest_size 11597851 1 T65 13 T99 3 T177 102

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%