Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

68295115

1

T65

34

T98

23

T99

16

full_word

20442507

1

T65

54

T98

15

T99

27

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	88737302	1			T65	88		T98	38		T99	43
auto[TlIntgErrCmd]	103	1			T103	5		T187	2		T201	7
auto[TlIntgErrData]	114	1			T103	1		T187	2		T201	6
auto[TlIntgErrBoth]	103	1			T103	4		T187	6		T201	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12550297

1

T65

30

T98

19

T99

14

auto[1]

76187325

1

T65

58

T98

19

T99

29

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7530687	1			T65	23		T98	7		T99	10
auto[TlIntgErrNone]	partial	auto[1]	60764128	1			T65	11		T98	16		T99	6
auto[TlIntgErrNone]	full_word	auto[0]	5019466	1			T65	7		T98	12		T99	4
auto[TlIntgErrNone]	full_word	auto[1]	15423021	1			T65	47		T98	3		T99	23
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T103	1		T187	1		T201	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T103	3		T201	3		T229	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T103	1		T201	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T187	1		T230	1		T316	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T187	1		T201	1		T229	1
auto[TlIntgErrData]	partial	auto[1]	56	1			T103	1		T187	1		T201	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T229	1		T312	2		T317	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T312	1		T230	1		T318	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T103	4		T187	3		T201	3
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T187	3		T201	4		T229	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T312	1		T316	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T257	1		T319	1		-	-