Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.75	96.48	88.57	96.71		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	21852328	0	0
check_regwen_rd_A	2147483647	5603	0	0
check_timeout_rd_A	2147483647	5280	0	0
check_trigger_regwen_rd_A	2147483647	5618	0	0
consistency_check_period_rd_A	2147483647	6136	0	0
creator_sw_cfg_read_lock_rd_A	2147483647	5412	0	0
direct_access_address_rd_A	2147483647	5004	0	0
direct_access_wdata_0_rd_A	2147483647	3591	0	0
direct_access_wdata_1_rd_A	2147483647	3730	0	0
integrity_check_period_rd_A	2147483647	5591	0	0
intr_enable_rd_A	2147483647	6549	0	0
owner_sw_cfg_read_lock_rd_A	2147483647	4624	0	0
vendor_test_read_lock_rd_A	2147483647	4730	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21852328	0	0
T100	3399	0	0	0
T101	4052	0	0	0
T102	3561	0	0	0
T103	61354	6	0	0
T104	7940	39	0	0
T177	7157	90	0	0
T178	6337	449	0	0
T179	0	134	0	0
T180	3231	0	0	0
T181	0	172	0	0
T182	0	38	0	0
T183	0	313	0	0
T184	0	288	0	0
T187	58226	1	0	0
T188	3371	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5603	0	0
T65	4416	7	0	0
T98	3294	0	0	0
T99	3382	0	0	0
T100	3399	0	0	0
T101	4052	0	0	0
T102	3561	0	0	0
T103	61354	0	0	0
T104	7940	0	0	0
T177	7157	0	0	0
T178	6337	0	0	0
T222	0	150	0	0
T229	0	26	0	0
T231	0	8	0	0
T232	0	138	0	0
T240	0	1	0	0
T245	0	1	0	0
T252	0	5	0	0
T273	0	437	0	0
T274	0	5	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5280	0	0
T3	0	46	0	0
T179	4442	0	0	0
T181	7308	0	0	0
T182	6591	0	0	0
T183	5772	0	0	0
T184	14521	0	0	0
T206	10892	0	0	0
T222	11583	153	0	0
T232	7647	174	0	0
T246	0	135	0	0
T252	0	14	0	0
T274	0	10	0	0
T275	0	4	0	0
T276	0	8	0	0
T277	0	57	0	0
T278	0	6	0	0
T279	3184	0	0	0
T280	3384	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5618	0	0
T65	4416	2	0	0
T98	3294	0	0	0
T99	3382	0	0	0
T100	3399	0	0	0
T101	4052	0	0	0
T102	3561	0	0	0
T103	61354	0	0	0
T104	7940	0	0	0
T177	7157	0	0	0
T178	6337	0	0	0
T222	0	125	0	0
T229	0	36	0	0
T231	0	19	0	0
T232	0	135	0	0
T240	0	9	0	0
T245	0	8	0	0
T252	0	5	0	0
T273	0	424	0	0
T274	0	13	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6136	0	0
T65	4416	8	0	0
T98	3294	0	0	0
T99	3382	0	0	0
T100	3399	0	0	0
T101	4052	0	0	0
T102	3561	0	0	0
T103	61354	0	0	0
T104	7940	0	0	0
T177	7157	0	0	0
T178	6337	0	0	0
T222	0	142	0	0
T229	0	38	0	0
T231	0	13	0	0
T232	0	142	0	0
T240	0	3	0	0
T245	0	3	0	0
T252	0	8	0	0
T273	0	428	0	0
T274	0	21	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5412	0	0
T3	0	74	0	0
T179	4442	0	0	0
T181	7308	0	0	0
T182	6591	0	0	0
T183	5772	0	0	0
T184	14521	0	0	0
T206	10892	0	0	0
T222	11583	164	0	0
T232	7647	114	0	0
T246	0	120	0	0
T252	0	6	0	0
T274	0	6	0	0
T275	0	3	0	0
T276	0	14	0	0
T277	0	35	0	0
T279	3184	0	0	0
T280	3384	0	0	0
T281	0	1	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5004	0	0
T3	0	33	0	0
T12	0	16	0	0
T91	0	216	0	0
T92	0	213	0	0
T225	9118	0	0	0
T239	4041	0	0	0
T240	3558	0	0	0
T241	8031	0	0	0
T242	3132	0	0	0
T252	9350	12	0	0
T274	9219	6	0	0
T275	0	5	0	0
T276	0	4	0	0
T278	0	3	0	0
T281	0	9	0	0
T282	3443	0	0	0
T283	3910	0	0	0
T284	4159	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3591	0	0
T3	136195	66	0	0
T5	50743	0	0	0
T6	214712	0	0	0
T7	88313	0	0	0
T8	409213	0	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T12	0	17	0	0
T22	826480	0	0	0
T72	14451	0	0	0
T91	0	177	0	0
T92	0	164	0	0
T93	0	35	0	0
T108	0	167	0	0
T203	0	78	0	0
T262	0	111	0	0
T263	0	101	0	0
T285	0	26	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3730	0	0
T3	136195	12	0	0
T5	50743	0	0	0
T6	214712	0	0	0
T7	88313	0	0	0
T8	409213	0	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T12	0	14	0	0
T22	826480	0	0	0
T72	14451	0	0	0
T91	0	164	0	0
T92	0	138	0	0
T93	0	42	0	0
T108	0	152	0	0
T203	0	90	0	0
T262	0	101	0	0
T263	0	84	0	0
T285	0	32	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5591	0	0
T65	4416	7	0	0
T98	3294	0	0	0
T99	3382	0	0	0
T100	3399	0	0	0
T101	4052	0	0	0
T102	3561	0	0	0
T103	61354	0	0	0
T104	7940	0	0	0
T177	7157	0	0	0
T178	6337	0	0	0
T222	0	146	0	0
T229	0	49	0	0
T231	0	25	0	0
T232	0	101	0	0
T240	0	1	0	0
T245	0	8	0	0
T252	0	10	0	0
T273	0	437	0	0
T274	0	12	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6549	0	0
T65	4416	15	0	0
T98	3294	0	0	0
T99	3382	0	0	0
T100	3399	0	0	0
T101	4052	9	0	0
T102	3561	25	0	0
T103	61354	0	0	0
T104	7940	0	0	0
T177	7157	0	0	0
T178	6337	0	0	0
T222	0	154	0	0
T229	0	57	0	0
T232	0	119	0	0
T272	0	27	0	0
T273	0	428	0	0
T274	0	28	0	0
T286	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4624	0	0
T3	0	33	0	0
T12	0	28	0	0
T179	4442	0	0	0
T181	7308	0	0	0
T182	6591	0	0	0
T183	5772	0	0	0
T184	14521	0	0	0
T206	10892	0	0	0
T222	11583	178	0	0
T232	7647	103	0	0
T246	0	127	0	0
T252	0	12	0	0
T274	0	11	0	0
T276	0	5	0	0
T277	0	41	0	0
T278	0	2	0	0
T279	3184	0	0	0
T280	3384	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4730	0	0
T3	0	32	0	0
T179	4442	0	0	0
T181	7308	0	0	0
T182	6591	0	0	0
T183	5772	0	0	0
T184	14521	0	0	0
T206	10892	0	0	0
T222	11583	140	0	0
T232	7647	123	0	0
T246	0	123	0	0
T252	0	10	0	0
T274	0	8	0	0
T275	0	3	0	0
T276	0	3	0	0
T277	0	22	0	0
T278	0	8	0	0
T279	3184	0	0	0
T280	3384	0	0	0