Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.06	98.11	97.78		66.67	97.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	94.00	97.62	95.56		87.50	93.18	96.15
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.00	97.62	95.56		87.50	93.18	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.22	98.44	95.74	97.87	87.50	94.64	97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.75	96.48	88.57	96.71		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.75	96.48	88.57	96.71		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.75	96.48	88.57	96.71		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
94.00	97.62

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	83	94.32
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	62	92.54
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
94.00	95.56

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T72,T17,T111

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T72,T17,T111

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T72,T17,T111

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T72,T16

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T5
1	0	Covered	T12,T106,T107

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T2,T3,T5
-	1	Covered	T12,T106,T107

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T12,T106,T107

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T12,T36,T19

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T112,T113,T114
1	Covered	T112,T113,T114

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T2,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T72

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T72

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 + Info=226594821,DigestOffset=1656,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T72,T75,T115
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T9,T16

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T90,T116,T106
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T90,T36

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T117,T112,T118
1	Covered	T117,T112,T118

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T65
IdleSt	199	Covered	T65
InitSt	175	Covered	T65
InitWaitSt	185	Covered	T65
ReadSt	221	Covered	T65
ReadWaitSt	239	Covered	T65
ResetSt	173	Covered	T65

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T65
IdleSt->ReadSt	221	Covered	T65
InitSt->ErrorSt	309	Covered	T65
InitSt->InitWaitSt	185	Covered	T65
InitWaitSt->ErrorSt	209	Covered	T65
InitWaitSt->IdleSt	199	Covered	T65
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T65
ReadSt->ReadWaitSt	239	Covered	T65
ReadWaitSt->ErrorSt	270	Covered	T65
ReadWaitSt->IdleSt	260	Covered	T65
ResetSt->ErrorSt	309	Covered	T65
ResetSt->InitSt	175	Covered	T65

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T65
CheckFailError	311	Covered	T65
FsmStateError	283	Covered	T65
MacroEccCorrError	206	Covered	T65
NoError	220	Covered	T65

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	311	Not Covered
AccessError->FsmStateError	319	Covered	T65
AccessError->MacroEccCorrError	206	Not Covered
AccessError->NoError	220	Covered	T65
CheckFailError->AccessError	243	Not Covered
CheckFailError->FsmStateError	319	Not Covered
CheckFailError->MacroEccCorrError	206	Not Covered
CheckFailError->NoError	220	Covered	T65
FsmStateError->AccessError	243	Not Covered
FsmStateError->CheckFailError	311	Not Covered
FsmStateError->MacroEccCorrError	206	Not Covered
FsmStateError->NoError	220	Covered	T65
MacroEccCorrError->AccessError	243	Not Covered
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T65
MacroEccCorrError->NoError	220	Covered	T65
NoError->AccessError	243	Covered	T65
NoError->CheckFailError	311	Covered	T65
NoError->FsmStateError	283	Covered	T65
NoError->MacroEccCorrError	206	Covered	T65

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T9,T16,T115
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T72,T75,T119
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T22,T76
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T90,T19,T116
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T116,T120,T121
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T117,T112,T118
1	0	Covered	T117,T112,T118
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T17
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T115,T122,T123
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T5
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T22,T76
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T78,T36,T80
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T90,T106,T107
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T8,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T8,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T117,T113,T114
1	0	Covered	T117,T113,T114
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
94.00	93.18

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T72
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T9,T72,T16
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T5
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T22,T76
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T12,T36,T19
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T112,T113,T114
1	0	Covered	T112,T113,T114
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	3480	3480	0	0
EccErrorState_A	2147483647	72112	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	1285350679	0	0
InitWriteLocksPartition_A	2147483647	1285350679	0	0
OffsetMustBeBlockAligned_A	3480	3480	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	131	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	2147483647	0	0
SizeMustBeBlockAligned_A	3480	3480	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	33025	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	4014556	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	55598102	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3480	3480	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	72112	0	0
T41	66236	0	0	0
T112	18784	4158	0	0
T113	13991	7920	0	0
T114	0	5350	0	0
T117	32876	7142	0	0
T118	0	3599	0	0
T124	0	5918	0	0
T125	0	4282	0	0
T126	0	4366	0	0
T127	0	7982	0	0
T128	0	2234	0	0
T129	0	5836	0	0
T130	0	7142	0	0
T131	0	6183	0	0
T132	326098	0	0	0
T133	34674	0	0	0
T134	198452	0	0	0
T135	25194	0	0	0
T136	69066	0	0	0
T137	299618	0	0	0
T138	1797988	0	0	0
T139	16141	0	0	0
T140	11151	0	0	0
T141	193082	0	0	0
T142	11650	0	0	0
T143	13149	0	0	0
T144	219534	0	0	0
T145	7280	0	0	0
T146	8294	0	0	0
T147	15128	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1285350679	0	0
T1	54387	17967	0	0
T2	43755	9372	0	0
T3	408585	2981373	0	0
T5	152229	1878	0	0
T6	644136	31722	0	0
T7	264939	63327	0	0
T8	1227639	119334	0	0
T9	31623	11910	0	0
T10	279597	7053	0	0
T11	70305	36456	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1285350679	0	0
T1	54387	17967	0	0
T2	43755	9372	0	0
T3	408585	2981373	0	0
T5	152229	1878	0	0
T6	644136	31722	0	0
T7	264939	63327	0	0
T8	1227639	119334	0	0
T9	31623	11910	0	0
T10	279597	7053	0	0
T11	70305	36456	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3480	3480	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	131	0	0
T12	119261	0	0	0
T16	15364	0	0	0
T22	826480	0	0	0
T36	46428	0	0	0
T55	15629	0	0	0
T72	14451	1	0	0
T73	6865	0	0	0
T74	10851	0	0	0
T75	12534	1	0	0
T76	41364	0	0	0
T79	36336	0	0	0
T88	23447	0	0	0
T89	25857	0	0	0
T90	25038	1	0	0
T106	0	1	0	0
T107	0	2	0	0
T110	34466	0	0	0
T111	0	1	0	0
T115	12347	1	0	0
T116	0	1	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	20057	0	0	0
T158	11013	0	0	0
T159	15495	0	0	0
T160	25254	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	36258	646	0	0
T2	29170	0	0	0
T3	408585	310823	0	0
T5	152229	22116	0	0
T6	644136	374206	0	0
T7	264939	23128	0	0
T8	1227639	51295	0	0
T9	31623	0	0	0
T10	279597	0	0	0
T11	70305	25511	0	0
T12	0	2448941	0	0
T22	826480	593626	0	0
T72	14451	0	0	0
T76	0	4634	0	0
T77	0	19418	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3480	3480	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T11	3	3	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33025	0	0
T1	36258	6	0	0
T2	29170	0	0	0
T3	408585	48	0	0
T5	152229	17	0	0
T6	644136	115	0	0
T7	264939	6	0	0
T8	1227639	134	0	0
T9	31623	0	0	0
T10	279597	2	0	0
T11	70305	23	0	0
T12	0	58	0	0
T22	826480	354	0	0
T72	14451	0	0	0
T73	0	13	0	0
T74	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4014556	0	0
T5	101486	12395	0	0
T6	429424	0	0	0
T7	176626	9543	0	0
T8	818426	21971	0	0
T9	21082	0	0	0
T10	186398	0	0	0
T11	46870	0	0	0
T19	47465	2489	0	0
T22	1652960	78288	0	0
T55	31258	0	0	0
T56	14902	0	0	0
T72	28902	0	0	0
T76	0	4224	0	0
T77	0	15774	0	0
T79	0	16149	0	0
T80	0	2675	0	0
T81	555471	50965	0	0
T82	42731	0	0	0
T90	0	5373	0	0
T111	16168	0	0	0
T160	0	3342	0	0
T161	0	716	0	0
T162	0	2871	0	0
T163	0	1673	0	0
T164	0	3262	0	0
T165	0	5491	0	0
T166	0	2796	0	0
T167	0	5957	0	0
T168	0	74095	0	0
T169	0	1883	0	0
T170	4800	0	0	0
T171	25023	0	0	0
T172	19273	0	0	0
T173	11245	0	0	0
T174	22457	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	55598102	0	0
T5	152229	93156	0	0
T6	644136	0	0	0
T7	264939	121655	0	0
T8	1227639	417420	0	0
T9	31623	0	0	0
T10	279597	0	0	0
T11	70305	0	0	0
T13	0	2833	0	0
T17	0	2496	0	0
T22	2479440	1183334	0	0
T55	46887	0	0	0
T72	43353	4577	0	0
T75	0	2429	0	0
T76	0	70186	0	0
T77	0	188618	0	0
T78	0	64037	0	0
T81	0	48233	0	0
T82	0	33181	0	0
T89	0	7470	0	0
T90	0	14181	0	0
T111	0	3927	0	0
T175	0	2462	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	54387	53472	0	0
T2	43755	42885	0	0
T3	408585	408579	0	0
T5	152229	149850	0	0
T6	644136	644130	0	0
T7	264939	260895	0	0
T8	1227639	1208010	0	0
T9	31623	30858	0	0
T10	279597	278850	0	0
T11	70305	69534	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		84	82	97.62
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	63	61	96.83
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270		excluded
			Exclude Annotation: VC_COV_UNR
271		excluded
			Exclude Annotation: VC_COV_UNR
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T72,T17,T111

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T72,T17,T111

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T72,T17,T111

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T72,T16

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T2,T3,T5
1	0	Covered	T12,T106,T107

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T2,T3,T5
-	1	Covered	T12,T106,T107

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T12,T106,T107

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T12,T36,T19

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T112,T113,T114
1	Covered	T112,T113,T114

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T2,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T72

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T72

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	11	84.62
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T65
IdleSt	199	Covered	T65
InitSt	175	Covered	T65
InitWaitSt	185	Covered	T65
ReadSt	221	Covered	T65
ReadWaitSt	239	Covered	T65
ResetSt	173	Covered	T65

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T65
IdleSt->ReadSt	221	Covered	T65
InitSt->ErrorSt	309	Covered	T65
InitSt->InitWaitSt	185	Covered	T65
InitWaitSt->ErrorSt	209	Covered	T65
InitWaitSt->IdleSt	199	Covered	T65
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T65
ReadSt->ReadWaitSt	239	Covered	T65
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T65
ResetSt->ErrorSt	309	Covered	T65
ResetSt->InitSt	175	Covered	T65

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T65
CheckFailError	311	Covered	T65
FsmStateError	283	Covered	T65
MacroEccCorrError	206	Covered	T65
NoError	220	Covered	T65

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T65
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T65
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T65
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T65
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T65
MacroEccCorrError->NoError	220	Covered	T65
NoError->AccessError	243	Covered	T65
NoError->CheckFailError	311	Covered	T65
NoError->FsmStateError	283	Covered	T65
NoError->MacroEccCorrError	206	Covered	T65

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T72
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T9,T72,T16
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T5
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T22,T76
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T12,T36,T19
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T112,T113,T114
1	0	Covered	T112,T113,T114
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	1160	1160	0	0
EccErrorState_A	2147483647	19935	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	428267293	0	0
InitWriteLocksPartition_A	2147483647	428267293	0	0
OffsetMustBeBlockAligned_A	1160	1160	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	0	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	1125188808	0	0
SizeMustBeBlockAligned_A	1160	1160	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	10789	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	655283	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	8198330	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19935	0	0
T41	33118	0	0	0
T112	9392	2079	0	0
T113	0	2640	0	0
T114	0	2675	0	0
T127	0	3991	0	0
T129	0	2918	0	0
T130	0	3571	0	0
T131	0	2061	0	0
T137	149809	0	0	0
T138	898994	0	0	0
T139	16141	0	0	0
T140	11151	0	0	0
T141	193082	0	0	0
T142	11650	0	0	0
T143	13149	0	0	0
T144	219534	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428267293	0	0
T1	18129	5921	0	0
T2	14585	3073	0	0
T3	136195	993781	0	0
T5	50743	490	0	0
T6	214712	10438	0	0
T7	88313	20871	0	0
T8	409213	38401	0	0
T9	10541	3919	0	0
T10	93199	2300	0	0
T11	23435	12084	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428267293	0	0
T1	18129	5921	0	0
T2	14585	3073	0	0
T3	136195	993781	0	0
T5	50743	490	0	0
T6	214712	10438	0	0
T7	88313	20871	0	0
T8	409213	38401	0	0
T9	10541	3919	0	0
T10	93199	2300	0	0
T11	23435	12084	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1125188808	0	0
T1	18129	324	0	0
T2	14585	0	0	0
T3	136195	103624	0	0
T5	50743	6925	0	0
T6	214712	114394	0	0
T7	88313	8946	0	0
T8	409213	17110	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	13119	0	0
T12	0	785222	0	0
T22	0	202652	0	0
T76	0	2019	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10789	0	0
T1	18129	4	0	0
T2	14585	0	0	0
T3	136195	16	0	0
T5	50743	2	0	0
T6	214712	36	0	0
T7	88313	1	0	0
T8	409213	46	0	0
T9	10541	0	0	0
T10	93199	1	0	0
T11	23435	9	0	0
T22	0	142	0	0
T73	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	655283	0	0
T19	47465	0	0	0
T56	14902	0	0	0
T81	555471	8340	0	0
T82	42731	0	0	0
T111	16168	0	0	0
T161	0	716	0	0
T162	0	2871	0	0
T163	0	1673	0	0
T164	0	3262	0	0
T165	0	5491	0	0
T166	0	2796	0	0
T167	0	5957	0	0
T168	0	74095	0	0
T169	0	1883	0	0
T170	4800	0	0	0
T171	25023	0	0	0
T172	19273	0	0	0
T173	11245	0	0	0
T174	22457	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8198330	0	0
T5	50743	12810	0	0
T6	214712	0	0	0
T7	88313	0	0	0
T8	409213	22713	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T13	0	2833	0	0
T17	0	2496	0	0
T22	826480	199584	0	0
T55	15629	0	0	0
T72	14451	2291	0	0
T81	0	48233	0	0
T82	0	33181	0	0
T89	0	2507	0	0
T111	0	3927	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T72,T75,T119
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T16,T115

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T116,T120,T121
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T90,T19,T116

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T117,T112,T118
1	Covered	T117,T112,T118

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T65
IdleSt	199	Covered	T65
InitSt	175	Covered	T65
InitWaitSt	185	Covered	T65
ReadSt	221	Covered	T65
ReadWaitSt	239	Covered	T65
ResetSt	173	Covered	T65

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T65
IdleSt->ReadSt	221	Covered	T65
InitSt->ErrorSt	309	Covered	T65
InitSt->InitWaitSt	185	Covered	T65
InitWaitSt->ErrorSt	209	Covered	T65
InitWaitSt->IdleSt	199	Covered	T65
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T65
ReadSt->ReadWaitSt	239	Covered	T65
ReadWaitSt->ErrorSt	270	Covered	T65
ReadWaitSt->IdleSt	260	Covered	T65
ResetSt->ErrorSt	309	Covered	T65
ResetSt->InitSt	175	Covered	T65

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T65
CheckFailError	311	Covered	T65
FsmStateError	283	Covered	T65
MacroEccCorrError	206	Covered	T65
NoError	220	Covered	T65

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T65
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T65
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T65
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T65
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T65
MacroEccCorrError->NoError	220	Covered	T65
NoError->AccessError	243	Covered	T65
NoError->CheckFailError	311	Covered	T65
NoError->FsmStateError	283	Covered	T65
NoError->MacroEccCorrError	206	Covered	T65

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T9,T16,T115
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T72,T75,T119
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T22,T76
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T90,T19,T116
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T3
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T116,T120,T121
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T6,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T117,T112,T118
1	0	Covered	T117,T112,T118
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	1160	1160	0	0
EccErrorState_A	2147483647	28795	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	428450628	0	0
InitWriteLocksPartition_A	2147483647	428450628	0	0
OffsetMustBeBlockAligned_A	1160	1160	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	73	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	1170821532	0	0
SizeMustBeBlockAligned_A	1160	1160	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	11144	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	1758542	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	24497562	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	28795	0	0
T41	33118	0	0	0
T112	9392	2079	0	0
T113	0	2640	0	0
T117	16438	3571	0	0
T118	0	3599	0	0
T124	0	2959	0	0
T125	0	2141	0	0
T126	0	2183	0	0
T127	0	3991	0	0
T130	0	3571	0	0
T131	0	2061	0	0
T132	163049	0	0	0
T133	17337	0	0	0
T134	99226	0	0	0
T135	12597	0	0	0
T136	34533	0	0	0
T137	149809	0	0	0
T138	898994	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428450628	0	0
T1	18129	5989	0	0
T2	14585	3124	0	0
T3	136195	993791	0	0
T5	50743	626	0	0
T6	214712	10574	0	0
T7	88313	21109	0	0
T8	409213	39778	0	0
T9	10541	3970	0	0
T10	93199	2351	0	0
T11	23435	12152	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428450628	0	0
T1	18129	5989	0	0
T2	14585	3124	0	0
T3	136195	993791	0	0
T5	50743	626	0	0
T6	214712	10574	0	0
T7	88313	21109	0	0
T8	409213	39778	0	0
T9	10541	3970	0	0
T10	93199	2351	0	0
T11	23435	12152	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	73	0	0
T12	119261	0	0	0
T22	826480	0	0	0
T55	15629	0	0	0
T72	14451	1	0	0
T73	6865	0	0	0
T74	10851	0	0	0
T75	12534	1	0	0
T76	41364	0	0	0
T88	23447	0	0	0
T89	25857	0	0	0
T111	0	1	0	0
T116	0	1	0	0
T119	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0
T155	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1170821532	0	0
T1	18129	322	0	0
T2	14585	0	0	0
T3	136195	103594	0	0
T5	50743	5376	0	0
T6	214712	114325	0	0
T7	88313	5785	0	0
T8	409213	15804	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T12	0	878355	0	0
T22	0	193610	0	0
T76	0	1919	0	0
T77	0	13712	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11144	0	0
T1	18129	2	0	0
T2	14585	0	0	0
T3	136195	15	0	0
T5	50743	4	0	0
T6	214712	48	0	0
T7	88313	2	0	0
T8	409213	40	0	0
T9	10541	0	0	0
T10	93199	1	0	0
T11	23435	6	0	0
T22	0	105	0	0
T73	0	8	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1758542	0	0
T5	50743	8085	0	0
T6	214712	0	0	0
T7	88313	9543	0	0
T8	409213	11035	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T22	826480	39741	0	0
T55	15629	0	0	0
T72	14451	0	0	0
T76	0	4224	0	0
T77	0	6684	0	0
T79	0	5229	0	0
T81	0	24279	0	0
T90	0	5373	0	0
T160	0	3342	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24497562	0	0
T5	50743	40224	0	0
T6	214712	0	0	0
T7	88313	60938	0	0
T8	409213	222267	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T22	826480	498932	0	0
T55	15629	0	0	0
T72	14451	2286	0	0
T75	0	2429	0	0
T76	0	35144	0	0
T77	0	94428	0	0
T78	0	32061	0	0
T89	0	2490	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T115,T122,T123
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T16,T17

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T90,T106,T107
0	1	Covered	T2,T3,T5
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T78,T36,T80

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T30,T31

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T117,T113,T114
1	Covered	T117,T113,T114

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T2,T3,T5

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T65
IdleSt	199	Covered	T65
InitSt	175	Covered	T65
InitWaitSt	185	Covered	T65
ReadSt	221	Covered	T65
ReadWaitSt	239	Covered	T65
ResetSt	173	Covered	T65

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T65
IdleSt->ReadSt	221	Covered	T65
InitSt->ErrorSt	309	Covered	T65
InitSt->InitWaitSt	185	Covered	T65
InitWaitSt->ErrorSt	209	Covered	T65
InitWaitSt->IdleSt	199	Covered	T65
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T65
ReadSt->ReadWaitSt	239	Covered	T65
ReadWaitSt->ErrorSt	270	Covered	T65
ReadWaitSt->IdleSt	260	Covered	T65
ResetSt->ErrorSt	309	Covered	T65
ResetSt->InitSt	175	Covered	T65

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T65
CheckFailError	311	Covered	T65
FsmStateError	283	Covered	T65
MacroEccCorrError	206	Covered	T65
NoError	220	Covered	T65

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T65
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T65
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T65
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T65
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T65
MacroEccCorrError->NoError	220	Covered	T65
NoError->AccessError	243	Covered	T65
NoError->CheckFailError	311	Covered	T65
NoError->FsmStateError	283	Covered	T65
NoError->MacroEccCorrError	206	Covered	T65

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T16,T17
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T115,T122,T123
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T2,T3,T5
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T8,T22,T76
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T78,T36,T80
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T2,T3,T5
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T90,T106,T107
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T5
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T31
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T6,T8,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T6,T8,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T117,T113,T114
1	0	Covered	T117,T113,T114
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	1160	1160	0	0
EccErrorState_A	2147483647	23382	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	428632758	0	0
InitWriteLocksPartition_A	2147483647	428632758	0	0
OffsetMustBeBlockAligned_A	1160	1160	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	58	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	1176415358	0	0
SizeMustBeBlockAligned_A	1160	1160	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	11092	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	1600731	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	22902210	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23382	0	0
T113	13991	2640	0	0
T114	0	2675	0	0
T117	16438	3571	0	0
T124	0	2959	0	0
T125	0	2141	0	0
T126	0	2183	0	0
T128	0	2234	0	0
T129	0	2918	0	0
T131	0	2061	0	0
T132	163049	0	0	0
T133	17337	0	0	0
T134	99226	0	0	0
T135	12597	0	0	0
T136	34533	0	0	0
T145	7280	0	0	0
T146	8294	0	0	0
T147	15128	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428632758	0	0
T1	18129	6057	0	0
T2	14585	3175	0	0
T3	136195	993801	0	0
T5	50743	762	0	0
T6	214712	10710	0	0
T7	88313	21347	0	0
T8	409213	41155	0	0
T9	10541	4021	0	0
T10	93199	2402	0	0
T11	23435	12220	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	428632758	0	0
T1	18129	6057	0	0
T2	14585	3175	0	0
T3	136195	993801	0	0
T5	50743	762	0	0
T6	214712	10710	0	0
T7	88313	21347	0	0
T8	409213	41155	0	0
T9	10541	4021	0	0
T10	93199	2402	0	0
T11	23435	12220	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	58	0	0
T16	15364	0	0	0
T36	46428	0	0	0
T79	36336	0	0	0
T90	25038	1	0	0
T106	0	1	0	0
T107	0	2	0	0
T110	34466	0	0	0
T115	12347	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T157	20057	0	0	0
T158	11013	0	0	0
T159	15495	0	0	0
T160	25254	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1176415358	0	0
T3	136195	103605	0	0
T5	50743	9815	0	0
T6	214712	145487	0	0
T7	88313	8397	0	0
T8	409213	18381	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	12392	0	0
T12	0	785364	0	0
T22	826480	197364	0	0
T72	14451	0	0	0
T76	0	696	0	0
T77	0	5706	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11092	0	0
T3	136195	17	0	0
T5	50743	11	0	0
T6	214712	31	0	0
T7	88313	3	0	0
T8	409213	48	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	8	0	0
T12	0	58	0	0
T22	826480	107	0	0
T72	14451	0	0	0
T73	0	2	0	0
T74	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1600731	0	0
T5	50743	4310	0	0
T6	214712	0	0	0
T7	88313	0	0	0
T8	409213	10936	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T19	0	2489	0	0
T22	826480	38547	0	0
T55	15629	0	0	0
T72	14451	0	0	0
T77	0	9090	0	0
T79	0	10920	0	0
T80	0	2675	0	0
T81	0	18346	0	0
T85	0	2030	0	0
T176	0	694	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22902210	0	0
T5	50743	40122	0	0
T6	214712	0	0	0
T7	88313	60717	0	0
T8	409213	172440	0	0
T9	10541	0	0	0
T10	93199	0	0	0
T11	23435	0	0	0
T22	826480	484818	0	0
T55	15629	0	0	0
T72	14451	0	0	0
T76	0	35042	0	0
T77	0	94190	0	0
T78	0	31976	0	0
T89	0	2473	0	0
T90	0	14181	0	0
T175	0	2462	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18129	17824	0	0
T2	14585	14295	0	0
T3	136195	136193	0	0
T5	50743	49950	0	0
T6	214712	214710	0	0
T7	88313	86965	0	0
T8	409213	402670	0	0
T9	10541	10286	0	0
T10	93199	92950	0	0
T11	23435	23178	0	0