Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	58.90			58.90
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	64.38			64.38
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	65.07			65.07
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	68.49			68.49
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	69.86			69.86
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	69.86			69.86
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	70.55			70.55
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	72.60			72.60
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	76.71			76.71
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	78.08			78.08
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	83.56			83.56
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.90			58.90

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.90			58.90

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.07			65.07

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.07			65.07

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.49			68.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.49			68.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.86			69.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.86			69.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.86			69.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.86			69.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.55			70.55

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.55			70.55

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.71			76.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
76.71			76.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.08			78.08

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.08			78.08

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.56			83.56

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.56			83.56

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[63:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[2:0]	Yes	Yes	T117,T112,T118	Yes	T117,T112,T118	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T117,*T112,*T118	Yes	T117,T112,T118	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	172	58.90
Total Bits 0->1	146	86	58.90
Total Bits 1->0	146	86	58.90

Ports	4	0	0.00
Port Bits	292	172	58.90
Port Bits 0->1	146	86	58.90
Port Bits 1->0	146	86	58.90

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[9]	No	No		No		INPUT
data_i[13:10]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[14]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[26:24]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[32:31]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[33]	No	No		No		INPUT
data_i[35:34]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[38:36]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[40]	No	No		No		INPUT
data_i[49:41]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[50]	No	No		No		INPUT
data_i[52:51]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[56:53]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[3:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[26:24]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[32:31]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[35:34]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[38:36]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[49:41]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[52:51]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[56:53]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	188	64.38
Total Bits 0->1	146	94	64.38
Total Bits 1->0	146	94	64.38

Ports	4	0	0.00
Port Bits	292	188	64.38
Port Bits 0->1	146	94	64.38
Port Bits 1->0	146	94	64.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[5]	No	No		No		INPUT
data_i[9:6]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[10]	No	No		No		INPUT
data_i[11]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[16]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[23:22]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[24]	No	No		No		INPUT
data_i[31:25]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[35]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[47]	No	No		No		INPUT
data_i[49:48]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[51:50]	No	No		No		INPUT
data_i[57:52]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[1:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[9:6]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[11]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[23:22]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[31:25]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[49:48]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[51:50]	No	No		No		OUTPUT
data_o[57:52]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	190	65.07
Total Bits 0->1	146	95	65.07
Total Bits 1->0	146	95	65.07

Ports	4	0	0.00
Port Bits	292	190	65.07
Port Bits 0->1	146	95	65.07
Port Bits 1->0	146	95	65.07

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[6:1]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[14:9]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[15]	No	No		No		INPUT
data_i[18:16]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[19]	No	No		No		INPUT
data_i[22:20]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[34:30]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[35]	No	No		No		INPUT
data_i[38:36]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[39]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[45:43]	No	No		No		INPUT
data_i[47:46]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[55]	No	No		No		INPUT
data_i[58:56]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[59]	No	No		No		INPUT
data_i[64:60]	Yes	Yes	*T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[65]	No	No		No		INPUT
data_i[71:66]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[6:1]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[14:9]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[18:16]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[22:20]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[34:30]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[38:36]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[47:46]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[58:56]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	200	68.49
Total Bits 0->1	146	100	68.49
Total Bits 1->0	146	100	68.49

Ports	4	0	0.00
Port Bits	292	200	68.49
Port Bits 0->1	146	100	68.49
Port Bits 1->0	146	100	68.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[23:17]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[27:26]	No	No		No		INPUT
data_i[34:28]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[35]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[41]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[46]	No	No		No		INPUT
data_i[51:47]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[52]	No	No		No		INPUT
data_i[59:53]	Yes	Yes	*T68,*T5,*T8	Yes	T68,T5,T8	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[23:17]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[27:26]	No	No		No		OUTPUT
data_o[34:28]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[51:47]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[59:53]	Yes	Yes	*T68,*T5,*T8	Yes	T68,T5,T8	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	204	69.86
Total Bits 0->1	146	102	69.86
Total Bits 1->0	146	102	69.86

Ports	4	0	0.00
Port Bits	292	204	69.86
Port Bits 0->1	146	102	69.86
Port Bits 1->0	146	102	69.86

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[4]	No	No		No		INPUT
data_i[8:5]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[9]	No	No		No		INPUT
data_i[10]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[27:17]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[32:28]	No	No		No		INPUT
data_i[41:33]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[42]	No	No		No		INPUT
data_i[46:43]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[47]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[55]	No	No		No		INPUT
data_i[61:56]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[63:62]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[10]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[27:17]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[32:28]	No	No		No		OUTPUT
data_o[41:33]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[42]	No	No		No		OUTPUT
data_o[46:43]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[61:56]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[63:62]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	204	69.86
Total Bits 0->1	146	102	69.86
Total Bits 1->0	146	102	69.86

Ports	4	0	0.00
Port Bits	292	204	69.86
Port Bits 0->1	146	102	69.86
Port Bits 1->0	146	102	69.86

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[4:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[19]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[26]	No	No		No		INPUT
data_i[37:27]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[38]	No	No		No		INPUT
data_i[44:39]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[47:45]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[52]	No	No		No		INPUT
data_i[55:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[56]	No	No		No		INPUT
data_i[59:57]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[61:60]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[4:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[37:27]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[44:39]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[47:45]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[55:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[59:57]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[61:60]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	206	70.55
Total Bits 0->1	146	103	70.55
Total Bits 1->0	146	103	70.55

Ports	4	0	0.00
Port Bits	292	206	70.55
Port Bits 0->1	146	103	70.55
Port Bits 1->0	146	103	70.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[8]	No	No		No		INPUT
data_i[12:9]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[13]	No	No		No		INPUT
data_i[17:14]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[18]	No	No		No		INPUT
data_i[21:19]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[24:22]	No	No		No		INPUT
data_i[28:25]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[38:31]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[39]	No	No		No		INPUT
data_i[45:40]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[46]	No	No		No		INPUT
data_i[50:47]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[55:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[56]	No	No		No		INPUT
data_i[60:57]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[61]	No	No		No		INPUT
data_i[69:62]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[70]	No	No		No		INPUT
data_i[71]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[0]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[12:9]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[17:14]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[21:19]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[24:22]	No	No		No		OUTPUT
data_o[28:25]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[38:31]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[45:40]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[50:47]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[55:53]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[60:57]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	212	72.60
Total Bits 0->1	146	106	72.60
Total Bits 1->0	146	106	72.60

Ports	4	0	0.00
Port Bits	292	212	72.60
Port Bits 0->1	146	106	72.60
Port Bits 1->0	146	106	72.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_i[2]	No	No		No		INPUT
data_i[7:3]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[14]	No	No		No		INPUT
data_i[16:15]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[17]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	INPUT
data_i[19]	No	No		No		INPUT
data_i[28:20]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[36:31]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_i[37]	No	No		No		INPUT
data_i[45:38]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_i[48:46]	No	No		No		INPUT
data_i[53:49]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_i[54]	No	No		No		INPUT
data_i[56:55]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[57]	No	No		No		INPUT
data_i[60:58]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[1:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[7:3]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[16:15]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[17]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[28:20]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[36:31]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[45:38]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
data_o[48:46]	No	No		No		OUTPUT
data_o[53:49]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[56:55]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[57]	No	No		No		OUTPUT
data_o[60:58]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	224	76.71
Total Bits 0->1	146	112	76.71
Total Bits 1->0	146	112	76.71

Ports	4	0	0.00
Port Bits	292	224	76.71
Port Bits 0->1	146	112	76.71
Port Bits 1->0	146	112	76.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[5:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[6]	No	No		No		INPUT
data_i[9:7]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[17]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[18]	No	No		No		INPUT
data_i[19]	Yes	Yes	*T217	Yes	T217	INPUT
data_i[20]	No	No		No		INPUT
data_i[31:21]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[32]	No	No		No		INPUT
data_i[36:33]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[37]	No	No		No		INPUT
data_i[46:38]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[47]	No	No		No		INPUT
data_i[52:48]	Yes	Yes	*T217,*T5,*T7	Yes	T217,T5,T7	INPUT
data_i[53]	No	No		No		INPUT
data_i[59:54]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[60]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[5:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[6]	No	No		No		OUTPUT
data_o[9:7]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[17]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[19]	Yes	Yes	*T217	Yes	T217	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[31:21]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[36:33]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[46:38]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[52:48]	Yes	Yes	*T217,*T5,*T7	Yes	T217,T5,T7	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[59:54]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	228	78.08
Total Bits 0->1	146	114	78.08
Total Bits 1->0	146	114	78.08

Ports	4	0	0.00
Port Bits	292	228	78.08
Port Bits 0->1	146	114	78.08
Port Bits 1->0	146	114	78.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[6:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[15]	No	No		No		INPUT
data_i[19:16]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	INPUT
data_i[20]	No	No		No		INPUT
data_i[22:21]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[23]	No	No		No		INPUT
data_i[24]	Yes	Yes	*T218	Yes	T218	INPUT
data_i[25]	No	No		No		INPUT
data_i[31:26]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[32]	No	No		No		INPUT
data_i[37:33]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	INPUT
data_i[38]	No	No		No		INPUT
data_i[57:39]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	INPUT
data_i[59:58]	No	No		No		INPUT
data_i[60]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_o[6:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[19:16]	Yes	Yes	T5,*T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[20]	No	No		No		OUTPUT
data_o[22:21]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[24]	Yes	Yes	*T218	Yes	T218	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[31:26]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[37:33]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[57:39]	Yes	Yes	*T5,*T8,*T22	Yes	T5,T8,T22	OUTPUT
data_o[59:58]	No	No		No		OUTPUT
data_o[60]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	244	83.56
Total Bits 0->1	146	122	83.56
Total Bits 1->0	146	122	83.56

Ports	4	0	0.00
Port Bits	292	244	83.56
Port Bits 0->1	146	122	83.56
Port Bits 1->0	146	122	83.56

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	No	No		No		INPUT
data_i[14:2]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[15]	No	No		No		INPUT
data_i[21:16]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[22]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_i[25]	No	No		No		INPUT
data_i[40:26]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	INPUT
data_i[41]	No	No		No		INPUT
data_i[60:42]	Yes	Yes	*T69,*T5,*T7	Yes	T69,T5,T7	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[14:2]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[21:16]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[40:26]	Yes	Yes	*T5,*T7,*T8	Yes	T5,T7,T8	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[60:42]	Yes	Yes	*T69,*T5,*T7	Yes	T69,T5,T7	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_o[63:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T8,T22,T55	Yes	T8,T22,T55	INPUT
data_o[63:0]	Yes	Yes	T8,T22,T55	Yes	T8,T22,T55	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T78,T157,T81	Yes	T78,T157,T81	INPUT
data_o[63:0]	Yes	Yes	T78,T157,T81	Yes	T78,T157,T81	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T88,T81,T68	Yes	T88,T81,T68	INPUT
data_o[63:0]	Yes	Yes	T88,T81,T68	Yes	T88,T81,T68	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T22,T81,T219	Yes	T22,T81,T173	INPUT
data_o[63:0]	Yes	Yes	T22,T81,T219	Yes	T22,T81,T173	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T78,T36,T56	Yes	T78,T36,T56	INPUT
data_o[63:0]	Yes	Yes	T78,T36,T56	Yes	T78,T36,T56	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T22,T174,T220	Yes	T22,T174,T87	INPUT
data_o[63:0]	Yes	Yes	T22,T174,T220	Yes	T22,T174,T87	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T8,T22,T82	Yes	T8,T22,T82	INPUT
data_o[63:0]	Yes	Yes	T8,T22,T82	Yes	T8,T22,T82	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T8,T22,T85	Yes	T8,T22,T88	INPUT
data_o[63:0]	Yes	Yes	T8,T22,T85	Yes	T8,T22,T88	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T8,T22,T55	Yes	T1,T8,T22	INPUT
data_o[63:0]	Yes	Yes	T8,T22,T55	Yes	T1,T8,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	INPUT
data_o[63:0]	Yes	Yes	T5,T8,T22	Yes	T5,T8,T22	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[63:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T8,T22,T76	Yes	T8,T22,T76	INPUT
data_o[63:0]	Yes	Yes	T8,T22,T76	Yes	T8,T22,T76	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T72,T22	Yes	T5,T72,T22	INPUT
data_o[63:0]	Yes	Yes	T5,T72,T22	Yes	T5,T72,T22	OUTPUT
syndrome_o[2:0]	Yes	Yes	T112,T113,T114	Yes	T112,T113,T114	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T112,*T113,*T114	Yes	T112,T113,T114	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T7,T22	Yes	T5,T7,T22	INPUT
data_o[63:0]	Yes	Yes	T5,T7,T22	Yes	T5,T7,T22	OUTPUT
syndrome_o[2:0]	Yes	Yes	T117,T112,T118	Yes	T117,T112,T118	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T117,*T112,*T118	Yes	T117,T112,T118	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	INPUT
data_o[63:0]	Yes	Yes	T5,T7,T8	Yes	T5,T7,T8	OUTPUT
syndrome_o[2:0]	Yes	Yes	T117,T113,T114	Yes	T117,T113,T114	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T117,*T113,*T114	Yes	T117,T113,T114	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range