Line Coverage for Module :
otp_ctrl_prim_reg_top
| Line No. | Total | Covered | Percent |
TOTAL | | 104 | 104 | 100.00 |
ALWAYS | 71 | 4 | 4 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
CONT_ASSIGN | 122 | 1 | 1 | 100.00 |
ALWAYS | 1271 | 9 | 9 | 100.00 |
CONT_ASSIGN | 1282 | 1 | 1 | 100.00 |
ALWAYS | 1286 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1298 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1300 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1302 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1306 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1309 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1311 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1315 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1319 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1320 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1322 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1323 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1325 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1327 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1329 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1330 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1332 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1334 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1338 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1339 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1343 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1345 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1346 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1348 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1350 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1352 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1354 | 1 | 1 | 100.00 |
ALWAYS | 1358 | 9 | 9 | 100.00 |
ALWAYS | 1371 | 41 | 41 | 100.00 |
CONT_ASSIGN | 1447 | 0 | 0 | |
CONT_ASSIGN | 1455 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1456 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
|
|
|
MISSING_ELSE |
80 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
1271 |
1 |
1 |
1272 |
1 |
1 |
1273 |
1 |
1 |
1274 |
1 |
1 |
1275 |
1 |
1 |
1276 |
1 |
1 |
1277 |
1 |
1 |
1278 |
1 |
1 |
1279 |
1 |
1 |
1282 |
1 |
1 |
1286 |
1 |
1 |
1298 |
1 |
1 |
1300 |
1 |
1 |
1302 |
1 |
1 |
1304 |
1 |
1 |
1306 |
1 |
1 |
1308 |
1 |
1 |
1309 |
1 |
1 |
1311 |
1 |
1 |
1313 |
1 |
1 |
1315 |
1 |
1 |
1317 |
1 |
1 |
1319 |
1 |
1 |
1320 |
1 |
1 |
1322 |
1 |
1 |
1323 |
1 |
1 |
1325 |
1 |
1 |
1327 |
1 |
1 |
1329 |
1 |
1 |
1330 |
1 |
1 |
1332 |
1 |
1 |
1334 |
1 |
1 |
1336 |
1 |
1 |
1338 |
1 |
1 |
1339 |
1 |
1 |
1341 |
1 |
1 |
1343 |
1 |
1 |
1345 |
1 |
1 |
1346 |
1 |
1 |
1348 |
1 |
1 |
1350 |
1 |
1 |
1352 |
1 |
1 |
1354 |
1 |
1 |
1358 |
1 |
1 |
1359 |
1 |
1 |
1360 |
1 |
1 |
1361 |
1 |
1 |
1362 |
1 |
1 |
1363 |
1 |
1 |
1364 |
1 |
1 |
1365 |
1 |
1 |
1366 |
1 |
1 |
1371 |
1 |
1 |
1372 |
1 |
1 |
1374 |
1 |
1 |
1375 |
1 |
1 |
1376 |
1 |
1 |
1377 |
1 |
1 |
1378 |
1 |
1 |
1382 |
1 |
1 |
1383 |
1 |
1 |
1384 |
1 |
1 |
1385 |
1 |
1 |
1386 |
1 |
1 |
1390 |
1 |
1 |
1394 |
1 |
1 |
1395 |
1 |
1 |
1396 |
1 |
1 |
1397 |
1 |
1 |
1398 |
1 |
1 |
1399 |
1 |
1 |
1400 |
1 |
1 |
1401 |
1 |
1 |
1402 |
1 |
1 |
1406 |
1 |
1 |
1407 |
1 |
1 |
1408 |
1 |
1 |
1409 |
1 |
1 |
1413 |
1 |
1 |
1414 |
1 |
1 |
1415 |
1 |
1 |
1416 |
1 |
1 |
1417 |
1 |
1 |
1418 |
1 |
1 |
1419 |
1 |
1 |
1423 |
1 |
1 |
1424 |
1 |
1 |
1425 |
1 |
1 |
1426 |
1 |
1 |
1430 |
1 |
1 |
1431 |
1 |
1 |
1432 |
1 |
1 |
1433 |
1 |
1 |
1447 |
|
unreachable |
1455 |
1 |
1 |
1456 |
1 |
1 |
Cond Coverage for Module :
otp_ctrl_prim_reg_top
| Total | Covered | Percent |
Conditions | 101 | 98 | 97.03 |
Logical | 101 | 98 | 97.03 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 61
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T65,T99,T177 |
LINE 73
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T65,T98,T99 |
0 | 1 | Covered | T29,T30,T31 |
1 | 0 | Covered | T103,T187,T201 |
LINE 80
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T65,T98,T99 |
0 | 0 | 1 | Covered | T29,T30,T31 |
0 | 1 | 0 | Covered | T103,T187,T201 |
1 | 0 | 0 | Covered | T103,T187,T201 |
LINE 122
EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
-----------1---------- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T65,T98,T99 |
0 | 0 | 1 | Covered | T103,T187,T201 |
0 | 1 | 0 | Covered | T177,T178,T104 |
1 | 0 | 0 | Not Covered | |
LINE 122
SUB-EXPRESSION (devmode_i & addrmiss)
----1---- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T65,T98,T99 |
1 | 1 | Not Covered | |
LINE 1272
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR0_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T98,T99 |
LINE 1273
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR1_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1274
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR2_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1275
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR3_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1276
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR4_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1277
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR5_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1278
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR6_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1279
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CSR7_OFFSET)
--------------------------1-------------------------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1282
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
-1- | Status | Tests |
0 | Covered | T65,T98,T99 |
1 | Covered | T65,T99,T177 |
LINE 1282
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T65,T98,T99 |
0 | 1 | Covered | T65,T99,T177 |
1 | 0 | Covered | T65,T99,T100 |
LINE 1286
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))))
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T100 |
1 | 1 | Covered | T177,T178,T103 |
LINE 1286
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1111 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1111 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b0111 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b0011 & (~reg_be))))))
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T65,T99,T177 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T65,T177,T100 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T65,T99,T177 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T65,T177,T100 |
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T65,T99,T177 |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T65,T177,T100 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T177,T100,T178 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T65,T99,T177 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T65,T98,T99 |
LINE 1286
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T99,T177 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T65,T98,T99 |
LINE 1286
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T65,T99,T177 |
LINE 1286
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T177,T100,T178 |
LINE 1286
SUB-EXPRESSION (addr_hit[3] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T65,T177,T100 |
LINE 1286
SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T65,T99,T177 |
LINE 1286
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T65,T177,T100 |
LINE 1286
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T65,T99,T177 |
LINE 1286
SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T65,T98,T99 |
1 | 0 | Covered | T65,T99,T177 |
1 | 1 | Covered | T65,T177,T100 |
LINE 1298
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T65,T99,T100 |
1 | 0 | 1 | Covered | T65,T98,T99 |
1 | 1 | 0 | Covered | T177,T178,T183 |
1 | 1 | 1 | Covered | T65,T99,T100 |
LINE 1309
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T65,T99,T100 |
1 | 0 | 1 | Covered | T65,T99,T177 |
1 | 1 | 0 | Covered | T177,T178,T104 |
1 | 1 | 1 | Covered | T65,T99,T100 |
LINE 1320
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T65,T99,T100 |
1 | 0 | 1 | Covered | T65,T99,T177 |
1 | 1 | 0 | Covered | T177,T178,T103 |
1 | 1 | 1 | Covered | T65,T99,T100 |
LINE 1323
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T65,T99,T100 |
1 | 0 | 1 | Covered | T65,T99,T177 |
1 | 1 | 0 | Covered | T178,T187,T179 |
1 | 1 | 1 | Covered | T65,T99,T100 |
LINE 1330
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T65,T99,T100 |
1 | 0 | 1 | Covered | T65,T99,T177 |
1 | 1 | 0 | Covered | T177,T178,T103 |
1 | 1 | 1 | Covered | T65,T99,T100 |
LINE 1339
EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T65,T99,T100 |
1 | 0 | 1 | Covered | T65,T99,T177 |
1 | 1 | 0 | Covered | T177,T178,T104 |
1 | 1 | 1 | Covered | T65,T99,T100 |
LINE 1346
EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T65,T99,T100 |
1 | 0 | 1 | Covered | T65,T99,T177 |
1 | 1 | 0 | Covered | T177,T178,T103 |
1 | 1 | 1 | Covered | T65,T99,T100 |
Branch Coverage for Module :
otp_ctrl_prim_reg_top
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
1282 |
2 |
2 |
100.00 |
IF |
71 |
3 |
3 |
100.00 |
CASE |
1372 |
9 |
9 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_prim_reg_top_1.0/rtl/otp_ctrl_prim_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 1282 ((reg_re || reg_we)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T65,T99,T177 |
0 |
Covered |
T65,T98,T99 |
LineNo. Expression
-1-: 71 if ((!rst_ni))
-2-: 73 if ((intg_err || reg_we_err))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T65,T98,T99 |
0 |
1 |
Covered |
T103,T187,T201 |
0 |
0 |
Covered |
T65,T98,T99 |
LineNo. Expression
-1-: 1372 case (1'b1)
Branches:
-1- | Status | Tests |
addr_hit[0] |
Covered |
T65,T98,T99 |
addr_hit[1] |
Covered |
T65,T98,T99 |
addr_hit[2] |
Covered |
T65,T98,T99 |
addr_hit[3] |
Covered |
T65,T98,T99 |
addr_hit[4] |
Covered |
T65,T98,T99 |
addr_hit[5] |
Covered |
T65,T98,T99 |
addr_hit[6] |
Covered |
T65,T98,T99 |
addr_hit[7] |
Covered |
T65,T98,T99 |
default |
Covered |
T65,T98,T99 |
Assert Coverage for Module :
otp_ctrl_prim_reg_top
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
en2addrHit |
2147483647 |
246796 |
0 |
0 |
reAfterRv |
2147483647 |
246796 |
0 |
0 |
rePulse |
2147483647 |
27420 |
0 |
0 |
wePulse |
2147483647 |
219376 |
0 |
0 |
en2addrHit
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
246796 |
0 |
0 |
T65 |
4416 |
61 |
0 |
0 |
T98 |
3294 |
0 |
0 |
0 |
T99 |
3382 |
22 |
0 |
0 |
T100 |
3399 |
62 |
0 |
0 |
T101 |
4052 |
0 |
0 |
0 |
T102 |
3561 |
0 |
0 |
0 |
T103 |
61354 |
306 |
0 |
0 |
T104 |
7940 |
42 |
0 |
0 |
T177 |
7157 |
8 |
0 |
0 |
T178 |
6337 |
17 |
0 |
0 |
T187 |
0 |
294 |
0 |
0 |
T202 |
0 |
184 |
0 |
0 |
T223 |
0 |
147 |
0 |
0 |
reAfterRv
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
246796 |
0 |
0 |
T65 |
4416 |
61 |
0 |
0 |
T98 |
3294 |
0 |
0 |
0 |
T99 |
3382 |
22 |
0 |
0 |
T100 |
3399 |
62 |
0 |
0 |
T101 |
4052 |
0 |
0 |
0 |
T102 |
3561 |
0 |
0 |
0 |
T103 |
61354 |
306 |
0 |
0 |
T104 |
7940 |
42 |
0 |
0 |
T177 |
7157 |
8 |
0 |
0 |
T178 |
6337 |
17 |
0 |
0 |
T187 |
0 |
294 |
0 |
0 |
T202 |
0 |
184 |
0 |
0 |
T223 |
0 |
147 |
0 |
0 |
rePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
27420 |
0 |
0 |
T65 |
4416 |
45 |
0 |
0 |
T98 |
3294 |
0 |
0 |
0 |
T99 |
3382 |
14 |
0 |
0 |
T100 |
3399 |
46 |
0 |
0 |
T101 |
4052 |
0 |
0 |
0 |
T102 |
3561 |
0 |
0 |
0 |
T103 |
61354 |
225 |
0 |
0 |
T104 |
7940 |
27 |
0 |
0 |
T177 |
7157 |
0 |
0 |
0 |
T178 |
6337 |
0 |
0 |
0 |
T187 |
0 |
214 |
0 |
0 |
T202 |
0 |
93 |
0 |
0 |
T222 |
0 |
592 |
0 |
0 |
T223 |
0 |
73 |
0 |
0 |
T224 |
0 |
39 |
0 |
0 |
wePulse
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
219376 |
0 |
0 |
T65 |
4416 |
16 |
0 |
0 |
T98 |
3294 |
0 |
0 |
0 |
T99 |
3382 |
8 |
0 |
0 |
T100 |
3399 |
16 |
0 |
0 |
T101 |
4052 |
0 |
0 |
0 |
T102 |
3561 |
0 |
0 |
0 |
T103 |
61354 |
81 |
0 |
0 |
T104 |
7940 |
15 |
0 |
0 |
T177 |
7157 |
8 |
0 |
0 |
T178 |
6337 |
17 |
0 |
0 |
T187 |
0 |
80 |
0 |
0 |
T202 |
0 |
91 |
0 |
0 |
T223 |
0 |
74 |
0 |
0 |