Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.07	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if	10.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if	20.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
10.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	9	1	10.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	9	1	10.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
20.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	8	2	20.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	8	2	20.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	9	1	10.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1
true	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

14292

1

T18

1

T97

1

T98

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	8	2	20.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

10353

1

T18

1

T97

1

T98

1

true

16526

1

T18

1

T97

1

T98

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	104	1			T1	2		T13	4		T35	2
others[1]	86	1			T1	2		T91	2		T170	4
others[2]	88	1			T1	4		T10	2		T94	2
others[3]	104	1			T13	8		T96	4		T323	4
others[4]	86	1			T1	2		T10	2		T323	2
others[5]	108	1			T95	2		T87	2		T91	2
others[6]	114	1			T1	4		T6	2		T13	6
others[7]	96	1			T1	6		T35	2		T95	2
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	108	1			T10	2		T35	2		T29	2
others[1]	94	1			T13	4		T88	2		T91	2
others[2]	106	1			T13	2		T96	2		T149	2
others[3]	70	1			T87	2		T92	2		T323	2
others[4]	70	1			T170	2		T168	4		T324	2
others[5]	88	1			T13	4		T93	2		T170	2
others[6]	88	1			T92	2		T170	2		T153	2
others[7]	114	1			T1	4		T13	2		T87	4
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	86	1			T1	10		T10	2		T323	4
others[1]	78	1			T1	2		T35	2		T87	2
others[2]	76	1			T10	2		T13	2		T276	2
others[3]	90	1			T1	4		T13	6		T87	2
others[4]	90	1			T10	2		T13	4		T96	2
others[5]	126	1			T6	2		T13	2		T35	2
others[6]	86	1			T94	2		T93	2		T96	2
others[7]	100	1			T94	2		T75	2		T325	2
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	92	1			T1	2		T10	2		T13	2
others[1]	82	1			T1	2		T57	2		T88	2
others[2]	94	1			T1	2		T29	2		T152	2
others[3]	88	1			T1	2		T13	2		T150	2
others[4]	100	1			T1	2		T13	4		T88	2
others[5]	90	1			T1	2		T13	2		T87	4
others[6]	84	1			T95	2		T170	2		T326	2
others[7]	114	1			T1	6		T6	2		T13	2
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	84	1			T1	2		T95	2		T92	2
others[1]	84	1			T1	2		T91	2		T92	2
others[2]	84	1			T13	2		T94	2		T150	2
others[3]	84	1			T1	4		T13	2		T35	2
others[4]	102	1			T1	6		T13	4		T35	2
others[5]	108	1			T1	2		T10	2		T152	2
others[6]	82	1			T91	2		T93	2		T96	2
others[7]	106	1			T1	2		T13	4		T170	2
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	96	1			T95	2		T92	2		T323	2
others[1]	88	1			T1	2		T13	2		T93	2
others[2]	76	1			T1	2		T13	2		T170	2
others[3]	70	1			T13	4		T92	2		T168	2
others[4]	92	1			T1	2		T13	2		T54	2
others[5]	90	1			T1	4		T13	4		T94	2
others[6]	116	1			T1	2		T10	2		T13	2
others[7]	110	1			T1	10		T13	6		T96	2
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	76	1			T1	2		T323	2		T170	2
others[1]	86	1			T1	2		T13	4		T88	2
others[2]	80	1			T1	2		T10	2		T13	4
others[3]	128	1			T1	4		T13	2		T91	2
others[4]	80	1			T1	2		T13	2		T323	2
others[5]	92	1			T35	2		T88	4		T170	2
others[6]	106	1			T13	2		T35	2		T87	2
others[7]	98	1			T13	4		T94	2		T152	2
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	28	1			T75	2		T152	2		T327	2
others[1]	22	1			T13	2		T328	2		T329	2
others[2]	32	1			T151	2		T168	2		T67	2
others[3]	30	1			T13	2		T35	2		T92	2
others[4]	22	1			T324	2		T330	2		T331	4
others[5]	26	1			T153	2		T168	2		T324	2
others[6]	36	1			T6	2		T13	6		T91	2
others[7]	32	1			T149	2		T152	2		T168	4
false	14292	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	40	1			T11	1		T32	1		T279	1
others[1]	43	1			T32	2		T33	1		T332	2
others[2]	26	1			T16	1		T32	1		T34	1
others[3]	38	1			T11	1		T16	1		T17	1
others[4]	48	1			T32	1		T33	1		T294	1
others[5]	33	1			T12	1		T33	1		T17	1
others[6]	24	1			T32	1		T279	1		T333	2
others[7]	40	1			T16	1		T32	1		T33	1
false	14292	1			T18	1		T97	1		T98	1
true	2348	1			T1	44		T2	1		T4	2

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	37	1			T33	1		T279	2		T294	1
others[1]	35	1			T11	1		T33	1		T17	1
others[2]	38	1			T16	1		T32	1		T279	1
others[3]	26	1			T11	1		T32	3		T294	1
others[4]	31	1			T279	1		T221	1		T334	1
others[5]	35	1			T16	2		T32	2		T153	2
others[6]	36	1			T12	1		T33	1		T279	1
others[7]	54	1			T32	1		T33	1		T34	1
false	11714	1			T18	1		T97	1		T98	1
true	18865	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	110	1			T1	6		T10	2		T13	4
others[1]	88	1			T1	2		T10	2		T94	2
others[2]	86	1			T13	6		T35	2		T93	2
others[3]	106	1			T1	4		T6	2		T35	2
others[4]	98	1			T1	4		T13	2		T323	2
others[5]	104	1			T1	2		T13	2		T87	2
others[6]	70	1			T95	2		T153	2		T335	2
others[7]	124	1			T1	2		T13	4		T35	2
false	7592	1			T18	1		T97	1		T98	1
true	16562	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	92	1			T13	2		T88	2		T91	2
others[1]	96	1			T10	2		T13	4		T35	2
others[2]	92	1			T91	2		T93	2		T170	2
others[3]	94	1			T87	4		T323	2		T170	2
others[4]	84	1			T13	2		T92	4		T96	2
others[5]	94	1			T1	2		T87	2		T93	2
others[6]	78	1			T170	4		T151	2		T295	2
others[7]	108	1			T1	2		T13	4		T170	4
false	7004	1			T18	1		T97	1		T98	1
true	16368	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36	1			T11	1		T12	1		T32	1
others[1]	41	1			T32	1		T279	3		T336	1
others[2]	40	1			T32	1		T33	1		T279	2
others[3]	39	1			T11	2		T32	1		T33	3
others[4]	32	1			T336	1		T337	1		T338	2
others[5]	52	1			T13	2		T32	1		T33	1
others[6]	34	1			T13	2		T32	1		T33	1
others[7]	45	1			T16	1		T32	1		T33	2
false	11653	1			T18	1		T97	1		T98	1
true	18860	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	74	1			T96	2		T75	2		T153	6
others[1]	96	1			T10	2		T13	2		T94	2
others[2]	116	1			T1	6		T13	2		T96	2
others[3]	86	1			T1	4		T10	2		T13	6
others[4]	82	1			T6	2		T10	2		T94	2
others[5]	74	1			T35	2		T170	2		T29	2
others[6]	90	1			T13	4		T193	2		T323	4
others[7]	114	1			T1	6		T323	2		T170	2
false	7799	1			T18	1		T97	1		T98	1
true	16536	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	82	1			T1	4		T170	4		T29	2
others[1]	118	1			T1	6		T57	2		T13	4
others[2]	86	1			T13	2		T87	4		T193	2
others[3]	80	1			T1	2		T88	2		T323	2
others[4]	102	1			T1	2		T10	2		T92	2
others[5]	82	1			T13	4		T95	2		T339	2
others[6]	100	1			T1	2		T6	2		T13	2
others[7]	94	1			T1	2		T87	2		T96	2
false	7168	1			T18	1		T97	1		T98	1
true	16377	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	86	1			T94	2		T35	4		T91	2
others[1]	120	1			T13	4		T95	2		T91	2
others[2]	86	1			T1	2		T13	4		T91	4
others[3]	84	1			T1	2		T92	2		T170	2
others[4]	64	1			T1	2		T13	2		T96	2
others[5]	72	1			T1	8		T29	2		T151	2
others[6]	98	1			T1	2		T93	2		T326	2
others[7]	124	1			T1	2		T10	2		T13	2
false	7168	1			T18	1		T97	1		T98	1
true	16377	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	108	1			T1	2		T13	2		T35	2
others[1]	98	1			T1	2		T13	6		T91	2
others[2]	76	1			T1	2		T13	6		T94	2
others[3]	92	1			T1	8		T13	2		T29	2
others[4]	82	1			T13	2		T88	2		T92	2
others[5]	98	1			T96	2		T323	2		T181	2
others[6]	78	1			T1	6		T91	2		T340	2
others[7]	106	1			T1	2		T10	2		T13	4
false	6503	1			T18	1		T97	1		T98	1
true	16349	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	96	1			T1	2		T13	2		T91	2
others[1]	92	1			T13	2		T35	2		T88	2
others[2]	76	1			T1	6		T35	2		T295	2
others[3]	72	1			T88	2		T181	2		T153	2
others[4]	100	1			T13	6		T94	2		T96	2
others[5]	98	1			T10	2		T88	2		T170	2
others[6]	100	1			T1	4		T13	2		T91	2
others[7]	112	1			T13	6		T87	2		T93	2
false	6503	1			T18	1		T97	1		T98	1
true	16349	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	70	1			T1	2		T88	2		T91	2
others[1]	58	1			T1	2		T13	4		T91	2
others[2]	62	1			T1	2		T95	2		T29	2
others[3]	66	1			T1	2		T335	2		T341	4
others[4]	60	1			T1	2		T342	2		T343	2
others[5]	66	1			T1	4		T91	2		T54	2
others[6]	50	1			T1	2		T13	2		T151	2
others[7]	72	1			T13	2		T93	2		T342	2
false	6958	1			T18	1		T97	1		T98	1
true	17774	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	60	1			T13	4		T325	2		T341	2
others[1]	42	1			T13	2		T344	2		T341	2
others[2]	70	1			T1	2		T13	4		T151	2
others[3]	56	1			T13	6		T88	2		T93	2
others[4]	76	1			T1	4		T13	2		T91	2
others[5]	58	1			T87	2		T96	2		T153	2
others[6]	48	1			T13	2		T91	2		T93	2
others[7]	86	1			T1	4		T29	2		T178	2
false	6958	1			T18	1		T97	1		T98	1
true	17774	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	38	1			T1	2		T4	1		T11	2
others[1]	37	1			T1	2		T16	1		T32	2
others[2]	43	1			T32	4		T181	2		T332	1
others[3]	43	1			T11	1		T33	2		T34	1
others[4]	27	1			T11	1		T32	1		T33	2
others[5]	40	1			T13	2		T16	1		T32	1
others[6]	37	1			T32	2		T33	1		T17	1
others[7]	41	1			T11	2		T17	1		T279	2
false	11784	1			T18	1		T97	1		T98	1
true	18898	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	22	1			T6	2		T13	2		T345	2
others[1]	26	1			T13	2		T35	2		T92	2
others[2]	22	1			T13	4		T346	2		T341	2
others[3]	20	1			T152	2		T153	2		T324	2
others[4]	36	1			T149	2		T168	4		T324	2
others[5]	16	1			T168	2		T347	2		T328	2
others[6]	38	1			T151	2		T328	2		T348	2
others[7]	48	1			T13	2		T91	2		T75	2
false	10483	1			T18	1		T97	1		T98	1
true	16685	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19	1			T32	3		T279	2		T294	1
others[1]	37	1			T11	1		T33	1		T332	1
others[2]	44	1			T33	1		T34	1		T279	3
others[3]	31	1			T32	1		T33	1		T34	1
others[4]	37	1			T16	1		T32	1		T33	1
others[5]	55	1			T11	1		T13	4		T33	1
others[6]	42	1			T11	1		T32	1		T33	1
others[7]	55	1			T12	1		T32	1		T33	2
false	14292	1			T18	1		T97	1		T98	1
true	2388	1			T109	1		T1	52		T4	2

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	44	1			T341	4		T349	2		T67	2
others[1]	50	1			T1	4		T342	4		T168	2
others[2]	62	1			T1	6		T13	2		T88	2
others[3]	44	1			T29	2		T295	2		T350	4
others[4]	60	1			T1	2		T30	2		T335	4
others[5]	82	1			T1	2		T95	2		T93	2
others[6]	98	1			T91	2		T30	2		T342	2
others[7]	64	1			T1	2		T13	6		T151	2
false	14226	1			T18	1		T97	1		T98	1
true	16777	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	58	1			T13	2		T93	2		T335	2
others[1]	60	1			T1	2		T13	4		T151	2
others[2]	72	1			T1	2		T87	2		T29	2
others[3]	62	1			T13	2		T91	2		T335	2
others[4]	54	1			T1	2		T13	4		T341	2
others[5]	76	1			T88	2		T93	2		T96	2
others[6]	62	1			T13	8		T91	2		T351	2
others[7]	52	1			T1	4		T29	4		T168	2
false	14226	1			T18	1		T97	1		T98	1
true	16778	1			T18	1		T97	1		T98	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34	1			T32	4		T33	1		T334	1
others[1]	39	1			T11	1		T16	2		T33	2
others[2]	41	1			T4	1		T11	3		T352	2
others[3]	22	1			T17	1		T294	1		T336	1
others[4]	43	1			T1	2		T11	1		T32	1
others[5]	46	1			T13	2		T16	1		T32	1
others[6]	23	1			T32	2		T33	1		T34	1
others[7]	58	1			T1	2		T11	1		T32	2
false	14292	1			T18	1		T97	1		T98	1
true	2337	1			T108	1		T109	2		T1	46