Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9186724	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16885100

1

T18

273

T97

298

T98

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7974884	1			T18	71		T97	556		T98	24
values[0x0]	6891329	1			T18	114		T97	13		T98	36
values[0x1]	11205611	1			T18	174		T97	16		T98	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4767110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21304714

1

T18

323

T97

356

T98

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	96521	1			T18	1		T97	3		T98	1
valid_sources[0x01]	102250	1			T18	1		T106	13		T194	1
valid_sources[0x02]	99675	1			T99	1		T106	13		T194	1
valid_sources[0x03]	98589	1			T99	3		T106	12		T194	2
valid_sources[0x04]	99501	1			T18	3		T98	1		T106	7
valid_sources[0x05]	97498	1			T18	1		T99	5		T106	8
valid_sources[0x06]	104285	1			T18	1		T106	6		T194	3
valid_sources[0x07]	101574	1			T18	2		T97	7		T99	1
valid_sources[0x08]	98147	1			T18	1		T99	1		T106	3
valid_sources[0x09]	96104	1			T18	3		T106	16		T154	1
valid_sources[0x0a]	94973	1			T18	1		T99	3		T106	14
valid_sources[0x0b]	99684	1			T97	1		T99	4		T106	16
valid_sources[0x0c]	101125	1			T18	2		T99	3		T106	17
valid_sources[0x0d]	99796	1			T18	2		T99	1		T106	19
valid_sources[0x0e]	96316	1			T18	4		T99	6		T106	11
valid_sources[0x0f]	98833	1			T99	2		T105	23		T106	5
valid_sources[0x10]	98893	1			T18	1		T97	4		T99	1
valid_sources[0x11]	100718	1			T18	1		T97	10		T106	14
valid_sources[0x12]	111189	1			T18	3		T99	6		T106	15
valid_sources[0x13]	100898	1			T18	3		T97	6		T99	1
valid_sources[0x14]	100605	1			T18	1		T97	3		T106	20
valid_sources[0x15]	98663	1			T18	2		T106	6		T194	2
valid_sources[0x16]	98579	1			T18	1		T97	4		T99	2
valid_sources[0x17]	98232	1			T18	1		T97	2		T98	1
valid_sources[0x18]	99343	1			T18	1		T97	3		T99	7
valid_sources[0x19]	101105	1			T97	3		T99	2		T106	3
valid_sources[0x1a]	121351	1			T99	1		T106	20		T194	1
valid_sources[0x1b]	94617	1			T18	1		T106	19		T194	1
valid_sources[0x1c]	101042	1			T97	11		T99	1		T106	5
valid_sources[0x1d]	99299	1			T18	2		T99	4		T106	8
valid_sources[0x1e]	102349	1			T98	5		T106	6		T194	4
valid_sources[0x1f]	101431	1			T18	1		T99	2		T106	4
valid_sources[0x20]	109937	1			T18	3		T99	2		T104	129
valid_sources[0x21]	100425	1			T18	2		T99	1		T106	2
valid_sources[0x22]	97289	1			T18	1		T97	1		T106	6
valid_sources[0x23]	96767	1			T18	4		T99	6		T106	6
valid_sources[0x24]	100002	1			T18	2		T106	10		T194	1
valid_sources[0x25]	96544	1			T18	2		T102	1		T106	2
valid_sources[0x26]	98631	1			T99	2		T106	2		T194	1
valid_sources[0x27]	102888	1			T18	1		T97	4		T99	2
valid_sources[0x28]	99821	1			T18	4		T106	4		T194	2
valid_sources[0x29]	96902	1			T18	1		T99	1		T106	4
valid_sources[0x2a]	109504	1			T106	8		T196	6		T157	1
valid_sources[0x2b]	101113	1			T99	5		T106	22		T194	5
valid_sources[0x2c]	98351	1			T99	1		T106	1		T194	4
valid_sources[0x2d]	103630	1			T106	3		T194	4		T224	1
valid_sources[0x2e]	105981	1			T18	1		T99	3		T102	1
valid_sources[0x2f]	105916	1			T99	1		T106	9		T194	3
valid_sources[0x30]	101374	1			T98	3		T106	7		T194	3
valid_sources[0x31]	103308	1			T18	1		T99	2		T106	6
valid_sources[0x32]	103210	1			T99	3		T105	20		T106	19
valid_sources[0x33]	94601	1			T18	2		T99	5		T106	12
valid_sources[0x34]	102004	1			T18	1		T97	8		T106	2
valid_sources[0x35]	100040	1			T18	2		T97	5		T98	1
valid_sources[0x36]	102891	1			T106	15		T194	4		T207	1
valid_sources[0x37]	97285	1			T18	3		T106	14		T194	1
valid_sources[0x38]	98430	1			T18	1		T99	1		T104	256
valid_sources[0x39]	99890	1			T106	6		T194	3		T224	1
valid_sources[0x3a]	103001	1			T18	2		T106	10		T154	1
valid_sources[0x3b]	104407	1			T18	2		T97	9		T106	7
valid_sources[0x3c]	98723	1			T18	3		T106	6		T194	1
valid_sources[0x3d]	145819	1			T18	5		T106	17		T194	7
valid_sources[0x3e]	100541	1			T98	7		T99	1		T103	40
valid_sources[0x3f]	103462	1			T18	2		T99	5		T106	8
valid_sources[0x40]	99360	1			T18	1		T99	2		T106	6
valid_sources[0x41]	102655	1			T18	1		T97	1		T98	4
valid_sources[0x42]	99547	1			T18	1		T102	1		T106	4
valid_sources[0x43]	118434	1			T18	1		T99	13		T102	1
valid_sources[0x44]	103105	1			T18	2		T99	1		T106	4
valid_sources[0x45]	99347	1			T18	2		T97	9		T99	4
valid_sources[0x46]	101492	1			T18	3		T97	2		T99	1
valid_sources[0x47]	102474	1			T18	1		T97	2		T105	14
valid_sources[0x48]	102712	1			T99	2		T102	1		T106	3
valid_sources[0x49]	102285	1			T18	1		T106	4		T194	1
valid_sources[0x4a]	97351	1			T18	2		T97	3		T99	1
valid_sources[0x4b]	104672	1			T99	3		T106	9		T194	2
valid_sources[0x4c]	118133	1			T18	1		T97	1		T99	12
valid_sources[0x4d]	101580	1			T18	1		T97	3		T99	6
valid_sources[0x4e]	98617	1			T18	1		T99	6		T106	14
valid_sources[0x4f]	100599	1			T98	1		T99	2		T106	5
valid_sources[0x50]	102359	1			T97	9		T106	11		T194	2
valid_sources[0x51]	104333	1			T18	1		T97	6		T98	3
valid_sources[0x52]	96765	1			T98	2		T99	3		T106	7
valid_sources[0x53]	100887	1			T18	2		T106	24		T194	2
valid_sources[0x54]	97115	1			T18	1		T99	9		T106	4
valid_sources[0x55]	105000	1			T18	1		T99	12		T102	2
valid_sources[0x56]	99854	1			T18	3		T97	6		T98	2
valid_sources[0x57]	99449	1			T18	1		T106	4		T194	1
valid_sources[0x58]	103193	1			T18	1		T98	2		T99	1
valid_sources[0x59]	98566	1			T18	2		T97	1		T102	1
valid_sources[0x5a]	98705	1			T18	1		T97	3		T98	2
valid_sources[0x5b]	96888	1			T97	2		T99	1		T106	6
valid_sources[0x5c]	97155	1			T106	2		T194	2		T154	1
valid_sources[0x5d]	97843	1			T18	2		T99	6		T106	3
valid_sources[0x5e]	99132	1			T18	2		T97	3		T99	3
valid_sources[0x5f]	98500	1			T97	2		T99	1		T106	5
valid_sources[0x60]	99850	1			T18	2		T98	1		T99	1
valid_sources[0x61]	98256	1			T106	9		T194	1		T154	2
valid_sources[0x62]	135047	1			T18	1		T97	3		T106	13
valid_sources[0x63]	105563	1			T18	2		T97	10		T106	3
valid_sources[0x64]	98324	1			T18	1		T97	7		T99	2
valid_sources[0x65]	104624	1			T99	1		T106	11		T194	2
valid_sources[0x66]	103418	1			T18	3		T101	40		T105	1
valid_sources[0x67]	101083	1			T99	1		T102	1		T106	13
valid_sources[0x68]	98194	1			T18	2		T97	1		T106	5
valid_sources[0x69]	98443	1			T18	2		T98	1		T99	2
valid_sources[0x6a]	99271	1			T18	3		T99	7		T106	2
valid_sources[0x6b]	101118	1			T18	2		T97	7		T99	1
valid_sources[0x6c]	103880	1			T18	4		T99	1		T100	40
valid_sources[0x6d]	102792	1			T18	1		T99	2		T106	5
valid_sources[0x6e]	97441	1			T99	1		T106	13		T194	2
valid_sources[0x6f]	100484	1			T99	6		T106	4		T194	2
valid_sources[0x70]	105303	1			T18	3		T99	9		T106	5
valid_sources[0x71]	100554	1			T18	1		T97	5		T99	2
valid_sources[0x72]	97924	1			T18	3		T99	1		T106	11
valid_sources[0x73]	102759	1			T18	2		T97	6		T106	9
valid_sources[0x74]	101046	1			T18	1		T97	8		T99	4
valid_sources[0x75]	102440	1			T18	3		T99	7		T106	9
valid_sources[0x76]	109363	1			T18	1		T99	3		T106	13
valid_sources[0x77]	98208	1			T18	1		T97	2		T106	2
valid_sources[0x78]	98268	1			T18	3		T98	3		T99	2
valid_sources[0x79]	100700	1			T18	1		T97	7		T106	14
valid_sources[0x7a]	100918	1			T99	8		T106	11		T154	1
valid_sources[0x7b]	98694	1			T18	1		T99	3		T106	9
valid_sources[0x7c]	100936	1			T99	3		T106	2		T194	2
valid_sources[0x7d]	101763	1			T18	1		T99	3		T106	7
valid_sources[0x7e]	110051	1			T18	1		T106	6		T194	3
valid_sources[0x7f]	101670	1			T18	1		T99	4		T106	15
valid_sources[0x80]	103027	1			T106	10		T194	4		T107	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4641604

1

T18

67

T97

275

T98

9

values[0x0]

all_enables

biggest_size

6164719

1

T18

107

T97

11

T98

31

values[0x1]

all_enables

biggest_size

6078777

1

T18

99

T97

12

T98

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	857538	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31577828

1

T18

159

T97

154

T98

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7951512	1			T18	39		T97	296		T98	42
values[0x0]	11882998	1			T18	61		T97	3		T98	5
values[0x1]	12600856	1			T18	74		T97	5		T98	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	296325	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

32139041

1

T18

170

T97

182

T98

26

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	127134	1			T106	53		T156	1		T157	3
valid_sources[0x01]	126925	1			T18	1		T97	2		T206	6
valid_sources[0x02]	127247	1			T156	2		T157	2		T245	5
valid_sources[0x03]	124164	1			T18	2		T97	2		T99	4
valid_sources[0x04]	130837	1			T97	5		T99	3		T106	8
valid_sources[0x05]	127373	1			T18	1		T99	1		T156	2
valid_sources[0x06]	121358	1			T97	3		T206	5		T156	1
valid_sources[0x07]	128553	1			T97	7		T99	2		T154	1
valid_sources[0x08]	125946	1			T106	21		T194	8		T155	2
valid_sources[0x09]	128402	1			T18	1		T97	3		T99	4
valid_sources[0x0a]	126121	1			T18	4		T99	2		T106	9
valid_sources[0x0b]	128102	1			T157	4		T245	4		T176	2
valid_sources[0x0c]	125160	1			T99	5		T155	1		T156	1
valid_sources[0x0d]	124337	1			T99	2		T194	12		T157	2
valid_sources[0x0e]	125989	1			T97	3		T156	1		T157	2
valid_sources[0x0f]	123783	1			T18	1		T155	1		T196	4
valid_sources[0x10]	123398	1			T97	3		T156	4		T157	3
valid_sources[0x11]	127407	1			T18	1		T97	4		T154	1
valid_sources[0x12]	125006	1			T18	3		T97	5		T194	5
valid_sources[0x13]	124514	1			T157	1		T245	4		T176	3
valid_sources[0x14]	128970	1			T106	53		T107	1		T196	2
valid_sources[0x15]	125909	1			T97	1		T99	2		T156	5
valid_sources[0x16]	130064	1			T97	3		T155	1		T156	2
valid_sources[0x17]	127458	1			T18	3		T97	7		T106	21
valid_sources[0x18]	128524	1			T18	2		T156	2		T157	2
valid_sources[0x19]	123267	1			T194	8		T196	2		T157	1
valid_sources[0x1a]	127834	1			T18	1		T97	1		T194	8
valid_sources[0x1b]	125375	1			T97	1		T99	8		T156	1
valid_sources[0x1c]	125748	1			T18	3		T99	2		T106	16
valid_sources[0x1d]	131428	1			T97	1		T155	1		T157	3
valid_sources[0x1e]	131252	1			T18	1		T97	1		T99	7
valid_sources[0x1f]	130785	1			T18	4		T99	1		T196	1
valid_sources[0x20]	127363	1			T18	2		T99	6		T194	4
valid_sources[0x21]	129002	1			T18	1		T97	4		T156	1
valid_sources[0x22]	123310	1			T18	2		T97	1		T99	4
valid_sources[0x23]	127834	1			T209	1		T156	4		T157	3
valid_sources[0x24]	126550	1			T18	2		T97	1		T99	3
valid_sources[0x25]	129531	1			T18	5		T99	1		T106	22
valid_sources[0x26]	128840	1			T18	1		T97	2		T99	4
valid_sources[0x27]	128061	1			T18	2		T106	3		T156	1
valid_sources[0x28]	128632	1			T18	1		T157	1		T158	1
valid_sources[0x29]	122644	1			T99	2		T106	8		T194	2
valid_sources[0x2a]	128537	1			T99	5		T105	17		T156	1
valid_sources[0x2b]	129753	1			T104	127		T106	4		T157	2
valid_sources[0x2c]	124067	1			T99	1		T156	1		T157	4
valid_sources[0x2d]	127287	1			T97	5		T157	3		T245	2
valid_sources[0x2e]	122544	1			T99	3		T106	14		T107	1
valid_sources[0x2f]	124087	1			T18	1		T196	11		T156	2
valid_sources[0x30]	129366	1			T18	1		T97	1		T99	7
valid_sources[0x31]	122863	1			T106	26		T194	5		T196	1
valid_sources[0x32]	130990	1			T97	1		T194	18		T156	1
valid_sources[0x33]	122662	1			T97	2		T99	3		T157	5
valid_sources[0x34]	121720	1			T106	5		T157	3		T245	2
valid_sources[0x35]	124037	1			T157	3		T245	3		T238	17
valid_sources[0x36]	126658	1			T99	5		T157	6		T176	3
valid_sources[0x37]	125122	1			T97	2		T106	81		T206	2
valid_sources[0x38]	128941	1			T18	3		T97	1		T99	5
valid_sources[0x39]	123049	1			T97	11		T106	34		T196	4
valid_sources[0x3a]	129810	1			T156	3		T157	3		T158	1
valid_sources[0x3b]	124913	1			T97	1		T99	1		T106	18
valid_sources[0x3c]	127456	1			T99	1		T194	1		T155	1
valid_sources[0x3d]	128424	1			T99	2		T106	35		T156	1
valid_sources[0x3e]	129866	1			T106	15		T194	14		T155	1
valid_sources[0x3f]	126916	1			T97	7		T99	1		T106	16
valid_sources[0x40]	122857	1			T194	1		T156	2		T157	2
valid_sources[0x41]	126003	1			T18	1		T99	1		T194	6
valid_sources[0x42]	124714	1			T18	4		T97	1		T196	3
valid_sources[0x43]	128479	1			T106	25		T156	3		T157	5
valid_sources[0x44]	126912	1			T97	5		T99	1		T106	5
valid_sources[0x45]	125373	1			T18	2		T99	4		T106	40
valid_sources[0x46]	126689	1			T18	1		T154	2		T156	3
valid_sources[0x47]	127161	1			T99	1		T106	2		T157	1
valid_sources[0x48]	128281	1			T99	1		T106	17		T196	2
valid_sources[0x49]	126298	1			T106	12		T156	1		T158	1
valid_sources[0x4a]	122031	1			T18	1		T99	1		T106	6
valid_sources[0x4b]	126898	1			T18	1		T99	6		T194	3
valid_sources[0x4c]	130340	1			T18	1		T106	1		T156	1
valid_sources[0x4d]	127413	1			T106	7		T194	2		T107	1
valid_sources[0x4e]	128573	1			T18	1		T99	1		T106	2
valid_sources[0x4f]	125983	1			T194	1		T156	2		T157	1
valid_sources[0x50]	127032	1			T18	1		T99	3		T106	27
valid_sources[0x51]	127143	1			T97	8		T99	1		T106	7
valid_sources[0x52]	130700	1			T18	2		T99	5		T156	2
valid_sources[0x53]	124301	1			T18	1		T97	2		T99	6
valid_sources[0x54]	129584	1			T97	4		T157	3		T245	2
valid_sources[0x55]	122029	1			T97	1		T99	5		T106	4
valid_sources[0x56]	125697	1			T97	3		T194	7		T206	1
valid_sources[0x57]	125078	1			T97	6		T106	2		T156	3
valid_sources[0x58]	124699	1			T99	5		T157	5		T158	1
valid_sources[0x59]	125140	1			T18	1		T106	11		T207	1
valid_sources[0x5a]	128087	1			T98	8		T99	2		T156	1
valid_sources[0x5b]	122282	1			T18	1		T106	2		T107	1
valid_sources[0x5c]	126431	1			T18	2		T106	18		T156	1
valid_sources[0x5d]	125786	1			T97	3		T106	46		T207	3
valid_sources[0x5e]	123134	1			T99	3		T106	24		T154	7
valid_sources[0x5f]	129524	1			T106	13		T196	5		T156	1
valid_sources[0x60]	124562	1			T18	1		T97	4		T154	2
valid_sources[0x61]	129175	1			T196	4		T209	6		T156	1
valid_sources[0x62]	124898	1			T97	6		T99	3		T155	1
valid_sources[0x63]	121677	1			T99	7		T106	3		T157	6
valid_sources[0x64]	128018	1			T18	2		T106	11		T206	1
valid_sources[0x65]	128238	1			T99	4		T106	28		T194	4
valid_sources[0x66]	125045	1			T99	1		T196	13		T157	5
valid_sources[0x67]	122876	1			T99	5		T107	1		T156	3
valid_sources[0x68]	131087	1			T106	2		T194	14		T155	1
valid_sources[0x69]	122558	1			T18	1		T97	1		T157	5
valid_sources[0x6a]	129052	1			T97	5		T99	2		T196	1
valid_sources[0x6b]	124987	1			T105	11		T155	1		T156	2
valid_sources[0x6c]	123823	1			T18	1		T104	128		T206	2
valid_sources[0x6d]	123328	1			T104	256		T154	8		T156	9
valid_sources[0x6e]	125109	1			T106	20		T194	8		T154	3
valid_sources[0x6f]	125772	1			T99	3		T106	2		T194	8
valid_sources[0x70]	126439	1			T97	7		T99	1		T194	15
valid_sources[0x71]	125374	1			T97	1		T106	23		T154	3
valid_sources[0x72]	128086	1			T18	1		T106	6		T154	5
valid_sources[0x73]	126978	1			T18	1		T97	5		T106	14
valid_sources[0x74]	130380	1			T97	2		T156	2		T157	1
valid_sources[0x75]	126540	1			T18	1		T97	2		T98	18
valid_sources[0x76]	121561	1			T99	7		T106	42		T156	2
valid_sources[0x77]	121726	1			T18	1		T99	3		T156	3
valid_sources[0x78]	129167	1			T97	2		T99	1		T155	2
valid_sources[0x79]	122521	1			T18	5		T106	2		T194	4
valid_sources[0x7a]	127923	1			T18	1		T97	4		T107	1
valid_sources[0x7b]	127489	1			T18	3		T156	3		T157	7
valid_sources[0x7c]	125248	1			T156	3		T157	5		T158	3
valid_sources[0x7d]	128662	1			T18	7		T97	7		T106	9
valid_sources[0x7e]	128120	1			T206	1		T157	1		T245	6
valid_sources[0x7f]	126105	1			T99	1		T106	2		T154	4
valid_sources[0x80]	129729	1			T106	17		T196	1		T207	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7937746

1

T18

39

T97

148

T98

6

values[0x0]

all_enables

biggest_size

11823445

1

T18

60

T97

3

T98

4

values[0x1]

all_enables

biggest_size

11816637

1

T18

60

T97

3

T98

6