Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

70130242

1

T18

1495

T97

287

T98

22

full_word

20855633

1

T18

381

T97

298

T98

58

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90985545	1			T18	1876		T97	585		T98	80
auto[TlIntgErrCmd]	123	1			T105	4		T176	9		T177	12
auto[TlIntgErrData]	116	1			T105	1		T176	9		T177	3
auto[TlIntgErrBoth]	91	1			T105	5		T176	2		T177	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12742741

1

T18

213

T97

556

T98

24

auto[1]

78243134

1

T18

1663

T97

29

T98

56

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7617986	1			T18	128		T97	281		T98	15
auto[TlIntgErrNone]	partial	auto[1]	62511953	1			T18	1367		T97	6		T98	7
auto[TlIntgErrNone]	full_word	auto[0]	5124609	1			T18	85		T97	275		T98	9
auto[TlIntgErrNone]	full_word	auto[1]	15730997	1			T18	296		T97	23		T98	49
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T105	2		T176	4		T177	5
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T105	1		T176	5		T177	7
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T105	1		T195	2		T257	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T208	1		T195	1		T298	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T105	1		T176	5		T177	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T176	3		T208	3		T195	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T176	1		T195	1		T231	3
auto[TlIntgErrData]	full_word	auto[1]	4	1			T231	1		T300	1		T301	2
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T105	4		T176	1		T177	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T105	1		T176	1		T177	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T299	1		T302	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T195	1		T231	1		T300	1