Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.93	97.18	88.57	96.91		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	22439238	0	0
check_regwen_rd_A	2147483647	4419	0	0
check_timeout_rd_A	2147483647	3700	0	0
check_trigger_regwen_rd_A	2147483647	4629	0	0
consistency_check_period_rd_A	2147483647	4551	0	0
creator_sw_cfg_read_lock_rd_A	2147483647	3632	0	0
direct_access_address_rd_A	2147483647	3217	0	0
direct_access_wdata_0_rd_A	2147483647	2314	0	0
direct_access_wdata_1_rd_A	2147483647	2656	0	0
integrity_check_period_rd_A	2147483647	4496	0	0
intr_enable_rd_A	2147483647	5126	0	0
owner_sw_cfg_read_lock_rd_A	2147483647	3218	0	0
vendor_test_read_lock_rd_A	2147483647	3414	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22439238	0	0
T18	7410	502	0	0
T97	4507	0	0	0
T98	3741	0	0	0
T99	6830	0	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	0	0	0
T105	58468	6	0	0
T154	0	31	0	0
T155	0	165	0	0
T156	0	64	0	0
T157	0	197	0	0
T158	0	70	0	0
T159	0	26	0	0
T176	0	4	0	0
T177	0	5	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4419	0	0
T98	3741	9	0	0
T99	6830	0	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	0	0	0
T105	58468	0	0	0
T106	43073	443	0	0
T176	0	40	0	0
T177	0	76	0	0
T194	4878	0	0	0
T196	0	10	0	0
T206	0	14	0	0
T208	0	24	0	0
T211	0	13	0	0
T246	0	148	0	0
T247	0	108	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3700	0	0
T160	14944	2	0	0
T161	6948	0	0	0
T196	8407	17	0	0
T207	3860	0	0	0
T209	5124	0	0	0
T227	3529	0	0	0
T228	5172	0	0	0
T229	3720	0	0	0
T230	3366	0	0	0
T242	0	14	0	0
T246	8581	127	0	0
T248	0	1	0	0
T249	0	20	0	0
T250	0	10	0	0
T251	0	48	0	0
T252	0	34	0	0
T253	0	1	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4629	0	0
T98	3741	12	0	0
T99	6830	0	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	0	0	0
T105	58468	0	0	0
T106	43073	437	0	0
T176	0	42	0	0
T177	0	72	0	0
T194	4878	0	0	0
T196	0	21	0	0
T206	0	6	0	0
T208	0	47	0	0
T211	0	8	0	0
T246	0	151	0	0
T247	0	177	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4551	0	0
T98	3741	15	0	0
T99	6830	0	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	0	0	0
T105	58468	0	0	0
T106	43073	450	0	0
T176	0	37	0	0
T177	0	81	0	0
T194	4878	0	0	0
T196	0	9	0	0
T206	0	1	0	0
T208	0	45	0	0
T211	0	5	0	0
T246	0	152	0	0
T247	0	140	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3632	0	0
T195	111583	0	0	0
T196	8407	4	0	0
T204	10021	0	0	0
T207	3860	0	0	0
T209	5124	0	0	0
T242	0	12	0	0
T246	8581	148	0	0
T247	21089	0	0	0
T248	0	2	0	0
T249	0	30	0	0
T250	0	19	0	0
T251	0	19	0	0
T252	0	2	0	0
T253	0	12	0	0
T254	0	12	0	0
T255	5984	0	0	0
T256	4814	0	0	0
T257	115927	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3217	0	0
T4	194089	28	0	0
T6	35565	0	0	0
T8	10666	0	0	0
T9	14511	0	0	0
T10	203241	0	0	0
T34	0	215	0	0
T221	0	195	0	0
T248	5783	4	0	0
T253	9302	8	0	0
T254	8073	0	0	0
T258	0	124	0	0
T259	0	47	0	0
T260	0	109	0	0
T261	0	133	0	0
T262	0	125	0	0
T263	3630	0	0	0
T264	3600	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2314	0	0
T34	193154	173	0	0
T36	60009	0	0	0
T51	13447	0	0	0
T54	82307	0	0	0
T59	12844	0	0	0
T221	0	187	0	0
T258	0	137	0	0
T259	0	20	0	0
T260	0	49	0	0
T261	0	24	0	0
T262	0	45	0	0
T265	0	98	0	0
T266	0	33	0	0
T267	0	112	0	0
T268	16614	0	0	0
T269	13460	0	0	0
T270	32089	0	0	0
T271	104789	0	0	0
T272	9263	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2656	0	0
T4	194089	20	0	0
T6	35565	0	0	0
T8	10666	0	0	0
T9	14511	0	0	0
T10	203241	0	0	0
T11	431689	0	0	0
T14	8199	0	0	0
T34	0	167	0	0
T57	16207	0	0	0
T117	16943	0	0	0
T121	10985	0	0	0
T221	0	224	0	0
T258	0	88	0	0
T259	0	21	0	0
T260	0	44	0	0
T261	0	118	0	0
T262	0	107	0	0
T265	0	93	0	0
T266	0	36	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4496	0	0
T98	3741	12	0	0
T99	6830	0	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	0	0	0
T103	3875	0	0	0
T104	8366	0	0	0
T105	58468	0	0	0
T106	43073	496	0	0
T176	0	29	0	0
T177	0	77	0	0
T194	4878	0	0	0
T196	0	23	0	0
T206	0	7	0	0
T208	0	46	0	0
T211	0	7	0	0
T246	0	165	0	0
T247	0	142	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5126	0	0
T98	3741	16	0	0
T99	6830	0	0	0
T100	3380	0	0	0
T101	3495	0	0	0
T102	3655	7	0	0
T103	3875	20	0	0
T104	8366	0	0	0
T105	58468	0	0	0
T106	43073	504	0	0
T176	0	60	0	0
T177	0	106	0	0
T194	4878	0	0	0
T196	0	30	0	0
T206	0	23	0	0
T208	0	50	0	0
T228	0	7	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3218	0	0
T4	0	34	0	0
T195	111583	0	0	0
T196	8407	18	0	0
T204	10021	0	0	0
T207	3860	0	0	0
T209	5124	0	0	0
T246	8581	145	0	0
T247	21089	0	0	0
T248	0	2	0	0
T249	0	7	0	0
T250	0	4	0	0
T251	0	93	0	0
T252	0	21	0	0
T253	0	8	0	0
T254	0	19	0	0
T255	5984	0	0	0
T256	4814	0	0	0
T257	115927	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3414	0	0
T4	0	22	0	0
T195	111583	0	0	0
T196	8407	35	0	0
T204	10021	0	0	0
T207	3860	0	0	0
T209	5124	0	0	0
T242	0	15	0	0
T246	8581	144	0	0
T247	21089	0	0	0
T249	0	23	0	0
T250	0	4	0	0
T251	0	41	0	0
T252	0	46	0	0
T253	0	1	0	0
T254	0	14	0	0
T255	5984	0	0	0
T256	4814	0	0	0
T257	115927	0	0	0