Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8215627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14289508

1

T18

11

T114

191

T115

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7224501	1			T18	19		T114	45		T115	19
values[0x0]	5836742	1			T18	7		T114	74		T115	11
values[0x1]	9443892	1			T18	12		T114	88		T115	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4376642	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

18128493

1

T18

13

T114

201

T115

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	86610	1			T116	1		T184	3		T118	3
valid_sources[0x01]	83751	1			T114	2		T116	10		T120	1
valid_sources[0x02]	82054	1			T116	5		T117	5		T183	1
valid_sources[0x03]	82447	1			T114	1		T116	6		T117	11
valid_sources[0x04]	99813	1			T114	4		T116	4		T117	3
valid_sources[0x05]	83170	1			T18	3		T114	1		T116	3
valid_sources[0x06]	85676	1			T116	1		T184	2		T121	4
valid_sources[0x07]	84898	1			T116	1		T183	3		T184	3
valid_sources[0x08]	86487	1			T116	5		T184	2		T121	5
valid_sources[0x09]	87226	1			T116	3		T122	15		T185	4
valid_sources[0x0a]	84994	1			T114	1		T116	3		T184	28
valid_sources[0x0b]	101026	1			T116	2		T121	2		T122	6
valid_sources[0x0c]	84582	1			T116	6		T120	1		T121	6
valid_sources[0x0d]	111856	1			T114	2		T116	3		T183	1
valid_sources[0x0e]	86551	1			T114	5		T116	8		T184	2
valid_sources[0x0f]	90784	1			T114	2		T116	6		T184	2
valid_sources[0x10]	119687	1			T116	4		T121	3		T122	7
valid_sources[0x11]	92589	1			T18	1		T116	1		T121	1
valid_sources[0x12]	83732	1			T116	8		T118	1		T120	1
valid_sources[0x13]	89657	1			T114	1		T116	3		T118	3
valid_sources[0x14]	114205	1			T114	1		T116	8		T121	4
valid_sources[0x15]	92397	1			T18	1		T116	4		T121	4
valid_sources[0x16]	86196	1			T116	8		T122	7		T186	1
valid_sources[0x17]	86980	1			T114	1		T116	6		T117	2
valid_sources[0x18]	82952	1			T114	1		T116	5		T121	1
valid_sources[0x19]	84959	1			T116	6		T117	9		T122	9
valid_sources[0x1a]	116206	1			T114	1		T116	7		T119	1
valid_sources[0x1b]	91527	1			T114	2		T116	4		T183	1
valid_sources[0x1c]	84158	1			T121	5		T122	10		T186	3
valid_sources[0x1d]	84424	1			T116	4		T121	2		T122	9
valid_sources[0x1e]	83248	1			T114	1		T116	4		T122	10
valid_sources[0x1f]	81582	1			T114	1		T116	4		T117	2
valid_sources[0x20]	84153	1			T114	3		T116	6		T118	2
valid_sources[0x21]	86815	1			T116	11		T121	1		T122	4
valid_sources[0x22]	86153	1			T114	1		T116	8		T121	2
valid_sources[0x23]	89767	1			T116	3		T184	4		T122	2
valid_sources[0x24]	82375	1			T114	1		T116	2		T119	6
valid_sources[0x25]	86105	1			T18	1		T114	2		T116	4
valid_sources[0x26]	84807	1			T116	3		T117	2		T121	1
valid_sources[0x27]	86113	1			T114	1		T121	2		T122	5
valid_sources[0x28]	89374	1			T116	8		T119	2		T184	1
valid_sources[0x29]	85395	1			T114	1		T116	6		T184	1
valid_sources[0x2a]	91053	1			T116	6		T120	1		T121	4
valid_sources[0x2b]	84825	1			T116	3		T184	11		T121	1
valid_sources[0x2c]	81093	1			T18	4		T116	8		T121	2
valid_sources[0x2d]	87343	1			T116	8		T117	4		T121	1
valid_sources[0x2e]	87669	1			T116	3		T121	2		T122	3
valid_sources[0x2f]	93056	1			T116	7		T118	1		T122	6
valid_sources[0x30]	90342	1			T114	4		T116	4		T183	2
valid_sources[0x31]	90124	1			T116	6		T121	1		T122	6
valid_sources[0x32]	89592	1			T116	6		T122	4		T186	2
valid_sources[0x33]	88302	1			T116	3		T117	11		T184	6
valid_sources[0x34]	88514	1			T116	3		T121	5		T122	4
valid_sources[0x35]	85115	1			T116	9		T120	1		T121	3
valid_sources[0x36]	84819	1			T114	2		T116	7		T121	1
valid_sources[0x37]	83422	1			T18	1		T114	3		T116	3
valid_sources[0x38]	86320	1			T116	3		T121	3		T122	5
valid_sources[0x39]	85738	1			T114	2		T116	6		T121	2
valid_sources[0x3a]	89928	1			T116	4		T121	2		T122	6
valid_sources[0x3b]	84096	1			T116	7		T122	19		T186	1
valid_sources[0x3c]	89042	1			T114	3		T116	7		T122	9
valid_sources[0x3d]	110573	1			T116	3		T184	3		T121	3
valid_sources[0x3e]	92343	1			T116	1		T117	4		T121	4
valid_sources[0x3f]	84878	1			T116	10		T119	1		T121	4
valid_sources[0x40]	87313	1			T116	4		T117	9		T118	2
valid_sources[0x41]	87846	1			T116	2		T121	1		T122	7
valid_sources[0x42]	83531	1			T114	1		T121	7		T122	12
valid_sources[0x43]	85690	1			T114	2		T116	2		T118	1
valid_sources[0x44]	84036	1			T18	1		T116	6		T117	1
valid_sources[0x45]	84156	1			T18	3		T116	4		T117	9
valid_sources[0x46]	84099	1			T116	1		T183	1		T122	13
valid_sources[0x47]	84667	1			T116	7		T118	2		T121	2
valid_sources[0x48]	82782	1			T114	3		T116	2		T120	1
valid_sources[0x49]	90984	1			T114	1		T116	3		T121	2
valid_sources[0x4a]	92450	1			T116	6		T121	2		T122	15
valid_sources[0x4b]	82926	1			T116	6		T121	3		T122	15
valid_sources[0x4c]	82983	1			T116	7		T183	1		T121	3
valid_sources[0x4d]	83779	1			T114	2		T116	6		T183	1
valid_sources[0x4e]	96009	1			T114	1		T116	5		T184	26
valid_sources[0x4f]	84664	1			T116	2		T121	2		T122	14
valid_sources[0x50]	88411	1			T121	3		T122	3		T185	1
valid_sources[0x51]	82509	1			T116	4		T121	4		T122	9
valid_sources[0x52]	81882	1			T114	1		T116	1		T184	2
valid_sources[0x53]	86492	1			T114	1		T116	4		T121	1
valid_sources[0x54]	82296	1			T116	5		T183	1		T184	4
valid_sources[0x55]	85892	1			T114	2		T116	5		T121	5
valid_sources[0x56]	88515	1			T114	2		T116	3		T183	1
valid_sources[0x57]	93017	1			T114	2		T116	2		T121	3
valid_sources[0x58]	82442	1			T116	2		T184	1		T121	1
valid_sources[0x59]	82280	1			T114	1		T115	1		T116	5
valid_sources[0x5a]	85383	1			T114	2		T116	2		T184	5
valid_sources[0x5b]	91479	1			T116	4		T121	2		T122	14
valid_sources[0x5c]	83322	1			T116	6		T184	11		T121	2
valid_sources[0x5d]	82473	1			T116	1		T183	1		T122	16
valid_sources[0x5e]	95832	1			T114	4		T116	3		T119	5
valid_sources[0x5f]	88192	1			T114	1		T116	2		T184	1
valid_sources[0x60]	84615	1			T116	1		T183	1		T121	6
valid_sources[0x61]	82613	1			T18	2		T116	5		T117	10
valid_sources[0x62]	87172	1			T114	2		T116	2		T184	1
valid_sources[0x63]	87204	1			T116	5		T121	2		T122	7
valid_sources[0x64]	86309	1			T114	2		T122	13		T185	5
valid_sources[0x65]	89673	1			T116	4		T121	3		T122	24
valid_sources[0x66]	84305	1			T114	2		T116	2		T184	20
valid_sources[0x67]	83551	1			T116	3		T119	1		T121	1
valid_sources[0x68]	88551	1			T114	1		T116	4		T184	1
valid_sources[0x69]	85577	1			T114	1		T116	1		T121	5
valid_sources[0x6a]	89468	1			T114	5		T116	4		T122	5
valid_sources[0x6b]	84597	1			T114	3		T116	4		T121	1
valid_sources[0x6c]	84121	1			T116	4		T121	2		T122	6
valid_sources[0x6d]	92593	1			T114	1		T116	5		T118	3
valid_sources[0x6e]	87871	1			T116	4		T121	1		T122	7
valid_sources[0x6f]	87276	1			T114	1		T116	8		T121	2
valid_sources[0x70]	93987	1			T114	1		T116	7		T118	1
valid_sources[0x71]	83953	1			T116	1		T184	27		T121	3
valid_sources[0x72]	86729	1			T114	1		T116	5		T118	2
valid_sources[0x73]	86671	1			T18	1		T114	1		T116	2
valid_sources[0x74]	84352	1			T116	2		T121	4		T122	12
valid_sources[0x75]	84371	1			T114	1		T115	8		T116	3
valid_sources[0x76]	84914	1			T116	6		T184	3		T120	1
valid_sources[0x77]	85619	1			T116	1		T121	2		T122	12
valid_sources[0x78]	84992	1			T116	1		T121	1		T122	4
valid_sources[0x79]	87100	1			T114	1		T116	4		T183	1
valid_sources[0x7a]	87573	1			T18	1		T116	5		T121	1
valid_sources[0x7b]	87910	1			T116	3		T121	2		T122	8
valid_sources[0x7c]	82890	1			T114	3		T116	4		T121	3
valid_sources[0x7d]	89377	1			T116	6		T121	1		T122	8
valid_sources[0x7e]	81896	1			T116	6		T117	5		T121	2
valid_sources[0x7f]	92570	1			T114	1		T116	6		T120	1
valid_sources[0x80]	82631	1			T114	1		T116	3		T121	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3985100

1

T18

6

T114

44

T115

12

values[0x0]

all_enables

biggest_size

5191146

1

T18

3

T114

73

T115

3

values[0x1]

all_enables

biggest_size

5113262

1

T18

2

T114

74

T115

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	718138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

26460100

1

T114

418

T116

281

T117

94

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	6668805	1			T114	103		T116	567		T117	47
values[0x0]	9951873	1			T114	166		T116	9		T117	26
values[0x1]	10557560	1			T114	157		T116	7		T117	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	247604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

26930634

1

T114

425

T116

341

T117

94

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	104529	1			T116	4		T118	1		T186	4
valid_sources[0x01]	99892	1			T116	3		T184	3		T120	1
valid_sources[0x02]	103503	1			T116	4		T186	2		T208	2
valid_sources[0x03]	106308	1			T116	5		T184	1		T186	2
valid_sources[0x04]	109829	1			T183	2		T122	896		T186	2
valid_sources[0x05]	109133	1			T116	2		T184	4		T186	1
valid_sources[0x06]	102702	1			T116	1		T183	1		T184	4
valid_sources[0x07]	114431	1			T116	2		T183	1		T121	16
valid_sources[0x08]	104989	1			T116	7		T183	1		T185	1
valid_sources[0x09]	98261	1			T116	1		T184	1		T185	6
valid_sources[0x0a]	113254	1			T116	5		T183	1		T184	5
valid_sources[0x0b]	107423	1			T208	4		T189	2		T224	3
valid_sources[0x0c]	102840	1			T183	1		T184	8		T118	2
valid_sources[0x0d]	101680	1			T116	1		T184	2		T186	2
valid_sources[0x0e]	107920	1			T116	2		T184	2		T186	1
valid_sources[0x0f]	106277	1			T116	2		T183	1		T184	1
valid_sources[0x10]	108734	1			T116	4		T183	2		T184	1
valid_sources[0x11]	105390	1			T116	6		T183	2		T184	9
valid_sources[0x12]	102423	1			T116	3		T184	3		T185	6
valid_sources[0x13]	112185	1			T116	3		T186	1		T208	2
valid_sources[0x14]	109106	1			T183	1		T184	4		T185	3
valid_sources[0x15]	110997	1			T116	4		T186	1		T208	4
valid_sources[0x16]	103121	1			T116	6		T184	2		T186	1
valid_sources[0x17]	105921	1			T116	3		T184	2		T185	1
valid_sources[0x18]	106605	1			T183	2		T184	3		T208	5
valid_sources[0x19]	110823	1			T116	2		T184	2		T186	4
valid_sources[0x1a]	100575	1			T116	1		T184	3		T121	2
valid_sources[0x1b]	102865	1			T183	2		T184	7		T123	4
valid_sources[0x1c]	103419	1			T116	5		T184	1		T118	1
valid_sources[0x1d]	103946	1			T116	3		T183	1		T184	1
valid_sources[0x1e]	106785	1			T116	3		T183	1		T184	1
valid_sources[0x1f]	114341	1			T116	4		T184	3		T208	1
valid_sources[0x20]	101910	1			T116	1		T184	1		T118	2
valid_sources[0x21]	105540	1			T116	5		T184	2		T208	2
valid_sources[0x22]	109938	1			T116	1		T183	2		T184	3
valid_sources[0x23]	109286	1			T116	1		T183	1		T184	1
valid_sources[0x24]	101601	1			T116	1		T184	2		T118	1
valid_sources[0x25]	104200	1			T116	5		T184	2		T185	4
valid_sources[0x26]	107470	1			T116	1		T184	2		T120	2
valid_sources[0x27]	111324	1			T116	3		T184	1		T186	1
valid_sources[0x28]	102407	1			T116	3		T184	1		T118	1
valid_sources[0x29]	104625	1			T116	1		T183	1		T184	3
valid_sources[0x2a]	106467	1			T116	3		T183	2		T184	1
valid_sources[0x2b]	102997	1			T116	3		T117	17		T184	3
valid_sources[0x2c]	104781	1			T114	8		T116	2		T184	1
valid_sources[0x2d]	101246	1			T116	2		T184	1		T118	2
valid_sources[0x2e]	107592	1			T114	93		T116	2		T186	3
valid_sources[0x2f]	99794	1			T116	1		T183	1		T184	1
valid_sources[0x30]	105424	1			T116	3		T183	1		T184	1
valid_sources[0x31]	107164	1			T184	2		T186	2		T208	2
valid_sources[0x32]	104764	1			T183	1		T184	1		T118	1
valid_sources[0x33]	108225	1			T116	1		T184	5		T118	3
valid_sources[0x34]	104929	1			T116	1		T118	2		T122	384
valid_sources[0x35]	106000	1			T116	3		T183	1		T184	3
valid_sources[0x36]	108094	1			T116	2		T183	3		T208	1
valid_sources[0x37]	114890	1			T116	3		T117	1		T183	1
valid_sources[0x38]	102870	1			T116	2		T184	6		T118	1
valid_sources[0x39]	105697	1			T116	2		T117	4		T183	1
valid_sources[0x3a]	110105	1			T116	3		T183	1		T186	3
valid_sources[0x3b]	108186	1			T186	2		T208	2		T188	1
valid_sources[0x3c]	107818	1			T116	2		T183	2		T186	2
valid_sources[0x3d]	99772	1			T116	4		T120	1		T186	5
valid_sources[0x3e]	105639	1			T116	4		T183	2		T184	3
valid_sources[0x3f]	103014	1			T184	1		T186	1		T208	1
valid_sources[0x40]	113180	1			T116	1		T184	1		T121	5
valid_sources[0x41]	108470	1			T114	3		T116	3		T184	3
valid_sources[0x42]	99241	1			T114	11		T183	1		T184	1
valid_sources[0x43]	101922	1			T116	2		T183	3		T184	1
valid_sources[0x44]	105585	1			T116	1		T183	1		T184	4
valid_sources[0x45]	104177	1			T116	1		T183	1		T184	7
valid_sources[0x46]	102121	1			T116	1		T184	3		T186	2
valid_sources[0x47]	95227	1			T116	1		T183	1		T186	1
valid_sources[0x48]	100004	1			T116	3		T184	1		T186	3
valid_sources[0x49]	105417	1			T116	5		T117	31		T184	2
valid_sources[0x4a]	108252	1			T116	6		T183	2		T184	4
valid_sources[0x4b]	104378	1			T121	5		T186	3		T208	3
valid_sources[0x4c]	112078	1			T117	8		T184	1		T186	2
valid_sources[0x4d]	109221	1			T116	5		T183	2		T184	5
valid_sources[0x4e]	104457	1			T117	7		T183	1		T184	1
valid_sources[0x4f]	104753	1			T116	1		T183	1		T184	4
valid_sources[0x50]	106723	1			T116	6		T184	2		T120	1
valid_sources[0x51]	108486	1			T116	2		T183	1		T184	1
valid_sources[0x52]	110185	1			T116	1		T184	5		T186	2
valid_sources[0x53]	101374	1			T116	6		T183	1		T184	3
valid_sources[0x54]	109638	1			T116	4		T184	1		T118	1
valid_sources[0x55]	106016	1			T114	4		T116	1		T183	1
valid_sources[0x56]	111848	1			T116	4		T184	3		T208	5
valid_sources[0x57]	105697	1			T116	1		T183	1		T208	1
valid_sources[0x58]	112057	1			T116	4		T184	2		T186	3
valid_sources[0x59]	109732	1			T116	3		T183	1		T184	6
valid_sources[0x5a]	109795	1			T116	2		T183	1		T226	1
valid_sources[0x5b]	107336	1			T116	1		T184	7		T118	1
valid_sources[0x5c]	104481	1			T116	2		T184	1		T120	1
valid_sources[0x5d]	106127	1			T116	2		T184	5		T185	8
valid_sources[0x5e]	108861	1			T184	6		T208	1		T227	2
valid_sources[0x5f]	110681	1			T116	3		T184	1		T122	256
valid_sources[0x60]	97256	1			T116	2		T184	2		T120	3
valid_sources[0x61]	106344	1			T116	5		T183	1		T184	5
valid_sources[0x62]	102908	1			T116	2		T183	1		T184	2
valid_sources[0x63]	104531	1			T116	3		T184	3		T118	1
valid_sources[0x64]	107181	1			T116	3		T183	1		T184	1
valid_sources[0x65]	108162	1			T116	3		T184	1		T185	2
valid_sources[0x66]	107452	1			T116	1		T183	4		T186	1
valid_sources[0x67]	108326	1			T116	3		T184	3		T118	1
valid_sources[0x68]	107037	1			T116	3		T184	2		T186	4
valid_sources[0x69]	106440	1			T116	1		T118	1		T186	2
valid_sources[0x6a]	104624	1			T116	3		T183	3		T184	1
valid_sources[0x6b]	106427	1			T116	2		T184	2		T186	1
valid_sources[0x6c]	108788	1			T183	2		T184	1		T118	1
valid_sources[0x6d]	101369	1			T116	2		T186	1		T208	1
valid_sources[0x6e]	106986	1			T208	3		T227	1		T190	2
valid_sources[0x6f]	104441	1			T114	8		T116	1		T183	1
valid_sources[0x70]	107727	1			T116	2		T184	6		T120	1
valid_sources[0x71]	105065	1			T116	1		T185	1		T186	2
valid_sources[0x72]	107081	1			T116	3		T184	2		T186	3
valid_sources[0x73]	106281	1			T116	3		T183	2		T184	1
valid_sources[0x74]	108417	1			T116	2		T183	1		T184	3
valid_sources[0x75]	110841	1			T116	1		T183	1		T184	1
valid_sources[0x76]	104049	1			T116	4		T208	4		T227	10
valid_sources[0x77]	103914	1			T116	5		T208	4		T261	1
valid_sources[0x78]	105924	1			T116	3		T183	1		T184	1
valid_sources[0x79]	111654	1			T116	5		T183	1		T184	2
valid_sources[0x7a]	113347	1			T116	3		T183	2		T184	5
valid_sources[0x7b]	105279	1			T116	2		T185	2		T186	2
valid_sources[0x7c]	110062	1			T116	2		T184	1		T120	1
valid_sources[0x7d]	107676	1			T116	1		T184	6		T186	2
valid_sources[0x7e]	107367	1			T116	5		T184	1		T185	6
valid_sources[0x7f]	110926	1			T116	1		T183	2		T184	1
valid_sources[0x80]	110436	1			T116	4		T183	1		T208	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6656019

1

T114

103

T116

270

T117

47

values[0x0]

all_enables

biggest_size

9902394

1

T114

166

T116

7

T117

26

values[0x1]

all_enables

biggest_size

9901687

1

T114

149

T116

4

T117

21