Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

58992991

1

T18

27

T114

279

T115

20

full_word

17600028

1

T18

11

T114

209

T115

18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	76592719	1			T18	38		T114	488		T115	38
auto[TlIntgErrCmd]	96	1			T208	8		T209	6		T211	1
auto[TlIntgErrData]	108	1			T208	5		T209	1		T211	5
auto[TlIntgErrBoth]	96	1			T208	7		T209	3		T211	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11192124

1

T18

19

T114

74

T115

19

auto[1]

65400895

1

T18

19

T114

414

T115

19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6804174	1			T18	13		T114	27		T115	7
auto[TlIntgErrNone]	partial	auto[1]	52188546	1			T18	14		T114	252		T115	13
auto[TlIntgErrNone]	full_word	auto[0]	4387816	1			T18	6		T114	47		T115	12
auto[TlIntgErrNone]	full_word	auto[1]	13212183	1			T18	5		T114	162		T115	6
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T208	3		T209	4		T309	1
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T208	4		T209	1		T211	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T316	1		T313	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T208	1		T209	1		T316	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T208	3		T211	3		T309	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T208	2		T209	1		T211	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T309	1		T315	2		T317	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T311	1		T315	1		T250	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T208	2		T209	1		T310	1
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T208	4		T209	2		T211	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T314	1		T250	1		T317	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T208	1		T314	1		T315	1