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back
LINE 66
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T184,T185,T186 |
| 1 | 1 | Covered | T18,T114,T115 |
LINE 78
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T18,T114,T115 |
| 0 | 1 | Covered | T21,T22,T23 |
| 1 | 0 | Covered | T208,T209,T211 |
LINE 85
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T18,T114,T115 |
| 0 | 0 | 1 | Covered | T21,T22,T23 |
| 0 | 1 | 0 | Covered | T208,T209,T211 |
| 1 | 0 | 0 | Covered | T208,T209,T211 |
LINE 133
EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[4096:6143]}) ? 1'b0 : 1'b1)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T117 |
LINE 171
EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
-----------1---------- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T18,T114,T115 |
| 0 | 0 | 1 | Covered | T208,T209,T211 |
| 0 | 1 | 0 | Covered | T114,T183,T184 |
| 1 | 0 | 0 | Covered | T183,T184,T185 |
LINE 171
SUB-EXPRESSION (devmode_i & addrmiss)
----1---- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T18,T114,T115 |
| 1 | 1 | Covered | T183,T184,T185 |
LINE 966
EXPRESSION (direct_access_cmd_we & direct_access_regwen_qs)
----------1--------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | Covered | T124,T223,T125 |
LINE 1019
EXPRESSION (direct_access_address_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T223,T2,T3 |
| 1 | 1 | Covered | T116,T117,T118 |
LINE 1051
EXPRESSION (direct_access_wdata_0_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T223,T2,T3 |
| 1 | 1 | Covered | T116,T118,T120 |
LINE 1083
EXPRESSION (direct_access_wdata_1_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T223,T2,T3 |
| 1 | 1 | Covered | T116,T117,T118 |
LINE 1179
EXPRESSION (check_trigger_we & check_trigger_regwen_qs)
--------1------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T121,T122,T123 |
| 1 | 1 | Covered | T116,T117,T118 |
LINE 1244
EXPRESSION (check_timeout_we & check_regwen_qs)
--------1------- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T8,T11,T131 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1275
EXPRESSION (integrity_check_period_we & check_regwen_qs)
------------1------------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T116,T118,T123 |
LINE 1306
EXPRESSION (consistency_check_period_we & check_regwen_qs)
-------------1------------- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T116,T122,T123 |
LINE 1337
EXPRESSION (vendor_test_read_lock_we & direct_access_regwen_qs)
------------1----------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T223,T2,T3 |
| 1 | 1 | Covered | T124,T125,T126 |
LINE 1368
EXPRESSION (creator_sw_cfg_read_lock_we & direct_access_regwen_qs)
-------------1------------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T223,T2,T4 |
| 1 | 1 | Covered | T124,T125,T126 |
LINE 1399
EXPRESSION (owner_sw_cfg_read_lock_we & direct_access_regwen_qs)
------------1------------ -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T223,T2,T3 |
| 1 | 1 | Covered | T124,T125,T126 |
LINE 1669
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_STATE_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T115 |
LINE 1670
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_ENABLE_OFFSET)
-----------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T115 |
LINE 1671
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTR_TEST_OFFSET)
----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T115 |
LINE 1672
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ALERT_TEST_OFFSET)
-----------------------------1----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1673
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_STATUS_OFFSET)
---------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1674
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_ERR_CODE_OFFSET)
----------------------------1---------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1675
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_REGWEN_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1676
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_CMD_OFFSET)
--------------------------------1--------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1677
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_ADDRESS_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1678
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T116 |
LINE 1679
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_WDATA_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1680
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1681
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_DIRECT_ACCESS_RDATA_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1682
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_REGWEN_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1683
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TRIGGER_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1684
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_REGWEN_OFFSET)
------------------------------1-----------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1685
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CHECK_TIMEOUT_OFFSET)
------------------------------1------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1686
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_INTEGRITY_CHECK_PERIOD_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1687
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CONSISTENCY_CHECK_PERIOD_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1688
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_READ_LOCK_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1689
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_READ_LOCK_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T116 |
LINE 1690
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_READ_LOCK_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1691
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_0_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1692
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_VENDOR_TEST_DIGEST_1_OFFSET)
----------------------------------1---------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1693
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1694
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1695
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1696
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OFFSET)
----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T116 |
LINE 1697
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_0_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1698
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_HW_CFG_DIGEST_1_OFFSET)
-------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1699
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1700
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET0_DIGEST_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1701
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1702
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET1_DIGEST_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1703
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_0_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1704
EXPRESSION (reg_addr == otp_ctrl_reg_pkg::OTP_CTRL_SECRET2_DIGEST_1_OFFSET)
--------------------------------1-------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T114,T116,T117 |
LINE 1707
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T114,T115 |
| 1 | Covered | T18,T114,T115 |
LINE 1707
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T18,T114,T115 |
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T18,T114,T115 |
LINE 1711
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T18,T115,T116 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b0111 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) |
36 (addr_hit[35] & ((|(4'b1111 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|
| ALL ZEROS | Covered | T18,T114,T115 |
| 36 (addr_hit[35] & ((|(4'... | Covered | T114,T183,T184 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T114,T183,T184 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T114,T183,T184 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T114,T183,T184 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T114,T183,T184 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T114,T183,T184 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T114,T183,T184 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T114,T183,T184 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T18,T114,T117 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T114,T183,T184 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T114,T183,T184 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T114,T183,T184 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T114,T183,T184 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T114,T183,T184 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T114,T116,T183 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T18,T114,T116 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T114,T116,T183 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T114,T116,T117 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T114,T116,T183 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T114,T116,T183 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T114,T116,T183 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T114,T116,T183 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T114,T116,T117 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T114,T116,T183 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T114,T116,T183 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T114,T183,T184 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T18,T114,T183 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T114,T183,T184 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T114,T116,T183 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T114,T183,T184 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T114,T183,T184 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T114,T183,T184 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T114,T116,T183 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T18,T114,T115 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T18,T114,T116 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T18,T114,T115 |
LINE 1711
SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T18,T115,T116 |
| 1 | 1 | Covered | T18,T114,T115 |
LINE 1711
SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T18,T115,T116 |
| 1 | 1 | Covered | T18,T114,T116 |
LINE 1711
SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T18,T115,T116 |
| 1 | 1 | Covered | T18,T114,T115 |
LINE 1711
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[4] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T114,T116,T117 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T121 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T184,T118 |
| 1 | 1 | Covered | T18,T114,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T116,T117 |
LINE 1711
SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T116,T117 |
LINE 1711
SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T121 |
| 1 | 1 | Covered | T18,T114,T116 |
LINE 1711
SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T116,T183 |
LINE 1711
SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T18,T114,T117 |
LINE 1711
SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[29] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[30] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T114,T116,T117 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[31] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[32] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T184 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1711
SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | Covered | T116,T117,T118 |
| 1 | 1 | Covered | T114,T183,T184 |
LINE 1751
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T18,T114,T115 |
| 1 | 1 | 0 | Covered | T114,T184,T186 |
| 1 | 1 | 1 | Covered | T18,T115,T119 |
LINE 1756
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T18,T114,T115 |
| 1 | 1 | 0 | Covered | T184,T186,T224 |
| 1 | 1 | 1 | Covered | T18,T115,T116 |
LINE 1761
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T18,T114,T115 |
| 1 | 1 | 0 | Covered | T114,T183,T184 |
| 1 | 1 | 1 | Covered | T18,T115,T119 |
LINE 1766
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T114,T183,T184 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1777
EXPRESSION (addr_hit[4] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1778
EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1779
EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T187,T188,T189 |
LINE 1780
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T183,T184,T185 |
| 1 | 1 | 1 | Covered | T124,T223,T125 |
LINE 1787
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T186,T224,T225 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1790
EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T18,T114,T116 |
| 1 | 1 | 0 | Covered | T184,T185,T224 |
| 1 | 1 | 1 | Covered | T116,T118,T120 |
LINE 1793
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T114,T183,T185 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1796
EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1797
EXPRESSION (addr_hit[12] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1798
EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T114,T183,T186 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1801
EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T114,T184,T185 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1806
EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T183,T184,T185 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1809
EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T183,T184,T185 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1812
EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T183,T184,T186 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1815
EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T183,T184,T185 |
| 1 | 1 | 1 | Covered | T116,T117,T118 |
LINE 1818
EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T183,T184,T185 |
| 1 | 1 | 1 | Covered | T124,T223,T125 |
LINE 1821
EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T18,T114,T116 |
| 1 | 1 | 0 | Covered | T183,T184,T185 |
| 1 | 1 | 1 | Covered | T124,T223,T125 |
LINE 1824
EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T115,T116 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Covered | T183,T185,T186 |
| 1 | 1 | 1 | Covered | T124,T223,T125 |
LINE 1827
EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1828
EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1829
EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1830
EXPRESSION (addr_hit[25] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1831
EXPRESSION (addr_hit[26] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1832
EXPRESSION (addr_hit[27] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T18,T114,T116 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1833
EXPRESSION (addr_hit[28] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1834
EXPRESSION (addr_hit[29] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1835
EXPRESSION (addr_hit[30] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1836
EXPRESSION (addr_hit[31] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1837
EXPRESSION (addr_hit[32] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1838
EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1839
EXPRESSION (addr_hit[34] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T18,T114,T115 |
| 1 | 0 | 1 | Covered | T114,T116,T117 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T1,T2,T3 |