Unified Coverage Report :: Module :: otp_ctrl_core_reg_top

Module : otp_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.87	100.00	95.48			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	98.87	100.00	95.48			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.87	100.00	95.48			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.28	99.59	96.83	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.90	97.18	88.57	96.76		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_check_error	100.00	100.00
u_alert_test_fatal_macro_error	100.00	100.00
u_alert_test_fatal_prim_otp_alert	100.00	100.00
u_alert_test_recov_prim_otp_alert	100.00	100.00
u_check_regwen	100.00	100.00	100.00			100.00
u_check_timeout	100.00	100.00	100.00			100.00
u_check_trigger_consistency	100.00	100.00
u_check_trigger_integrity	100.00	100.00
u_check_trigger_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_consistency_check_period	100.00	100.00	100.00			100.00
u_creator_sw_cfg_digest_0	100.00	100.00
u_creator_sw_cfg_digest_1	100.00	100.00
u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_direct_access_address	100.00	100.00	100.00			100.00
u_direct_access_cmd_digest	100.00	100.00
u_direct_access_cmd_rd	100.00	100.00
u_direct_access_cmd_wr	100.00	100.00
u_direct_access_rdata_0	100.00	100.00
u_direct_access_rdata_1	100.00	100.00
u_direct_access_regwen	100.00	100.00
u_direct_access_wdata_0	100.00	100.00	100.00			100.00
u_direct_access_wdata_1	100.00	100.00	100.00			100.00
u_err_code_err_code_0	100.00	100.00
u_err_code_err_code_1	100.00	100.00
u_err_code_err_code_2	100.00	100.00
u_err_code_err_code_3	100.00	100.00
u_err_code_err_code_4	100.00	100.00
u_err_code_err_code_5	100.00	100.00
u_err_code_err_code_6	100.00	100.00
u_err_code_err_code_7	100.00	100.00
u_err_code_err_code_8	100.00	100.00
u_err_code_err_code_9	100.00	100.00
u_hw_cfg_digest_0	100.00	100.00
u_hw_cfg_digest_1	100.00	100.00
u_integrity_check_period	100.00	100.00	100.00			100.00
u_intr_enable_otp_error	100.00	100.00	100.00			100.00
u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_state_otp_error	100.00	100.00	100.00			100.00
u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_test_otp_error	100.00	100.00
u_intr_test_otp_operation_done	100.00	100.00
u_owner_sw_cfg_digest_0	100.00	100.00
u_owner_sw_cfg_digest_1	100.00	100.00
u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_secret0_digest_0	100.00	100.00
u_secret0_digest_1	100.00	100.00
u_secret1_digest_0	100.00	100.00
u_secret1_digest_1	100.00	100.00
u_secret2_digest_0	100.00	100.00
u_secret2_digest_1	100.00	100.00
u_socket	99.24	98.75	98.21			100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_check_pending	100.00	100.00
u_status_creator_sw_cfg_error	100.00	100.00
u_status_dai_error	100.00	100.00
u_status_dai_idle	100.00	100.00
u_status_hw_cfg_error	100.00	100.00
u_status_key_deriv_fsm_error	100.00	100.00
u_status_lci_error	100.00	100.00
u_status_lfsr_fsm_error	100.00	100.00
u_status_life_cycle_error	100.00	100.00
u_status_owner_sw_cfg_error	100.00	100.00
u_status_scrambling_fsm_error	100.00	100.00
u_status_secret0_error	100.00	100.00
u_status_secret1_error	100.00	100.00
u_status_secret2_error	100.00	100.00
u_status_timeout_error	100.00	100.00
u_status_vendor_test_error	100.00	100.00
u_vendor_test_digest_0	100.00	100.00
u_vendor_test_digest_1	100.00	100.00
u_vendor_test_read_lock	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		255	255	100.00
ALWAYS	76	4	4	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
ALWAYS	133	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	499	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	531	1	1	100.00
CONT_ASSIGN	963	1	1	100.00
CONT_ASSIGN	966	1	1	100.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	997	1	1	100.00
CONT_ASSIGN	1013	1	1	100.00
CONT_ASSIGN	1019	1	1	100.00
CONT_ASSIGN	1051	1	1	100.00
CONT_ASSIGN	1083	1	1	100.00
CONT_ASSIGN	1176	1	1	100.00
CONT_ASSIGN	1179	1	1	100.00
CONT_ASSIGN	1194	1	1	100.00
CONT_ASSIGN	1210	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1368	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
ALWAYS	1668	37	37	100.00
CONT_ASSIGN	1707	1	1	100.00
ALWAYS	1711	1	1	100.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1753	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1758	1	1	100.00
CONT_ASSIGN	1760	1	1	100.00
CONT_ASSIGN	1761	1	1	100.00
CONT_ASSIGN	1763	1	1	100.00
CONT_ASSIGN	1765	1	1	100.00
CONT_ASSIGN	1766	1	1	100.00
CONT_ASSIGN	1768	1	1	100.00
CONT_ASSIGN	1770	1	1	100.00
CONT_ASSIGN	1772	1	1	100.00
CONT_ASSIGN	1774	1	1	100.00
CONT_ASSIGN	1776	1	1	100.00
CONT_ASSIGN	1777	1	1	100.00
CONT_ASSIGN	1778	1	1	100.00
CONT_ASSIGN	1779	1	1	100.00
CONT_ASSIGN	1780	1	1	100.00
CONT_ASSIGN	1782	1	1	100.00
CONT_ASSIGN	1784	1	1	100.00
CONT_ASSIGN	1786	1	1	100.00
CONT_ASSIGN	1787	1	1	100.00
CONT_ASSIGN	1789	1	1	100.00
CONT_ASSIGN	1790	1	1	100.00
CONT_ASSIGN	1792	1	1	100.00
CONT_ASSIGN	1793	1	1	100.00
CONT_ASSIGN	1795	1	1	100.00
CONT_ASSIGN	1796	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1798	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1808	1	1	100.00
CONT_ASSIGN	1809	1	1	100.00
CONT_ASSIGN	1811	1	1	100.00
CONT_ASSIGN	1812	1	1	100.00
CONT_ASSIGN	1814	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1818	1	1	100.00
CONT_ASSIGN	1820	1	1	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1826	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1829	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1831	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1833	1	1	100.00
CONT_ASSIGN	1834	1	1	100.00
CONT_ASSIGN	1835	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1837	1	1	100.00
CONT_ASSIGN	1838	1	1	100.00
CONT_ASSIGN	1839	1	1	100.00
CONT_ASSIGN	1840	1	1	100.00
ALWAYS	1844	37	37	100.00
ALWAYS	1885	73	73	100.00
CONT_ASSIGN	2077	0	0
CONT_ASSIGN	2085	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
76	1	1
77	1	1
78	1	1
79	1	1
			MISSING_ELSE
85	1	1
103	1	1
104	1	1
106	1	1
107	1	1
133	1	1
139	1	1
140	1	1
			MISSING_ELSE
170	1	1
171	1	1
415	1	1
430	1	1
446	1	1
452	1	1
467	1	1
483	1	1
499	1	1
515	1	1
531	1	1
963	1	1
966	1	1
981	1	1
997	1	1
1013	1	1
1019	1	1
1051	1	1
1083	1	1
1176	1	1
1179	1	1
1194	1	1
1210	1	1
1244	1	1
1275	1	1
1306	1	1
1337	1	1
1368	1	1
1399	1	1
1668	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1676	1	1
1677	1	1
1678	1	1
1679	1	1
1680	1	1
1681	1	1
1682	1	1
1683	1	1
1684	1	1
1685	1	1
1686	1	1
1687	1	1
1688	1	1
1689	1	1
1690	1	1
1691	1	1
1692	1	1
1693	1	1
1694	1	1
1695	1	1
1696	1	1
1697	1	1
1698	1	1
1699	1	1
1700	1	1
1701	1	1
1702	1	1
1703	1	1
1704	1	1
1707	1	1
1711	1	1
1751	1	1
1753	1	1
1755	1	1
1756	1	1
1758	1	1
1760	1	1
1761	1	1
1763	1	1
1765	1	1
1766	1	1
1768	1	1
1770	1	1
1772	1	1
1774	1	1
1776	1	1
1777	1	1
1778	1	1
1779	1	1
1780	1	1
1782	1	1
1784	1	1
1786	1	1
1787	1	1
1789	1	1
1790	1	1
1792	1	1
1793	1	1
1795	1	1
1796	1	1
1797	1	1
1798	1	1
1800	1	1
1801	1	1
1803	1	1
1805	1	1
1806	1	1
1808	1	1
1809	1	1
1811	1	1
1812	1	1
1814	1	1
1815	1	1
1817	1	1
1818	1	1
1820	1	1
1821	1	1
1823	1	1
1824	1	1
1826	1	1
1827	1	1
1828	1	1
1829	1	1
1830	1	1
1831	1	1
1832	1	1
1833	1	1
1834	1	1
1835	1	1
1836	1	1
1837	1	1
1838	1	1
1839	1	1
1840	1	1
1844	1	1
1845	1	1
1846	1	1
1847	1	1
1848	1	1
1849	1	1
1850	1	1
1851	1	1
1852	1	1
1853	1	1
1854	1	1
1855	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1866	1	1
1867	1	1
1868	1	1
1869	1	1
1870	1	1
1871	1	1
1872	1	1
1873	1	1
1874	1	1
1875	1	1
1876	1	1
1877	1	1
1878	1	1
1879	1	1
1880	1	1
1885	1	1
1886	1	1
1888	1	1
1889	1	1
1893	1	1
1894	1	1
1898	1	1
1899	1	1
1903	1	1
1904	1	1
1905	1	1
1906	1	1
1907	1	1
1911	1	1
1912	1	1
1913	1	1
1914	1	1
1915	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1924	1	1
1925	1	1
1926	1	1
1927	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1944	1	1
1948	1	1
1949	1	1
1950	1	1
1954	1	1
1958	1	1
1962	1	1
1966	1	1
1970	1	1
1974	1	1
1978	1	1
1979	1	1
1983	1	1
1987	1	1
1991	1	1
1995	1	1
1999	1	1
2003	1	1
2007	1	1
2011	1	1
2015	1	1
2019	1	1
2023	1	1
2027	1	1
2031	1	1
2035	1	1
2039	1	1
2043	1	1
2047	1	1
2051	1	1
2055	1	1
2059	1	1
2063	1	1
2077		unreachable
2085	1	1
2086	1	1

---

Cond Coverage for Module : otp_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	420	401	95.48
Logical	420	401	95.48
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
66-1839	95.67
1840	75.00

---

Branch Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		46	46	100.00
TERNARY	1707	2	2	100.00
IF	76	3	3	100.00
TERNARY	133	2	2	100.00
IF	139	2	2	100.00
CASE	1886	37	37	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1707	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T114,T115
0	Covered	T18,T114,T115

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T114,T115
0	1	Covered	T208,T209,T211
0	0	Covered	T18,T114,T115

	LineNo.	Expression
-1-:	133	((tl_i.a_address[(AW - 1):0] inside {[4096:6143]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T114,T117
0	Covered	T18,T114,T115

	LineNo.	Expression
-1-:	139	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T208,T209,T211
0	Covered	T18,T114,T115

	LineNo.	Expression
-1-:	1886	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T18,T114,T115
addr_hit[1]	Covered	T18,T114,T115
addr_hit[2]	Covered	T18,T114,T115
addr_hit[3]	Covered	T114,T115,T116
addr_hit[4]	Covered	T114,T115,T116
addr_hit[5]	Covered	T114,T115,T116
addr_hit[6]	Covered	T114,T115,T116
addr_hit[7]	Covered	T114,T115,T116
addr_hit[8]	Covered	T114,T115,T116
addr_hit[9]	Covered	T18,T114,T115
addr_hit[10]	Covered	T114,T115,T116
addr_hit[11]	Covered	T114,T115,T116
addr_hit[12]	Covered	T114,T115,T116
addr_hit[13]	Covered	T114,T115,T116
addr_hit[14]	Covered	T114,T115,T116
addr_hit[15]	Covered	T114,T115,T116
addr_hit[16]	Covered	T114,T115,T116
addr_hit[17]	Covered	T114,T115,T116
addr_hit[18]	Covered	T114,T115,T116
addr_hit[19]	Covered	T114,T115,T116
addr_hit[20]	Covered	T18,T114,T115
addr_hit[21]	Covered	T114,T115,T116
addr_hit[22]	Covered	T114,T115,T116
addr_hit[23]	Covered	T114,T115,T116
addr_hit[24]	Covered	T114,T115,T116
addr_hit[25]	Covered	T114,T115,T116
addr_hit[26]	Covered	T114,T115,T116
addr_hit[27]	Covered	T18,T114,T115
addr_hit[28]	Covered	T114,T115,T116
addr_hit[29]	Covered	T114,T115,T116
addr_hit[30]	Covered	T114,T115,T116
addr_hit[31]	Covered	T114,T115,T116
addr_hit[32]	Covered	T114,T115,T116
addr_hit[33]	Covered	T114,T115,T116
addr_hit[34]	Covered	T114,T115,T116
addr_hit[35]	Covered	T114,T115,T116
default	Covered	T18,T114,T115

---

Assert Coverage for Module : otp_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1910540985	6586592	0	0
reAfterRv	1910540985	6586585	0	0
rePulse	1910540985	3848133	0	0
wePulse	1910540985	2738452	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1910540985	6586592	0	0
T18	3702	38	0	0
T114	5238	10	0	0
T115	4491	38	0	0
T116	5356	1123	0	0
T117	4470	268	0	0
T118	4114	83	0	0
T119	3570	38	0	0
T120	3728	38	0	0
T183	6893	38	0	0
T184	6847	52	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1910540985	6586585	0	0
T18	3702	38	0	0
T114	5238	10	0	0
T115	4491	38	0	0
T116	5356	1123	0	0
T117	4470	268	0	0
T118	4114	83	0	0
T119	3570	38	0	0
T120	3728	38	0	0
T183	6893	38	0	0
T184	6847	52	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1910540985	3848133	0	0
T18	3702	19	0	0
T114	5238	1	0	0
T115	4491	19	0	0
T116	5356	1065	0	0
T117	4470	104	0	0
T118	4114	25	0	0
T119	3570	19	0	0
T120	3728	11	0	0
T183	6893	5	0	0
T184	6847	9	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1910540985	2738452	0	0
T18	3702	19	0	0
T114	5238	9	0	0
T115	4491	19	0	0
T116	5356	58	0	0
T117	4470	164	0	0
T118	4114	58	0	0
T119	3570	19	0	0
T120	3728	27	0	0
T183	6893	33	0	0
T184	6847	43	0	0