Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1306020
Category 01306020

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1306020
Severity 01306020

Summary for Assertions
NUMBERPERCENT
Total Number1306100.00
Uncovered463.52
Success126096.48
Failure00.00
Incomplete100.77
Without Attempts40.31

Summary for Cover Sequences
NUMBERPERCENT
Total Number20100.00
Uncovered00.00
All Matches20100.00
First Matches20100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 00210099508513506801300
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 0021009950854610108900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 0021009950855634056900
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 0021009950856701343400
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 0021009950857872744400
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 002100995085210011902200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001333133300
tb.dut.u_reg_core.u_socket.maxN 001333133300
tb.dut.u_reg_core.wePulse 002100995085286560000
tb.dut.u_scrmbl_mtx.CheckHotOne_A 002098301949209747590100
tb.dut.u_scrmbl_mtx.CheckNGreaterZero_A 001160116000
tb.dut.u_scrmbl_mtx.GrantKnown_A 002098301949209747590100
tb.dut.u_scrmbl_mtx.IdxKnown_A 002098301949209747590100
tb.dut.u_scrmbl_mtx.NoReadyValidNoGrant_A 002098301949206044009500
tb.dut.u_scrmbl_mtx.ReqImpliesValid_A 0020983019493703580600
tb.dut.u_scrmbl_mtx.ValidKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.AddrOutKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.DataIntgOptions_A 001160116000
tb.dut.u_tlul_adapter_sram.ReqOutKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.SramDwHasByteGranularity_A 001160116000
tb.dut.u_tlul_adapter_sram.SramDwIsMultipleOfTlulWidth_A 001160116000
tb.dut.u_tlul_adapter_sram.TlOutKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_A 0020983019495631622800
tb.dut.u_tlul_adapter_sram.TlOutPayloadKnown_AKnownEnable 002098301949209747590100
tb.dut.u_tlul_adapter_sram.WdataOutKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.WeOutKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.WmaskOutKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.adapterNoReadOrWrite 001160116000
tb.dut.u_tlul_adapter_sram.rvalidHighReqFifoEmpty 0020983019499738700
tb.dut.u_tlul_adapter_sram.rvalidHighWhenRspFifoFull 0020983019499738700
tb.dut.u_tlul_adapter_sram.u_err.dataWidthOnly32_A 001160116000
tb.dut.u_tlul_adapter_sram.u_reqfifo.DataKnown_A 0020983019495691933400
tb.dut.u_tlul_adapter_sram.u_reqfifo.DepthKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_reqfifo.RvalidKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_reqfifo.WreadyKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 0020983019495691933400
tb.dut.u_tlul_adapter_sram.u_rsp_gen.DataWidthCheck_A 001160116000
tb.dut.u_tlul_adapter_sram.u_rsp_gen.PayLoadWidthCheck 001160116000
tb.dut.u_tlul_adapter_sram.u_rspfifo.DataKnown_A 00209830194925709200
tb.dut.u_tlul_adapter_sram.u_rspfifo.DepthKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_rspfifo.RvalidKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_rspfifo.WreadyKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00209830194925709200
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DataKnown_A 00209830194970049300
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.DepthKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.RvalidKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.WreadyKnown_A 002098301949209747590100
tb.dut.u_tlul_adapter_sram.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00209830194970049300
tb.dut.u_tlul_lc_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001160116000
tb.dut.u_tlul_lc_gate.u_err_en_sync.OutputsKnown_A 002098301949209747590100
tb.dut.u_tlul_lc_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 002098301949209747590100
tb.dut.u_tlul_lc_gate.u_state_regs.AssertConnected_A 001160116000
tb.dut.u_tlul_lc_gate.u_state_regs_A 002098301949209747590100
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001160116000
tb.dut.u_tlul_lc_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001160116000

Assertions Incomplete:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.u_edn_arb.RoundRobin_A 002098301949001160
tb.dut.u_otp_arb.RoundRobin_A 002098301949001160
tb.dut.u_otp_ctrl_kdi.u_req_arb.RoundRobin_A 002098301949001160
tb.dut.u_prim_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A 002098301949001160
tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.OutputDelay_A 002098301949209743696203480
tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.OutputDelay_A 002098301949209743696203480
tb.dut.u_prim_lc_sync_dft_en.gen_flops.OutputDelay_A 002098301949209743696203480
tb.dut.u_prim_lc_sync_escalate_en.gen_flops.OutputDelay_A 002098301949209743696203480
tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.OutputDelay_A 002098301949209743696203480
tb.dut.u_scrmbl_mtx.RoundRobin_A 002098301949001160

Assertions Without Attempts:
ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETESRC
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.OtpErrorState_A 000000
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.OtpErrorState_A 000000

Detail Report for Cover Sequences

Cover Sequences All Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021009960308378370
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021009960302412410
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021009960302422420
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0021009960301701700
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00210099603024240
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0021009960301251250
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00210099603078780
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002100996030272727270
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 002100996030815981590
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 002100996030178420017842001242
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021009960303203200
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021009960301121120
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021009960301151150
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00210099603080800
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 002100996030330
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00210099603066660
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00210099603025250
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0021009960309729720
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 002100996030364436440
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 002100996030531225312275

Cover Sequences First Matches:
COVER SEQUENCESCATEGORYSEVERITYATTEMPTSALL MATCHESFIRST MATCHESINCOMPLETESRC
tb.dut.core_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021009960308378370
tb.dut.core_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021009960302412410
tb.dut.core_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021009960302422420
tb.dut.core_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 0021009960301701700
tb.dut.core_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 00210099603024240
tb.dut.core_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 0021009960301251250
tb.dut.core_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00210099603078780
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 002100996030272727270
tb.dut.core_tlul_assert_device.gen_device_cov.b2bReq_C 002100996030815981590
tb.dut.core_tlul_assert_device.gen_device_cov.b2bSameSource_C 002100996030178420017842001242
tb.dut.prim_tlul_assert_device.gen_device_cov.aValidNotAccepted_C 0021009960303203200
tb.dut.prim_tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C 0021009960301121120
tb.dut.prim_tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C 0021009960301151150
tb.dut.prim_tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C 00210099603080800
tb.dut.prim_tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C 002100996030330
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C 00210099603066660
tb.dut.prim_tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C 00210099603025250
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C 0021009960309729720
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bReq_C 002100996030364436440
tb.dut.prim_tlul_assert_device.gen_device_cov.b2bSameSource_C 002100996030531225312275