Unified Coverage Report :: Module :: tlul_err

Module : tlul_err

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_err	100.00	100.00	100.00			100.00	100.00
tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg_core.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.91	100.00	95.65			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.12	100.00	84.48			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.91	100.00	95.65			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Module : tlul_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T108
0	0	1	Covered	T107,T185,T200
0	1	0	Covered	T185,T190,T192
1	0	0	Covered	T13,T107,T185

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T107,T185,T200
1	0	Covered	T13,T107,T185
1	1	Covered	T13,T107,T108

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T185
0	0	1	Covered	T13,T107,T108
0	1	0	Covered	T13,T107,T108
1	0	0	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T13,T107,T185
1	Covered	T13,T107,T185

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T13,T107,T185
1	Covered	T13,T107,T185

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T107,T185,T200
1	0	1	Covered	T107,T185,T200
1	1	0	Covered	T13,T107,T185
1	1	1	Covered	T13,T107,T108

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T108
0	0	1	Covered	T13,T107,T108
0	1	0	Covered	T13,T107,T185
1	0	0	Covered	T13,T107,T185

---

Branch Coverage for Module : tlul_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T13,T107,T185
1	'h1	1	-	Covered	T13,T107,T185
1	'h1	0	-	Covered	T13,T107,T185
1	'h1	-	1	Covered	T13,T107,T185
1	'h1	-	0	Covered	T13,T107,T185
1	'h00000002	-	-	Covered	T13,T107,T108
1	default	-	-	Covered	T185,T190,T192
0	-	-	-	Covered	T13,T107,T108

---

Assert Coverage for Module : tlul_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	3826	3826	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3826	3826	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T13	2	2	0	0
T107	2	2	0	0
T108	2	2	0	0
T183	2	2	0	0
T184	2	2	0	0
T185	2	2	0	0
T186	2	2	0	0
T187	2	2	0	0
T188	2	2	0	0
T189	2	2	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T108
0	0	1	Covered	T107,T185,T200
0	1	0	Covered	T185,T190,T192
1	0	0	Covered	T13,T107,T185

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T107,T185,T200
1	0	Covered	T107,T185,T186
1	1	Covered	T13,T107,T108

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T185
0	0	1	Covered	T13,T107,T108
0	1	0	Covered	T13,T107,T108
1	0	0	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T13,T107,T185
1	Covered	T13,T107,T185

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T13,T107,T185
1	Covered	T13,T107,T185

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T107,T185,T201
1	0	1	Covered	T107,T185,T200
1	1	0	Covered	T13,T107,T185
1	1	1	Covered	T13,T107,T108

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T185
0	0	1	Covered	T13,T107,T108
0	1	0	Covered	T13,T107,T185
1	0	0	Covered	T13,T107,T185

---

Branch Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T13,T107,T185
1	'h1	1	-	Covered	T13,T107,T185
1	'h1	0	-	Covered	T13,T107,T185
1	'h1	-	1	Covered	T13,T107,T185
1	'h1	-	0	Covered	T13,T107,T185
1	'h00000002	-	-	Covered	T13,T107,T108
1	default	-	-	Covered	T185,T190,T192
0	-	-	-	Covered	T13,T107,T108

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1333	1333	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1333	1333	0	0
T13	1	1	0	0
T107	1	1	0	0
T108	1	1	0	0
T183	1	1	0	0
T184	1	1	0	0
T185	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T188	1	1	0	0
T189	1	1	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T4
0	0	1	Covered	T1,T4,T11
0	1	0	Covered	T1,T4,T11
1	0	0	Covered	T1,T2,T3

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T4,T11
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T4,T11

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T1,T4,T11
1	Covered	T1,T4,T11

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T11
1	0	1	Covered	T1,T4,T11
1	1	0	Covered	T1,T4,T11
1	1	1	Covered	T1,T2,T4

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T11
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T1,T4,T11
1	'h1	1	-	Covered	T1,T4,T11
1	'h1	0	-	Covered	T1,T4,T11
1	'h1	-	1	Covered	T1,T4,T11
1	'h1	-	0	Covered	T1,T4,T11
1	'h00000002	-	-	Covered	T1,T2,T4
1	default	-	-	Covered	T1,T4,T11
0	-	-	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1160	1160	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Line No.	Total	Covered	Percent
TOTAL		26	26	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	32	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
CONT_ASSIGN	39	1	1	100.00
CONT_ASSIGN	42	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
ALWAYS	56	17	17	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
26	1	1
27	1	1
28	1	1
32	1	1
36	1	1
39	1	1
42	1	1
53	1	1
56	1	1
57	1	1
58	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
69	1	1
71	1	1
73	1	1
77	1	1
78	1	1
79	1	1
89	1	1
90	1	1
91	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T108
0	0	1	Covered	T107,T185,T200
0	1	0	Covered	T185,T190,T192
1	0	0	Covered	T13,T107,T185

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T107,T185,T190
1	0	Covered	T13,T107,T108
1	1	Covered	T13,T107,T108

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T185
0	0	1	Covered	T13,T107,T108
0	1	0	Covered	T13,T107,T108
1	0	0	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------

-1-	Status	Tests
0	Covered	T13,T107,T108
1	Covered	T13,T107,T108

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------

-1-	Status	Tests
0	Covered	T13,T107,T185
1	Covered	T13,T107,T185

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------

-1-	Status	Tests
0	Covered	T13,T107,T185
1	Covered	T13,T107,T185

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T185,T200,T190
1	0	1	Covered	T185,T200,T190
1	1	0	Covered	T13,T107,T185
1	1	1	Covered	T13,T107,T108

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T13,T107,T108
0	0	1	Covered	T13,T107,T108
0	1	0	Covered	T13,T107,T185
1	0	0	Covered	T13,T107,T185

---

Branch Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	8	8	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	'h0	-	-	Covered	T13,T107,T185
1	'h1	1	-	Covered	T13,T107,T185
1	'h1	0	-	Covered	T13,T107,T185
1	'h1	-	1	Covered	T13,T107,T185
1	'h1	-	0	Covered	T13,T107,T185
1	'h00000002	-	-	Covered	T13,T107,T108
1	default	-	-	Covered	T185,T190,T192
0	-	-	-	Covered	T13,T107,T108

---

Assert Coverage for Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
dataWidthOnly32_A	1333	1333	0	0

dataWidthOnly32_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1333	1333	0	0
T13	1	1	0	0
T107	1	1	0	0
T108	1	1	0	0
T183	1	1	0	0
T184	1	1	0	0
T185	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T188	1	1	0	0
T189	1	1	0	0