Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(8,32'sh00000096,32'sh00000069)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.07	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

28 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if	10.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if	20.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if	90.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if	100.00	1	100	1	64	64
mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
10.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	9	1	10.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	9	1	10.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
20.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	8	2	20.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	8	2	20.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	1	9	90.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	1	9	90.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_creator_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_hw_cfg_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_owner_sw_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret0_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret1_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.dai_vendor_test_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.owner_sw_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.secret2_write_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

---

Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00

Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.vendor_test_read_lock_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	10	0	10	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	9	1	10.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1
true	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

13614

1

T13

21

T107

21

T108

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	8	2	20.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
others[4]	0	1	1
others[5]	0	1	1
others[6]	0	1	1
others[7]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

9783

1

T13

21

T107

21

T108

1

true

15817

1

T13

21

T107

21

T108

1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	80	1			T53	4		T87	2		T93	2
others[1]	84	1			T85	2		T180	2		T66	2
others[2]	104	1			T84	2		T181	2		T182	2
others[3]	80	1			T181	2		T182	2		T163	2
others[4]	92	1			T29	2		T85	2		T163	4
others[5]	94	1			T83	2		T182	2		T350	2
others[6]	85	1			T125	3		T84	2		T85	2
others[7]	116	1			T86	2		T42	2		T180	2
false	13613	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	106	1			T91	2		T93	2		T180	2
others[1]	88	1			T84	4		T85	2		T180	2
others[2]	76	1			T30	2		T351	2		T352	4
others[3]	76	1			T85	2		T93	2		T66	2
others[4]	82	1			T100	2		T89	2		T91	2
others[5]	68	1			T42	2		T353	2		T163	2
others[6]	66	1			T29	2		T85	2		T86	2
others[7]	90	1			T85	2		T354	2		T355	2
false	13614	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	114	1			T85	2		T162	2		T352	2
others[1]	92	1			T84	2		T85	4		T163	4
others[2]	106	1			T6	2		T54	2		T181	2
others[3]	68	1			T87	2		T180	2		T181	2
others[4]	96	1			T160	2		T181	2		T351	2
others[5]	84	1			T85	2		T182	2		T163	2
others[6]	82	1			T83	4		T356	2		T163	6
others[7]	90	1			T160	2		T180	2		T66	2
false	13614	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	72	1			T357	2		T210	2		T358	2
others[1]	76	1			T29	2		T84	2		T180	2
others[2]	74	1			T29	2		T92	2		T166	2
others[3]	70	1			T84	2		T163	4		T352	2
others[4]	72	1			T85	4		T91	2		T161	2
others[5]	68	1			T92	2		T93	2		T180	2
others[6]	70	1			T87	2		T90	2		T163	2
others[7]	100	1			T86	4		T42	2		T93	4
false	13614	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	58	1			T85	2		T182	2		T350	2
others[1]	80	1			T91	2		T93	2		T163	2
others[2]	80	1			T85	2		T65	2		T359	2
others[3]	76	1			T30	2		T86	2		T89	2
others[4]	92	1			T91	2		T182	2		T351	2
others[5]	70	1			T87	2		T161	2		T352	2
others[6]	82	1			T53	2		T83	2		T84	2
others[7]	118	1			T84	2		T85	2		T86	2
false	13614	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	74	1			T29	2		T83	2		T87	2
others[1]	74	1			T84	2		T87	2		T42	2
others[2]	68	1			T53	2		T84	2		T93	2
others[3]	66	1			T30	2		T88	2		T360	2
others[4]	84	1			T84	2		T87	2		T351	4
others[5]	82	1			T53	2		T42	2		T91	2
others[6]	72	1			T29	2		T90	2		T163	2
others[7]	114	1			T87	2		T93	2		T162	2
false	13614	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	74	1			T85	2		T42	2		T162	2
others[1]	74	1			T86	2		T87	2		T351	2
others[2]	74	1			T83	2		T84	2		T93	2
others[3]	94	1			T53	2		T84	2		T361	2
others[4]	84	1			T91	2		T93	2		T161	2
others[5]	92	1			T30	2		T87	2		T90	2
others[6]	62	1			T85	2		T42	2		T91	2
others[7]	100	1			T53	2		T85	2		T87	2
false	13614	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	1	9	90.00

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30	1			T91	2		T166	2		T362	2
others[1]	18	1			T162	2		T163	4		T144	2
others[2]	20	1			T163	2		T363	2		T144	2
others[3]	18	1			T85	2		T43	2		T364	4
others[4]	14	1			T362	2		T365	2		T366	2
others[5]	26	1			T85	2		T161	2		T44	2
others[6]	32	1			T165	4		T144	2		T367	2
others[7]	30	1			T160	2		T164	2		T368	4
false	13614	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	29	1			T11	1		T65	2		T163	2
others[1]	35	1			T29	2		T27	1		T119	1
others[2]	29	1			T4	1		T71	1		T322	1
others[3]	46	1			T71	1		T27	1		T28	2
others[4]	22	1			T71	1		T28	1		T369	1
others[5]	25	1			T11	1		T28	2		T324	1
others[6]	40	1			T11	1		T267	1		T370	3
others[7]	48	1			T11	2		T125	3		T71	1
false	13613	1			T13	21		T107	21		T108	1
true	2132	1			T1	5		T4	2		T7	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35	1			T28	2		T353	2		T267	1
others[1]	40	1			T11	3		T125	3		T28	1
others[2]	35	1			T71	2		T27	1		T118	1
others[3]	23	1			T29	2		T267	1		T219	1
others[4]	33	1			T119	1		T324	1		T370	1
others[5]	28	1			T28	1		T119	1		T322	1
others[6]	30	1			T4	1		T71	1		T28	2
others[7]	51	1			T11	2		T71	1		T27	2
false	11059	1			T13	21		T107	21		T108	1
true	17933	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	87	1			T125	3		T83	2		T87	2
others[1]	80	1			T85	2		T42	2		T181	2
others[2]	78	1			T53	4		T353	2		T356	2
others[3]	100	1			T29	2		T84	2		T85	2
others[4]	84	1			T85	2		T371	2		T163	6
others[5]	102	1			T180	2		T350	2		T163	2
others[6]	94	1			T84	2		T180	2		T351	2
others[7]	110	1			T86	2		T87	2		T93	2
false	7308	1			T13	21		T107	21		T108	1
true	15880	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	82	1			T30	2		T85	2		T86	2
others[1]	88	1			T91	4		T92	2		T182	2
others[2]	104	1			T85	2		T93	2		T180	4
others[3]	72	1			T84	2		T360	2		T166	2
others[4]	82	1			T85	2		T93	2		T162	2
others[5]	80	1			T163	2		T352	2		T354	2
others[6]	64	1			T29	2		T85	2		T351	2
others[7]	80	1			T84	2		T88	2		T160	2
false	6760	1			T13	21		T107	21		T108	1
true	15689	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	28	1			T219	2		T203	1		T222	1
others[1]	36	1			T15	1		T119	1		T372	1
others[2]	40	1			T4	1		T11	1		T15	1
others[3]	28	1			T71	1		T182	2		T324	1
others[4]	38	1			T27	1		T322	1		T316	1
others[5]	29	1			T71	1		T27	1		T28	1
others[6]	34	1			T4	1		T11	1		T27	1
others[7]	21	1			T324	1		T267	1		T219	1
false	11012	1			T13	21		T107	21		T108	1
true	17912	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	84	1			T54	2		T83	2		T87	2
others[1]	96	1			T6	2		T160	2		T181	2
others[2]	100	1			T351	2		T163	4		T352	2
others[3]	102	1			T163	4		T210	2		T355	2
others[4]	92	1			T84	2		T85	2		T180	2
others[5]	76	1			T83	2		T180	2		T163	2
others[6]	82	1			T85	4		T181	4		T163	4
others[7]	100	1			T85	2		T160	2		T66	2
false	7512	1			T13	21		T107	21		T108	1
true	15859	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	84	1			T29	2		T84	2		T85	2
others[1]	64	1			T180	2		T353	2		T166	4
others[2]	78	1			T93	2		T161	2		T180	2
others[3]	74	1			T29	2		T84	2		T86	2
others[4]	88	1			T42	2		T355	2		T373	2
others[5]	68	1			T87	2		T92	2		T93	2
others[6]	60	1			T163	2		T373	2		T374	4
others[7]	86	1			T85	2		T92	2		T357	2
false	6934	1			T13	21		T107	21		T108	1
true	15693	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	76	1			T30	2		T85	4		T163	2
others[1]	82	1			T53	2		T84	4		T85	2
others[2]	68	1			T180	2		T210	2		T375	2
others[3]	106	1			T86	2		T42	2		T90	2
others[4]	72	1			T87	2		T90	2		T91	2
others[5]	76	1			T65	2		T352	2		T360	2
others[6]	56	1			T161	2		T350	2		T210	2
others[7]	120	1			T83	2		T86	2		T89	2
false	6934	1			T13	21		T107	21		T108	1
true	15693	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	64	1			T30	2		T84	2		T42	2
others[1]	72	1			T29	2		T84	4		T357	2
others[2]	72	1			T29	2		T182	2		T65	2
others[3]	90	1			T83	2		T92	2		T351	6
others[4]	80	1			T87	4		T88	2		T92	2
others[5]	92	1			T87	2		T88	2		T42	2
others[6]	60	1			T93	2		T360	2		T40	2
others[7]	104	1			T53	4		T87	2		T89	2
false	6294	1			T13	21		T107	21		T108	1
true	15681	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	76	1			T30	2		T83	2		T85	4
others[1]	76	1			T53	2		T87	2		T162	2
others[2]	76	1			T42	2		T91	2		T357	2
others[3]	72	1			T85	2		T86	2		T210	2
others[4]	98	1			T42	2		T92	2		T180	2
others[5]	96	1			T84	2		T90	2		T93	2
others[6]	84	1			T84	2		T87	2		T161	2
others[7]	76	1			T53	2		T163	4		T210	2
false	6294	1			T13	21		T107	21		T108	1
true	15681	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	38	1			T86	2		T88	2		T352	2
others[1]	60	1			T29	2		T93	2		T162	2
others[2]	56	1			T86	2		T180	2		T371	2
others[3]	64	1			T30	2		T181	2		T352	2
others[4]	58	1			T85	2		T93	2		T180	2
others[5]	46	1			T182	2		T210	4		T376	2
others[6]	38	1			T85	2		T64	2		T375	2
others[7]	44	1			T92	2		T181	2		T353	2
false	6751	1			T13	21		T107	21		T108	1
true	17128	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	44	1			T88	2		T93	2		T210	2
others[1]	66	1			T88	2		T91	2		T180	2
others[2]	76	1			T90	4		T92	2		T93	2
others[3]	62	1			T84	2		T166	2		T377	4
others[4]	76	1			T84	4		T88	2		T89	2
others[5]	52	1			T29	2		T91	2		T371	2
others[6]	60	1			T29	2		T210	2		T166	4
others[7]	70	1			T91	2		T92	2		T181	2
false	6751	1			T13	21		T107	21		T108	1
true	17128	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36	1			T4	2		T11	1		T27	1
others[1]	29	1			T15	1		T119	1		T372	1
others[2]	34	1			T316	1		T372	1		T370	1
others[3]	27	1			T71	2		T27	1		T28	1
others[4]	38	1			T4	2		T11	2		T71	1
others[5]	33	1			T11	1		T28	2		T119	1
others[6]	24	1			T119	1		T370	3		T219	1
others[7]	32	1			T316	1		T165	2		T378	1
false	11146	1			T13	21		T107	21		T108	1
true	17974	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34	1			T164	2		T364	2		T144	2
others[1]	26	1			T85	2		T43	2		T144	4
others[2]	24	1			T163	4		T166	2		T44	2
others[3]	16	1			T162	2		T163	2		T364	2
others[4]	14	1			T161	2		T365	2		T379	2
others[5]	26	1			T85	2		T165	2		T362	2
others[6]	26	1			T91	2		T160	2		T165	2
others[7]	22	1			T363	2		T346	2		T380	2
false	10007	1			T13	21		T107	21		T108	1
true	15987	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30	1			T4	1		T15	1		T219	2
others[1]	31	1			T71	1		T316	1		T219	2
others[2]	34	1			T27	1		T119	1		T222	3
others[3]	22	1			T219	1		T203	1		T222	1
others[4]	35	1			T27	1		T28	1		T324	1
others[5]	21	1			T182	2		T316	1		T347	1
others[6]	40	1			T4	1		T11	1		T27	1
others[7]	41	1			T11	1		T71	1		T322	1
false	13614	1			T13	21		T107	21		T108	1
true	2158	1			T1	5		T4	2		T7	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	40	1			T180	2		T371	2		T357	2
others[1]	56	1			T86	4		T88	2		T352	2
others[2]	48	1			T376	2		T375	2		T377	4
others[3]	26	1			T181	2		T163	2		T381	2
others[4]	50	1			T92	2		T182	2		T162	2
others[5]	66	1			T29	2		T353	2		T210	2
others[6]	62	1			T30	2		T85	4		T93	2
others[7]	56	1			T93	2		T180	2		T181	2
false	13544	1			T13	21		T107	21		T108	1
true	16101	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	86	1			T29	2		T91	4		T92	2
others[1]	74	1			T90	2		T181	2		T352	2
others[2]	58	1			T84	2		T162	2		T371	2
others[3]	48	1			T88	4		T381	2		T166	2
others[4]	64	1			T84	2		T88	2		T89	2
others[5]	56	1			T91	2		T181	2		T182	2
others[6]	66	1			T29	2		T180	2		T352	2
others[7]	54	1			T84	2		T90	2		T93	2
false	13544	1			T13	21		T107	21		T108	1
true	16047	1			T13	21		T107	21		T108	1

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	47	1			T4	1		T11	1		T27	1
others[1]	28	1			T11	1		T28	1		T15	1
others[2]	28	1			T28	1		T15	1		T316	1
others[3]	30	1			T4	1		T11	1		T372	1
others[4]	30	1			T11	1		T28	1		T370	1
others[5]	31	1			T71	1		T28	1		T165	2
others[6]	37	1			T4	1		T71	1		T119	1
others[7]	27	1			T4	1		T71	1		T27	1
false	13614	1			T13	21		T107	21		T108	1
true	2122	1			T112	1		T1	5		T4	3