Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

Group : otp_ctrl_env_pkg::otp_ctrl_unbuf_access_lock_cg_wrap::unbuf_access_lock_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[CreatorSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[OwnerSwCfgIdx]	100.00	1	100	1	64	64
buf_err_code_cg_wrap[VendorTestIdx]	100.00	1	100	1	64	64

---

Group Instance : buf_err_code_cg_wrap[CreatorSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[CreatorSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[OwnerSwCfgIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[OwnerSwCfgIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

---

Group Instance : buf_err_code_cg_wrap[VendorTestIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
operation_type	2	0	2	100.00	100	1	1	0
read_access_locked	2	0	2	100.00	100	1	1	2
write_access_locked	2	0	2	100.00	100	1	1	2

Crosses for Group Instance buf_err_code_cg_wrap[VendorTestIdx]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
unbuf_part_access_cross	8	0	8	100.00	100	1	1	0

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

34783

1

T1

126

T2

16

T4

75

write_op

10284

1

T1

46

T2

8

T4

37

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15950

1

T1

49

T2

24

T4

30

auto[1]

29117

1

T1

123

T4

82

T7

44

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34045

1

T1

172

T2

24

T4

112

auto[1]

11022

1

T6

9

T53

14

T96

14

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	7340	1			T1	29		T2	16		T4	19
auto[0]	auto[0]	write_op	4372	1			T1	20		T2	8		T4	11
auto[0]	auto[1]	read_op	2861	1			T53	7		T96	1		T29	2
auto[0]	auto[1]	write_op	1377	1			T53	3		T29	2		T54	1
auto[1]	auto[0]	read_op	19310	1			T1	97		T4	56		T7	42
auto[1]	auto[0]	write_op	3023	1			T1	26		T4	26		T7	2
auto[1]	auto[1]	read_op	5272	1			T6	6		T53	3		T96	9
auto[1]	auto[1]	write_op	1512	1			T6	3		T53	1		T96	4

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

35172

1

T1

122

T2

8

T4

64

write_op

9952

1

T1

47

T2

4

T4

21

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15900

1

T1

54

T2

12

T4

30

auto[1]

29224

1

T1

115

T4

55

T7

43

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34404

1

T1

169

T2

12

T4

85

auto[1]

10720

1

T6

6

T53

31

T54

12

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	7408	1			T1	35		T2	8		T4	22
auto[0]	auto[0]	write_op	4288	1			T1	19		T2	4		T4	8
auto[0]	auto[1]	read_op	2820	1			T6	2		T53	6		T54	5
auto[0]	auto[1]	write_op	1384	1			T53	2		T54	4		T30	3
auto[1]	auto[0]	read_op	19836	1			T1	87		T4	42		T7	42
auto[1]	auto[0]	write_op	2872	1			T1	28		T4	13		T7	1
auto[1]	auto[1]	read_op	5108	1			T6	3		T53	16		T54	3
auto[1]	auto[1]	write_op	1408	1			T6	1		T53	7		T30	1

Summary for Variable operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for operation_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_op

33776

1

T1

98

T2

10

T4

62

write_op

6661

1

T1

23

T2

3

T4

19

---

Summary for Variable read_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for read_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13818

1

T1

32

T2

13

T4

30

auto[1]

26619

1

T1

89

T4

51

T7

52

---

Summary for Variable write_access_locked

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for write_access_locked

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37024

1

T1

121

T2

13

T4

81

auto[1]

3413

1

T83

2

T85

53

T86

3

---

Summary for Cross unbuf_part_access_cross

Samples crossed: read_access_locked write_access_locked operation_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for unbuf_part_access_cross

Bins

read_access_locked	write_access_locked	operation_type	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	read_op	8813	1			T1	19		T2	10		T4	23
auto[0]	auto[0]	write_op	3761	1			T1	13		T2	3		T4	7
auto[0]	auto[1]	read_op	1007	1			T83	1		T85	12		T86	3
auto[0]	auto[1]	write_op	237	1			T83	1		T85	2		T42	1
auto[1]	auto[0]	read_op	22025	1			T1	79		T4	39		T7	51
auto[1]	auto[0]	write_op	2425	1			T1	10		T4	12		T7	1
auto[1]	auto[1]	read_op	1931	1			T85	33		T42	10		T160	4
auto[1]	auto[1]	write_op	238	1			T85	6		T160	1		T161	2