Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_core_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_otp_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8501134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15386295

1

T13

296

T107

305

T108

464

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7403860	1			T13	129		T107	114		T108	150
values[0x0]	6281281	1			T13	162		T107	152		T108	173
values[0x1]	10202288	1			T13	131		T107	140		T108	141

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4450923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

19436506

1

T13

324

T107

332

T108

464

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	96517	1			T13	1		T107	1		T183	1
valid_sources[0x01]	91410	1			T107	2		T108	11		T183	8
valid_sources[0x02]	91399	1			T13	2		T107	1		T183	5
valid_sources[0x03]	91843	1			T13	1		T107	5		T183	1
valid_sources[0x04]	91722	1			T13	1		T107	1		T183	1
valid_sources[0x05]	91618	1			T13	2		T107	2		T183	1
valid_sources[0x06]	90147	1			T13	1		T107	1		T183	2
valid_sources[0x07]	92783	1			T107	4		T189	2		T191	2
valid_sources[0x08]	93335	1			T185	1		T200	3		T251	4
valid_sources[0x09]	89819	1			T107	1		T108	29		T183	4
valid_sources[0x0a]	92527	1			T13	5		T107	1		T183	2
valid_sources[0x0b]	92686	1			T13	1		T107	2		T108	15
valid_sources[0x0c]	88647	1			T13	2		T107	1		T183	2
valid_sources[0x0d]	95645	1			T13	2		T107	4		T108	8
valid_sources[0x0e]	92428	1			T13	2		T107	3		T108	4
valid_sources[0x0f]	96792	1			T13	2		T107	3		T183	1
valid_sources[0x10]	88744	1			T13	2		T107	2		T183	1
valid_sources[0x11]	92212	1			T107	2		T184	1		T186	12
valid_sources[0x12]	90645	1			T107	4		T183	2		T186	2
valid_sources[0x13]	105243	1			T13	1		T107	2		T184	2
valid_sources[0x14]	90838	1			T13	2		T107	3		T108	4
valid_sources[0x15]	91114	1			T13	4		T185	1		T189	2
valid_sources[0x16]	89875	1			T13	2		T107	2		T108	1
valid_sources[0x17]	91940	1			T13	4		T108	5		T185	1
valid_sources[0x18]	90139	1			T13	2		T183	2		T185	1
valid_sources[0x19]	90483	1			T13	2		T186	5		T189	2
valid_sources[0x1a]	93180	1			T13	2		T107	5		T183	1
valid_sources[0x1b]	88222	1			T13	4		T183	5		T185	1
valid_sources[0x1c]	92628	1			T13	1		T107	1		T183	2
valid_sources[0x1d]	89053	1			T13	1		T107	2		T183	3
valid_sources[0x1e]	95451	1			T13	4		T107	3		T183	1
valid_sources[0x1f]	90168	1			T13	4		T108	5		T185	3
valid_sources[0x20]	91914	1			T13	1		T107	2		T185	2
valid_sources[0x21]	88751	1			T13	1		T107	2		T183	1
valid_sources[0x22]	93717	1			T13	1		T107	1		T183	2
valid_sources[0x23]	92731	1			T13	2		T107	2		T184	6
valid_sources[0x24]	88486	1			T107	3		T185	2		T186	3
valid_sources[0x25]	120033	1			T13	4		T107	1		T183	1
valid_sources[0x26]	90268	1			T13	1		T107	1		T183	1
valid_sources[0x27]	88281	1			T107	1		T183	2		T185	3
valid_sources[0x28]	91216	1			T13	3		T107	2		T183	3
valid_sources[0x29]	92500	1			T13	2		T184	29		T189	2
valid_sources[0x2a]	108066	1			T13	2		T107	2		T108	4
valid_sources[0x2b]	92127	1			T13	2		T107	2		T183	2
valid_sources[0x2c]	95741	1			T13	2		T107	2		T108	1
valid_sources[0x2d]	89461	1			T13	1		T185	1		T191	2
valid_sources[0x2e]	94687	1			T13	1		T107	3		T184	2
valid_sources[0x2f]	87767	1			T13	2		T107	3		T183	1
valid_sources[0x30]	90004	1			T13	1		T183	1		T185	2
valid_sources[0x31]	89090	1			T107	1		T183	4		T191	12
valid_sources[0x32]	92723	1			T13	2		T183	3		T184	4
valid_sources[0x33]	95058	1			T13	1		T107	4		T183	2
valid_sources[0x34]	89943	1			T13	2		T185	1		T188	768
valid_sources[0x35]	91701	1			T13	1		T107	1		T186	1
valid_sources[0x36]	89043	1			T13	3		T107	2		T108	2
valid_sources[0x37]	93917	1			T13	3		T185	1		T186	7
valid_sources[0x38]	90183	1			T13	2		T107	4		T183	4
valid_sources[0x39]	88006	1			T13	1		T107	1		T108	6
valid_sources[0x3a]	90634	1			T13	4		T107	1		T183	6
valid_sources[0x3b]	94840	1			T13	2		T107	4		T186	12
valid_sources[0x3c]	112030	1			T13	2		T183	1		T184	20
valid_sources[0x3d]	89014	1			T13	1		T107	2		T183	6
valid_sources[0x3e]	100313	1			T13	2		T107	1		T183	2
valid_sources[0x3f]	94820	1			T13	1		T107	2		T183	1
valid_sources[0x40]	95147	1			T13	2		T107	2		T183	2
valid_sources[0x41]	90609	1			T13	2		T107	1		T183	1
valid_sources[0x42]	92546	1			T13	2		T107	1		T183	5
valid_sources[0x43]	90742	1			T13	2		T107	2		T189	2
valid_sources[0x44]	94148	1			T107	3		T183	3		T185	1
valid_sources[0x45]	95056	1			T13	1		T107	1		T183	3
valid_sources[0x46]	89153	1			T13	2		T107	1		T185	1
valid_sources[0x47]	91088	1			T13	2		T108	1		T183	4
valid_sources[0x48]	88875	1			T13	1		T185	1		T189	1
valid_sources[0x49]	97414	1			T13	1		T107	2		T108	12
valid_sources[0x4a]	92864	1			T13	1		T107	2		T183	5
valid_sources[0x4b]	89261	1			T13	1		T107	1		T108	1
valid_sources[0x4c]	88700	1			T107	1		T108	38		T183	5
valid_sources[0x4d]	92950	1			T13	3		T107	3		T184	5
valid_sources[0x4e]	92770	1			T13	1		T107	4		T185	3
valid_sources[0x4f]	89774	1			T13	1		T107	1		T108	5
valid_sources[0x50]	90808	1			T13	1		T107	2		T183	4
valid_sources[0x51]	122620	1			T13	4		T107	2		T108	2
valid_sources[0x52]	89521	1			T107	1		T183	3		T185	1
valid_sources[0x53]	91557	1			T13	2		T107	2		T184	2
valid_sources[0x54]	90294	1			T107	2		T183	4		T185	2
valid_sources[0x55]	90707	1			T13	2		T107	4		T183	2
valid_sources[0x56]	91848	1			T107	3		T183	2		T185	1
valid_sources[0x57]	95593	1			T13	3		T107	4		T108	2
valid_sources[0x58]	91099	1			T13	2		T107	1		T108	10
valid_sources[0x59]	90899	1			T13	2		T107	1		T183	2
valid_sources[0x5a]	91029	1			T13	1		T108	8		T183	2
valid_sources[0x5b]	90509	1			T13	2		T107	1		T108	10
valid_sources[0x5c]	95510	1			T13	2		T107	2		T183	1
valid_sources[0x5d]	96502	1			T13	1		T107	2		T183	3
valid_sources[0x5e]	91259	1			T13	1		T107	3		T185	4
valid_sources[0x5f]	92679	1			T13	2		T107	2		T108	5
valid_sources[0x60]	88807	1			T13	4		T107	2		T183	1
valid_sources[0x61]	91691	1			T13	2		T107	1		T185	3
valid_sources[0x62]	90279	1			T13	2		T107	1		T183	6
valid_sources[0x63]	87303	1			T13	1		T107	1		T185	1
valid_sources[0x64]	88455	1			T13	3		T107	2		T108	2
valid_sources[0x65]	95039	1			T185	2		T189	4		T200	2
valid_sources[0x66]	91862	1			T107	1		T183	1		T185	1
valid_sources[0x67]	92503	1			T13	1		T107	1		T108	10
valid_sources[0x68]	95670	1			T13	1		T107	5		T183	2
valid_sources[0x69]	93796	1			T107	1		T185	1		T186	2
valid_sources[0x6a]	91951	1			T13	1		T107	1		T183	3
valid_sources[0x6b]	88694	1			T107	1		T108	6		T183	5
valid_sources[0x6c]	91873	1			T13	1		T107	1		T184	7
valid_sources[0x6d]	91000	1			T13	1		T185	1		T251	1
valid_sources[0x6e]	90422	1			T108	1		T183	1		T185	1
valid_sources[0x6f]	89094	1			T13	1		T107	2		T183	5
valid_sources[0x70]	98920	1			T13	1		T107	4		T183	1
valid_sources[0x71]	95785	1			T107	3		T183	1		T186	15
valid_sources[0x72]	92628	1			T13	1		T107	1		T183	5
valid_sources[0x73]	89141	1			T107	1		T186	1		T251	1
valid_sources[0x74]	91025	1			T13	1		T107	1		T185	1
valid_sources[0x75]	87901	1			T13	1		T107	2		T108	9
valid_sources[0x76]	89773	1			T13	3		T107	1		T184	10
valid_sources[0x77]	101392	1			T13	4		T107	2		T108	2
valid_sources[0x78]	92496	1			T13	2		T107	2		T183	1
valid_sources[0x79]	94186	1			T13	1		T107	2		T185	3
valid_sources[0x7a]	92969	1			T13	3		T183	2		T184	25
valid_sources[0x7b]	90332	1			T13	3		T107	2		T183	2
valid_sources[0x7c]	92781	1			T13	3		T107	1		T108	7
valid_sources[0x7d]	90789	1			T107	3		T183	5		T184	6
valid_sources[0x7e]	92608	1			T13	4		T107	2		T185	1
valid_sources[0x7f]	93656	1			T13	1		T107	3		T183	5
valid_sources[0x80]	90827	1			T13	1		T107	1		T184	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4245833

1

T13

46

T107

53

T108

150

values[0x0]

all_enables

biggest_size

5607314

1

T13

138

T107

132

T108

173

values[0x1]

all_enables

biggest_size

5533148

1

T13

112

T107

120

T108

141

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	778771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

28644702

1

T13

80

T107

77

T108

175

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7209635	1			T13	244		T107	238		T108	89
values[0x0]	10776689	1			T13	47		T107	38		T108	49
values[0x1]	11437149	1			T13	34		T107	48		T108	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	268508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29154965

1

T13

154

T107

156

T108

175

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	111518	1			T184	1		T187	1		T188	4
valid_sources[0x01]	112431	1			T188	1		T200	1		T195	3
valid_sources[0x02]	110437	1			T13	1		T183	3		T185	2
valid_sources[0x03]	112535	1			T185	1		T188	9		T200	1
valid_sources[0x04]	116734	1			T13	1		T108	1		T184	1
valid_sources[0x05]	117037	1			T13	2		T188	17		T200	4
valid_sources[0x06]	114058	1			T13	2		T188	4		T201	3
valid_sources[0x07]	114954	1			T13	2		T107	11		T183	1
valid_sources[0x08]	115500	1			T184	1		T188	12		T200	12
valid_sources[0x09]	117354	1			T184	1		T185	1		T186	3
valid_sources[0x0a]	117967	1			T13	2		T184	1		T186	4
valid_sources[0x0b]	112302	1			T107	22		T183	3		T184	1
valid_sources[0x0c]	113307	1			T188	11		T189	5		T200	5
valid_sources[0x0d]	115308	1			T184	2		T185	2		T186	4
valid_sources[0x0e]	112810	1			T13	2		T185	2		T188	1
valid_sources[0x0f]	114326	1			T188	2		T200	1		T201	4
valid_sources[0x10]	115217	1			T183	1		T184	1		T185	10
valid_sources[0x11]	115882	1			T13	3		T108	8		T184	1
valid_sources[0x12]	121494	1			T183	1		T188	26		T200	1
valid_sources[0x13]	112277	1			T184	1		T185	1		T201	3
valid_sources[0x14]	111848	1			T13	1		T184	1		T185	1
valid_sources[0x15]	115150	1			T13	2		T107	35		T108	20
valid_sources[0x16]	119790	1			T183	2		T184	1		T188	2
valid_sources[0x17]	112423	1			T13	2		T184	1		T188	10
valid_sources[0x18]	116124	1			T183	4		T186	12		T191	1
valid_sources[0x19]	108635	1			T13	3		T183	3		T184	1
valid_sources[0x1a]	116965	1			T13	8		T185	2		T188	11
valid_sources[0x1b]	114327	1			T185	1		T188	7		T200	10
valid_sources[0x1c]	113062	1			T13	2		T183	1		T184	1
valid_sources[0x1d]	114841	1			T183	2		T184	1		T188	1
valid_sources[0x1e]	113209	1			T13	2		T108	9		T183	3
valid_sources[0x1f]	115767	1			T185	1		T188	31		T200	1
valid_sources[0x20]	116667	1			T185	2		T188	14		T200	10
valid_sources[0x21]	111348	1			T13	1		T183	1		T184	1
valid_sources[0x22]	118334	1			T183	1		T185	2		T188	12
valid_sources[0x23]	108955	1			T13	1		T188	5		T200	3
valid_sources[0x24]	113263	1			T13	2		T185	4		T188	19
valid_sources[0x25]	113564	1			T13	2		T183	1		T185	3
valid_sources[0x26]	114689	1			T13	1		T184	1		T185	1
valid_sources[0x27]	118830	1			T13	1		T188	1		T191	2
valid_sources[0x28]	113984	1			T188	10		T201	5		T195	4
valid_sources[0x29]	117100	1			T13	1		T107	2		T184	2
valid_sources[0x2a]	114914	1			T13	4		T185	1		T188	4
valid_sources[0x2b]	113224	1			T184	1		T185	3		T186	8
valid_sources[0x2c]	116267	1			T13	2		T107	11		T108	9
valid_sources[0x2d]	114877	1			T184	2		T185	5		T188	6
valid_sources[0x2e]	114554	1			T13	2		T184	1		T188	6
valid_sources[0x2f]	115500	1			T13	1		T185	1		T188	14
valid_sources[0x30]	116240	1			T183	6		T188	11		T191	14
valid_sources[0x31]	110625	1			T13	3		T183	2		T185	1
valid_sources[0x32]	123436	1			T13	2		T188	7		T201	3
valid_sources[0x33]	113539	1			T13	3		T185	9		T186	8
valid_sources[0x34]	114592	1			T185	2		T186	3		T188	6
valid_sources[0x35]	111328	1			T13	2		T184	1		T188	7
valid_sources[0x36]	111042	1			T188	1		T200	7		T249	12
valid_sources[0x37]	113852	1			T107	3		T185	2		T188	13
valid_sources[0x38]	115772	1			T13	1		T183	6		T185	1
valid_sources[0x39]	114334	1			T13	1		T185	3		T186	24
valid_sources[0x3a]	113942	1			T13	1		T186	1		T188	8
valid_sources[0x3b]	115950	1			T185	1		T188	15		T189	17
valid_sources[0x3c]	115936	1			T185	3		T188	7		T192	1
valid_sources[0x3d]	117328	1			T13	7		T184	1		T185	2
valid_sources[0x3e]	117019	1			T183	1		T185	3		T186	8
valid_sources[0x3f]	119737	1			T13	3		T188	11		T201	2
valid_sources[0x40]	113000	1			T13	4		T185	4		T188	7
valid_sources[0x41]	110011	1			T107	19		T185	3		T188	5
valid_sources[0x42]	117215	1			T13	2		T183	2		T185	5
valid_sources[0x43]	116486	1			T13	1		T107	47		T183	1
valid_sources[0x44]	115403	1			T13	2		T184	1		T185	4
valid_sources[0x45]	112774	1			T185	1		T188	4		T200	3
valid_sources[0x46]	115701	1			T188	29		T192	1		T195	2
valid_sources[0x47]	116266	1			T184	1		T185	2		T186	10
valid_sources[0x48]	113843	1			T13	1		T107	33		T184	1
valid_sources[0x49]	112043	1			T184	1		T185	4		T188	30
valid_sources[0x4a]	118900	1			T13	2		T185	1		T188	15
valid_sources[0x4b]	110731	1			T13	4		T183	3		T184	1
valid_sources[0x4c]	113321	1			T13	1		T185	3		T188	2
valid_sources[0x4d]	115200	1			T183	1		T184	1		T185	4
valid_sources[0x4e]	114154	1			T13	3		T183	2		T184	1
valid_sources[0x4f]	116323	1			T13	2		T183	1		T185	2
valid_sources[0x50]	115788	1			T13	3		T183	1		T184	1
valid_sources[0x51]	114506	1			T13	5		T183	2		T185	2
valid_sources[0x52]	116069	1			T185	3		T188	5		T200	5
valid_sources[0x53]	111688	1			T13	1		T183	2		T184	1
valid_sources[0x54]	111628	1			T13	1		T185	2		T186	4
valid_sources[0x55]	111282	1			T13	4		T188	8		T200	2
valid_sources[0x56]	115339	1			T184	2		T185	1		T186	3
valid_sources[0x57]	114791	1			T13	2		T185	3		T188	1
valid_sources[0x58]	113952	1			T183	1		T188	9		T200	1
valid_sources[0x59]	113252	1			T183	1		T184	1		T188	18
valid_sources[0x5a]	112145	1			T13	1		T185	1		T187	1
valid_sources[0x5b]	115075	1			T183	7		T184	1		T185	3
valid_sources[0x5c]	114822	1			T185	2		T187	1		T201	2
valid_sources[0x5d]	113031	1			T13	1		T185	6		T188	12
valid_sources[0x5e]	118220	1			T13	3		T183	2		T184	2
valid_sources[0x5f]	113707	1			T185	2		T188	29		T200	12
valid_sources[0x60]	119799	1			T107	9		T183	1		T185	2
valid_sources[0x61]	118391	1			T184	1		T185	2		T195	7
valid_sources[0x62]	113816	1			T13	1		T184	1		T185	3
valid_sources[0x63]	120669	1			T13	1		T186	2		T188	2
valid_sources[0x64]	117548	1			T13	1		T108	4		T183	2
valid_sources[0x65]	113081	1			T13	1		T200	2		T201	1
valid_sources[0x66]	110873	1			T13	3		T107	12		T188	9
valid_sources[0x67]	118331	1			T185	3		T188	5		T195	7
valid_sources[0x68]	116917	1			T13	1		T184	1		T185	3
valid_sources[0x69]	113337	1			T107	1		T186	6		T200	5
valid_sources[0x6a]	113315	1			T183	2		T185	1		T187	1
valid_sources[0x6b]	116744	1			T13	1		T184	2		T185	3
valid_sources[0x6c]	112940	1			T13	2		T184	1		T185	1
valid_sources[0x6d]	114659	1			T185	2		T186	4		T188	6
valid_sources[0x6e]	115483	1			T107	2		T185	6		T188	24
valid_sources[0x6f]	114559	1			T13	1		T184	1		T185	2
valid_sources[0x70]	118292	1			T13	1		T184	2		T188	10
valid_sources[0x71]	109065	1			T13	4		T183	1		T185	3
valid_sources[0x72]	110727	1			T183	1		T185	2		T200	2
valid_sources[0x73]	115842	1			T13	2		T108	14		T183	2
valid_sources[0x74]	117934	1			T13	3		T185	2		T188	13
valid_sources[0x75]	109488	1			T185	2		T187	1		T188	13
valid_sources[0x76]	117166	1			T13	3		T183	2		T184	1
valid_sources[0x77]	116781	1			T183	1		T184	1		T188	10
valid_sources[0x78]	114056	1			T13	1		T188	19		T191	4
valid_sources[0x79]	118844	1			T185	5		T188	4		T200	6
valid_sources[0x7a]	112179	1			T13	1		T183	1		T185	1
valid_sources[0x7b]	115639	1			T13	2		T185	3		T188	1
valid_sources[0x7c]	118381	1			T185	3		T188	12		T195	7
valid_sources[0x7d]	113703	1			T13	1		T183	2		T188	5
valid_sources[0x7e]	118375	1			T107	3		T185	3		T187	1
valid_sources[0x7f]	113988	1			T13	1		T107	13		T183	1
valid_sources[0x80]	113284	1			T13	1		T184	2		T192	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7196579

1

T13

15

T107

16

T108

89

values[0x0]

all_enables

biggest_size

10722643

1

T13

41

T107

27

T108

49

values[0x1]

all_enables

biggest_size

10725480

1

T13

24

T107

34

T108

37