Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

63735609

1

T13

129

T107

105

T185

659

full_word

18990604

1

T13

296

T107

306

T108

464

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	82725933	1			T13	415		T107	401		T108	464
auto[TlIntgErrCmd]	96	1			T13	2		T107	4		T200	6
auto[TlIntgErrData]	83	1			T13	2		T107	3		T200	5
auto[TlIntgErrBoth]	101	1			T13	6		T107	3		T200	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11732564

1

T13

129

T107

114

T108

150

auto[1]

70993649

1

T13

296

T107

297

T108

314

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7046692	1			T13	79		T107	59		T185	54
auto[TlIntgErrNone]	partial	auto[1]	56688663	1			T13	40		T107	38		T185	605
auto[TlIntgErrNone]	full_word	auto[0]	4685734	1			T13	46		T107	53		T108	150
auto[TlIntgErrNone]	full_word	auto[1]	14304844	1			T13	250		T107	251		T108	314
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T200	3		T243	3		T249	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T13	2		T107	3		T200	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T201	1		T330	1		T333	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T107	1		T249	1		T329	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T13	1		T107	2		T200	4
auto[TlIntgErrData]	partial	auto[1]	30	1			T13	1		T107	1		T201	2
auto[TlIntgErrData]	full_word	auto[0]	4	1			T274	2		T329	1		T330	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T200	1		T250	1		T287	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T13	3		T200	4		T201	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1			T13	3		T107	2		T200	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T200	1		T329	1		T305	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T107	1		T287	1		T330	1