Unified Coverage Report :: Module :: prim_secded_inv_72_64_dec

Module : prim_secded_inv_72_64_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	58.90			58.90
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	63.70			63.70
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	64.38			64.38
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	67.12			67.12
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	72.60			72.60
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	72.60			72.60
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	75.34			75.34
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	75.34			75.34
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	79.45			79.45
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	82.19			82.19
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	84.93			84.93
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	93.15			93.15
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	95.89			95.89

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.90			58.90

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
58.90			58.90

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.70			63.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
64.38			64.38

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.12			67.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.12			67.12

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.60			72.60

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.34			75.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.34			75.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.34			75.34

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.34			75.34

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.45			79.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.45			79.45

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.19			82.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.19			82.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.93			84.93

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.93			84.93

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.15			93.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	66.67			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.89			95.89

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_otp_ctrl_ecc_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T53,T29	Yes	T6,T53,T29	INPUT
data_o[63:0]	Yes	Yes	T6,T53,T29	Yes	T6,T53,T29	OUTPUT
syndrome_o[2:0]	Yes	Yes	T130,T122,T131	Yes	T130,T122,T131	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T130,*T122,*T131	Yes	T130,T122,T131	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	172	58.90
Total Bits 0->1	146	86	58.90
Total Bits 1->0	146	86	58.90

Ports	4	0	0.00
Port Bits	292	172	58.90
Port Bits 0->1	146	86	58.90
Port Bits 1->0	146	86	58.90

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[5:4]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[7]	No	No		No		INPUT
data_i[8]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[9]	No	No		No		INPUT
data_i[13:10]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[14]	No	No		No		INPUT
data_i[17:15]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[19:18]	No	No		No		INPUT
data_i[21:20]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[22]	No	No		No		INPUT
data_i[23]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[26:24]	No	No		No		INPUT
data_i[28:27]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[32:31]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[33]	No	No		No		INPUT
data_i[35:34]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[38:36]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T6,*T53,*T96	Yes	T5,T6,T53	INPUT
data_i[40]	No	No		No		INPUT
data_i[49:41]	Yes	Yes	T6,T53,T96	Yes	T5,T6,T53	INPUT
data_i[50]	No	No		No		INPUT
data_i[52:51]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[56:53]	No	No		No		INPUT
data_i[58:57]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[71:61]	Yes	Yes	T6,T53,T96	Yes	T5,T6,T53	INPUT
data_o[3:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[5:4]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[8]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[9]	No	No		No		OUTPUT
data_o[13:10]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[17:15]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[19:18]	No	No		No		OUTPUT
data_o[21:20]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[23]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[26:24]	No	No		No		OUTPUT
data_o[28:27]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[32:31]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[33]	No	No		No		OUTPUT
data_o[35:34]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[38:36]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T6,*T53,*T96	Yes	T5,T6,T53	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[49:41]	Yes	Yes	T6,T53,T96	Yes	T5,T6,T53	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[52:51]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[56:53]	No	No		No		OUTPUT
data_o[58:57]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[60:59]	No	No		No		OUTPUT
data_o[63:61]	Yes	Yes	T6,T53,T96	Yes	T5,T6,T53	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	186	63.70
Total Bits 0->1	146	93	63.70
Total Bits 1->0	146	93	63.70

Ports	4	0	0.00
Port Bits	292	186	63.70
Port Bits 0->1	146	93	63.70
Port Bits 1->0	146	93	63.70

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[1]	Yes	Yes	*T6,*T53,*T96	Yes	T6,T53,T96	INPUT
data_i[3:2]	No	No		No		INPUT
data_i[4]	Yes	Yes	*T6,*T53,*T96	Yes	T6,T53,T96	INPUT
data_i[5]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	T6,T53,T96	Yes	T6,T53,T96	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[23:17]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[27:26]	No	No		No		INPUT
data_i[33:28]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[35:34]	No	No		No		INPUT
data_i[36]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[37]	No	No		No		INPUT
data_i[40:38]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[41]	No	No		No		INPUT
data_i[45:42]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[46]	No	No		No		INPUT
data_i[48:47]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[49]	No	No		No		INPUT
data_i[51:50]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[59:54]	Yes	Yes	T53,T96,T29	Yes	T53,T96,T29	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[63]	No	No		No		INPUT
data_i[67:64]	Yes	Yes	*T5,*T6,*T96	Yes	T5,T6,T96	INPUT
data_i[68]	No	No		No		INPUT
data_i[71:69]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Yes	Yes	*T6,*T53,*T96	Yes	T6,T53,T96	OUTPUT
data_o[3:2]	No	No		No		OUTPUT
data_o[4]	Yes	Yes	*T6,*T53,*T96	Yes	T6,T53,T96	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[6]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	T6,T53,T96	Yes	T6,T53,T96	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[23:17]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[27:26]	No	No		No		OUTPUT
data_o[33:28]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[35:34]	No	No		No		OUTPUT
data_o[36]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[37]	No	No		No		OUTPUT
data_o[40:38]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[41]	No	No		No		OUTPUT
data_o[45:42]	Yes	Yes	*T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[48:47]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[49]	No	No		No		OUTPUT
data_o[51:50]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[59:54]	Yes	Yes	T53,T96,T29	Yes	T53,T96,T29	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	188	64.38
Total Bits 0->1	146	94	64.38
Total Bits 1->0	146	94	64.38

Ports	4	0	0.00
Port Bits	292	188	64.38
Port Bits 0->1	146	94	64.38
Port Bits 1->0	146	94	64.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[2]	No	No		No		INPUT
data_i[4:3]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[5]	No	No		No		INPUT
data_i[9:6]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[10]	No	No		No		INPUT
data_i[11]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[12]	No	No		No		INPUT
data_i[13]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[16]	No	No		No		INPUT
data_i[19:17]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[21:20]	No	No		No		INPUT
data_i[23:22]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[24]	No	No		No		INPUT
data_i[31:25]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[35]	No	No		No		INPUT
data_i[37:36]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[38]	No	No		No		INPUT
data_i[39]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[40]	No	No		No		INPUT
data_i[41]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[43:42]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[47]	No	No		No		INPUT
data_i[49:48]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[51:50]	No	No		No		INPUT
data_i[57:52]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[58]	No	No		No		INPUT
data_i[59]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[60]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[63]	No	No		No		INPUT
data_i[71:64]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[1:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[4:3]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[9:6]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[11]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[12]	No	No		No		OUTPUT
data_o[13]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[16]	No	No		No		OUTPUT
data_o[19:17]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[21:20]	No	No		No		OUTPUT
data_o[23:22]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[31:25]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[37:36]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[40]	No	No		No		OUTPUT
data_o[41]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[43:42]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[49:48]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[51:50]	No	No		No		OUTPUT
data_o[57:52]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[59]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[60]	No	No		No		OUTPUT
data_o[62:61]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[63]	No	No		No		OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	196	67.12
Total Bits 0->1	146	98	67.12
Total Bits 1->0	146	98	67.12

Ports	4	0	0.00
Port Bits	292	196	67.12
Port Bits 0->1	146	98	67.12
Port Bits 1->0	146	98	67.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[6:1]	Yes	Yes	T53,T96,T54	Yes	T5,T53,T96	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[18:9]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[19]	No	No		No		INPUT
data_i[22:20]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[24:23]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[26]	No	No		No		INPUT
data_i[27]	Yes	Yes	*T53,*T96,*T54	Yes	T5,T53,T96	INPUT
data_i[29:28]	No	No		No		INPUT
data_i[34:30]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	INPUT
data_i[35]	No	No		No		INPUT
data_i[38:36]	Yes	Yes	T53,T96,T106	Yes	T5,T53,T96	INPUT
data_i[39]	No	No		No		INPUT
data_i[42:40]	Yes	Yes	T53,T96,T106	Yes	T5,T53,T96	INPUT
data_i[45:43]	No	No		No		INPUT
data_i[47:46]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[48]	No	No		No		INPUT
data_i[49]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[50]	No	No		No		INPUT
data_i[51]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	INPUT
data_i[55]	No	No		No		INPUT
data_i[58:56]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	INPUT
data_i[59]	No	No		No		INPUT
data_i[71:60]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[6:1]	Yes	Yes	T53,T96,T54	Yes	T5,T53,T96	OUTPUT
data_o[8:7]	No	No		No		OUTPUT
data_o[18:9]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[22:20]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[24:23]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[27]	Yes	Yes	*T53,*T96,*T54	Yes	T5,T53,T96	OUTPUT
data_o[29:28]	No	No		No		OUTPUT
data_o[34:30]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[38:36]	Yes	Yes	T53,T96,T106	Yes	T5,T53,T96	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[42:40]	Yes	Yes	T53,T96,T106	Yes	T5,T53,T96	OUTPUT
data_o[45:43]	No	No		No		OUTPUT
data_o[47:46]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[48]	No	No		No		OUTPUT
data_o[49]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[50]	No	No		No		OUTPUT
data_o[51]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[58:56]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	OUTPUT
data_o[59]	No	No		No		OUTPUT
data_o[63:60]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	212	72.60
Total Bits 0->1	146	106	72.60
Total Bits 1->0	146	106	72.60

Ports	4	0	0.00
Port Bits	292	212	72.60
Port Bits 0->1	146	106	72.60
Port Bits 1->0	146	106	72.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	No	No		No		INPUT
data_i[12:2]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[15]	No	No		No		INPUT
data_i[20:16]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[22:21]	No	No		No		INPUT
data_i[24:23]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[25]	No	No		No		INPUT
data_i[36:26]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[38:37]	No	No		No		INPUT
data_i[40:39]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[42:41]	No	No		No		INPUT
data_i[51:43]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[52]	No	No		No		INPUT
data_i[54:53]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[55]	No	No		No		INPUT
data_i[57:56]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[58]	No	No		No		INPUT
data_i[60:59]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[1:0]	No	No		No		OUTPUT
data_o[12:2]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[20:16]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[22:21]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[36:26]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[38:37]	No	No		No		OUTPUT
data_o[40:39]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[42:41]	No	No		No		OUTPUT
data_o[51:43]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[52]	No	No		No		OUTPUT
data_o[54:53]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[55]	No	No		No		OUTPUT
data_o[57:56]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[60:59]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	212	72.60
Total Bits 0->1	146	106	72.60
Total Bits 1->0	146	106	72.60

Ports	4	0	0.00
Port Bits	292	212	72.60
Port Bits 0->1	146	106	72.60
Port Bits 1->0	146	106	72.60

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[1]	No	No		No		INPUT
data_i[4:2]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	INPUT
data_i[8]	No	No		No		INPUT
data_i[17:9]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[18]	No	No		No		INPUT
data_i[21:19]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	INPUT
data_i[24:22]	No	No		No		INPUT
data_i[28:25]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	INPUT
data_i[30:29]	No	No		No		INPUT
data_i[38:31]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[39]	No	No		No		INPUT
data_i[45:40]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[46]	No	No		No		INPUT
data_i[50:47]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[52:51]	No	No		No		INPUT
data_i[55:53]	Yes	Yes	T96,T106,T84	Yes	T96,T106,T84	INPUT
data_i[56]	No	No		No		INPUT
data_i[60:57]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[0]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[1]	No	No		No		OUTPUT
data_o[4:2]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[17:9]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[18]	No	No		No		OUTPUT
data_o[21:19]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[24:22]	No	No		No		OUTPUT
data_o[28:25]	Yes	Yes	T53,T96,T106	Yes	T53,T96,T106	OUTPUT
data_o[30:29]	No	No		No		OUTPUT
data_o[38:31]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[39]	No	No		No		OUTPUT
data_o[45:40]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[50:47]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[52:51]	No	No		No		OUTPUT
data_o[55:53]	Yes	Yes	T96,T106,T84	Yes	T96,T106,T84	OUTPUT
data_o[56]	No	No		No		OUTPUT
data_o[60:57]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	220	75.34
Total Bits 0->1	146	110	75.34
Total Bits 1->0	146	110	75.34

Ports	4	0	0.00
Port Bits	292	220	75.34
Port Bits 0->1	146	110	75.34
Port Bits 1->0	146	110	75.34

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[4:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[5]	No	No		No		INPUT
data_i[7:6]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[8]	No	No		No		INPUT
data_i[10:9]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[11]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[14]	No	No		No		INPUT
data_i[15]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[17:16]	No	No		No		INPUT
data_i[18]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[19]	No	No		No		INPUT
data_i[23:20]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[24]	No	No		No		INPUT
data_i[25]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[26]	No	No		No		INPUT
data_i[37:27]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[38]	No	No		No		INPUT
data_i[44:39]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[47:45]	No	No		No		INPUT
data_i[71:48]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[4:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[5]	No	No		No		OUTPUT
data_o[7:6]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[10:9]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[15]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[17:16]	No	No		No		OUTPUT
data_o[18]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[23:20]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[24]	No	No		No		OUTPUT
data_o[25]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[26]	No	No		No		OUTPUT
data_o[37:27]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[44:39]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[47:45]	No	No		No		OUTPUT
data_o[63:48]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	220	75.34
Total Bits 0->1	146	110	75.34
Total Bits 1->0	146	110	75.34

Ports	4	0	0.00
Port Bits	292	220	75.34
Port Bits 0->1	146	110	75.34
Port Bits 1->0	146	110	75.34

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[9:0]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[10]	No	No		No		INPUT
data_i[12:11]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[13]	No	No		No		INPUT
data_i[14]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[16:15]	No	No		No		INPUT
data_i[18:17]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[20:19]	No	No		No		INPUT
data_i[21]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[22]	No	No		No		INPUT
data_i[31:23]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[32]	No	No		No		INPUT
data_i[34:33]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[35]	No	No		No		INPUT
data_i[42:36]	Yes	Yes	*T78,*T5,*T6	Yes	T78,T5,T6	INPUT
data_i[43]	No	No		No		INPUT
data_i[46:44]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[47]	No	No		No		INPUT
data_i[51:48]	Yes	Yes	*T78,*T5,*T6	Yes	T78,T5,T6	INPUT
data_i[53:52]	No	No		No		INPUT
data_i[71:54]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[9:0]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[10]	No	No		No		OUTPUT
data_o[12:11]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[13]	No	No		No		OUTPUT
data_o[14]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[16:15]	No	No		No		OUTPUT
data_o[18:17]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[20:19]	No	No		No		OUTPUT
data_o[21]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[31:23]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[34:33]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[35]	No	No		No		OUTPUT
data_o[42:36]	Yes	Yes	*T78,*T5,*T6	Yes	T78,T5,T6	OUTPUT
data_o[43]	No	No		No		OUTPUT
data_o[46:44]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[51:48]	Yes	Yes	*T78,*T5,*T6	Yes	T78,T5,T6	OUTPUT
data_o[53:52]	No	No		No		OUTPUT
data_o[63:54]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	232	79.45
Total Bits 0->1	146	116	79.45
Total Bits 1->0	146	116	79.45

Ports	4	0	0.00
Port Bits	292	232	79.45
Port Bits 0->1	146	116	79.45
Port Bits 1->0	146	116	79.45

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[1:0]	Yes	Yes	T53,T96,T29	Yes	T53,T96,T29	INPUT
data_i[2]	No	No		No		INPUT
data_i[7:3]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	INPUT
data_i[8]	No	No		No		INPUT
data_i[9]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[11:10]	No	No		No		INPUT
data_i[13:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[14]	No	No		No		INPUT
data_i[18:15]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[19]	No	No		No		INPUT
data_i[29:20]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[30]	No	No		No		INPUT
data_i[45:31]	Yes	Yes	*T53,*T96,*T29	Yes	T53,T96,T29	INPUT
data_i[46]	No	No		No		INPUT
data_i[53:47]	Yes	Yes	*T82,*T79,*T53	Yes	T82,T79,T53	INPUT
data_i[54]	No	No		No		INPUT
data_i[60:55]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[61]	No	No		No		INPUT
data_i[71:62]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[1:0]	Yes	Yes	T53,T96,T29	Yes	T53,T96,T29	OUTPUT
data_o[2]	No	No		No		OUTPUT
data_o[7:3]	Yes	Yes	*T5,*T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[8]	No	No		No		OUTPUT
data_o[9]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[11:10]	No	No		No		OUTPUT
data_o[13:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[14]	No	No		No		OUTPUT
data_o[18:15]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[19]	No	No		No		OUTPUT
data_o[29:20]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[45:31]	Yes	Yes	*T53,*T96,*T29	Yes	T53,T96,T29	OUTPUT
data_o[46]	No	No		No		OUTPUT
data_o[53:47]	Yes	Yes	*T82,*T79,*T53	Yes	T82,T79,T53	OUTPUT
data_o[54]	No	No		No		OUTPUT
data_o[60:55]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[61]	No	No		No		OUTPUT
data_o[63:62]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	240	82.19
Total Bits 0->1	146	120	82.19
Total Bits 1->0	146	120	82.19

Ports	4	0	0.00
Port Bits	292	240	82.19
Port Bits 0->1	146	120	82.19
Port Bits 1->0	146	120	82.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[6:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[7]	No	No		No		INPUT
data_i[10:8]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[15]	No	No		No		INPUT
data_i[22:16]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[23]	No	No		No		INPUT
data_i[37:24]	Yes	Yes	*T2,*T234,*T5	Yes	T2,T234,T5	INPUT
data_i[38]	No	No		No		INPUT
data_i[46:39]	Yes	Yes	*T2,*T5,*T6	Yes	T2,T5,T6	INPUT
data_i[47]	No	No		No		INPUT
data_i[52:48]	Yes	Yes	*T2,*T234,*T235	Yes	T2,T234,T235	INPUT
data_i[53]	No	No		No		INPUT
data_i[57:54]	Yes	Yes	*T2,*T5,T6	Yes	T2,T5,T6	INPUT
data_i[58]	No	No		No		INPUT
data_i[71:59]	Yes	Yes	T2,T234,T235	Yes	T2,T234,T235	INPUT
data_o[6:0]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[10:8]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[22:16]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[23]	No	No		No		OUTPUT
data_o[37:24]	Yes	Yes	*T2,*T234,*T5	Yes	T2,T234,T5	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[46:39]	Yes	Yes	*T2,*T5,*T6	Yes	T2,T5,T6	OUTPUT
data_o[47]	No	No		No		OUTPUT
data_o[52:48]	Yes	Yes	*T2,*T234,*T235	Yes	T2,T234,T235	OUTPUT
data_o[53]	No	No		No		OUTPUT
data_o[57:54]	Yes	Yes	*T2,*T5,T6	Yes	T2,T5,T6	OUTPUT
data_o[58]	No	No		No		OUTPUT
data_o[63:59]	Yes	Yes	T2,T234,T235	Yes	T2,T234,T235	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	0	0.00
Total Bits	292	248	84.93
Total Bits 0->1	146	124	84.93
Total Bits 1->0	146	124	84.93

Ports	4	0	0.00
Port Bits	292	248	84.93
Port Bits 0->1	146	124	84.93
Port Bits 1->0	146	124	84.93

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[0]	No	No		No		INPUT
data_i[3:1]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[4]	No	No		No		INPUT
data_i[10:5]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	INPUT
data_i[11]	No	No		No		INPUT
data_i[14:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_i[15]	No	No		No		INPUT
data_i[29:16]	Yes	Yes	*T236,*T5,*T6	Yes	T236,T5,T6	INPUT
data_i[30]	No	No		No		INPUT
data_i[31]	Yes	Yes	*T237	Yes	T237	INPUT
data_i[32]	No	No		No		INPUT
data_i[71:33]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	INPUT
data_o[0]	No	No		No		OUTPUT
data_o[3:1]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[10:5]	Yes	Yes	*T5,*T6,*T53	Yes	T5,T6,T53	OUTPUT
data_o[11]	No	No		No		OUTPUT
data_o[14:12]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[29:16]	Yes	Yes	*T236,*T5,*T6	Yes	T236,T5,T6	OUTPUT
data_o[30]	No	No		No		OUTPUT
data_o[31]	Yes	Yes	*T237	Yes	T237	OUTPUT
data_o[32]	No	No		No		OUTPUT
data_o[63:33]	Yes	Yes	T5,T6,T53	Yes	T5,T6,T53	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T2,T29,T106	Yes	T2,T29,T106	INPUT
data_o[63:0]	Yes	Yes	T2,T29,T106	Yes	T2,T29,T106	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T60,T238,T239	Yes	T60,T238,T239	INPUT
data_o[63:0]	Yes	Yes	T60,T238,T239	Yes	T60,T238,T239	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T53,T90	Yes	T5,T53,T90	INPUT
data_o[63:0]	Yes	Yes	T5,T53,T90	Yes	T5,T53,T90	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T9,T10,T106	Yes	T9,T10,T106	INPUT
data_o[63:0]	Yes	Yes	T9,T10,T106	Yes	T9,T10,T106	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T10,T85,T232	Yes	T10,T85,T232	INPUT
data_o[63:0]	Yes	Yes	T10,T85,T232	Yes	T10,T85,T232	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T9,T34,T29	Yes	T9,T34,T29	INPUT
data_o[63:0]	Yes	Yes	T9,T34,T29	Yes	T9,T34,T29	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T53,T34,T106	Yes	T5,T53,T34	INPUT
data_o[63:0]	Yes	Yes	T53,T34,T106	Yes	T5,T53,T34	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T240,T232,T241	Yes	T104,T240,T232	INPUT
data_o[63:0]	Yes	Yes	T240,T232,T241	Yes	T104,T240,T232	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T60,T96	Yes	T6,T60,T96	INPUT
data_o[63:0]	Yes	Yes	T6,T60,T96	Yes	T6,T60,T96	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[3].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T9,T60	Yes	T5,T9,T60	INPUT
data_o[63:0]	Yes	Yes	T5,T9,T60	Yes	T5,T9,T60	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T2,T5,T9	Yes	T2,T5,T9	INPUT
data_o[63:0]	Yes	Yes	T2,T5,T9	Yes	T2,T5,T9	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	INPUT
data_o[63:0]	Yes	Yes	T2,T9,T10	Yes	T2,T9,T10	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T9,T10,T53	Yes	T5,T9,T10	INPUT
data_o[63:0]	Yes	Yes	T9,T10,T53	Yes	T5,T9,T10	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T9,T53,T34	Yes	T9,T53,T34	INPUT
data_o[63:0]	Yes	Yes	T9,T53,T34	Yes	T9,T53,T34	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[4].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T60,T34	Yes	T6,T60,T34	INPUT
data_o[63:0]	Yes	Yes	T6,T60,T34	Yes	T6,T60,T34	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
data_o[63:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T34,T29	Yes	T5,T34,T29	INPUT
data_o[63:0]	Yes	Yes	T5,T34,T29	Yes	T5,T34,T29	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T9,T34,T106	Yes	T9,T34,T106	INPUT
data_o[63:0]	Yes	Yes	T9,T34,T106	Yes	T9,T34,T106	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[1].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T6,T60	Yes	T5,T6,T60	INPUT
data_o[63:0]	Yes	Yes	T5,T6,T60	Yes	T5,T6,T60	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[2].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T9,T60,T125	Yes	T9,T60,T125	INPUT
data_o[63:0]	Yes	Yes	T9,T60,T125	Yes	T9,T60,T125	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[3].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T9,T53,T106	Yes	T9,T53,T106	INPUT
data_o[63:0]	Yes	Yes	T9,T53,T106	Yes	T9,T53,T106	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[4].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T60,T57,T58	Yes	T60,T57,T34	INPUT
data_o[63:0]	Yes	Yes	T60,T57,T58	Yes	T60,T57,T34	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[5].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T106,T115,T242	Yes	T106,T115,T242	INPUT
data_o[63:0]	Yes	Yes	T106,T115,T242	Yes	T106,T115,T242	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[6].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T86,T242,T181	Yes	T34,T105,T86	INPUT
data_o[63:0]	Yes	Yes	T86,T242,T181	Yes	T34,T105,T86	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[7].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T37,T100	Yes	T6,T37,T100	INPUT
data_o[63:0]	Yes	Yes	T6,T37,T100	Yes	T6,T37,T100	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[8].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T34,T239,T242	Yes	T34,T105,T239	INPUT
data_o[63:0]	Yes	Yes	T34,T239,T242	Yes	T34,T105,T239	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[9].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T125,T104	Yes	T6,T125,T104	INPUT
data_o[63:0]	Yes	Yes	T6,T125,T104	Yes	T6,T125,T104	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg.gen_ecc_dec[10].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	272	93.15
Total Bits 0->1	146	136	93.15
Total Bits 1->0	146	136	93.15

Ports	4	2	50.00
Port Bits	292	272	93.15
Port Bits 0->1	146	136	93.15
Port Bits 1->0	146	136	93.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T5,T34,T29	Yes	T5,T34,T29	INPUT
data_o[63:0]	Yes	Yes	T5,T34,T29	Yes	T5,T34,T29	OUTPUT
syndrome_o[7:0]	No	No		No		OUTPUT
err_o[1:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T121,T42,T91	Yes	T121,T125,T105	INPUT
data_o[63:0]	Yes	Yes	T121,T42,T91	Yes	T121,T125,T105	OUTPUT
syndrome_o[2:0]	Yes	Yes	T122,T123,T124	Yes	T122,T123,T124	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T122,*T123,*T124	Yes	T122,T123,T124	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T53,T29	Yes	T6,T53,T29	INPUT
data_o[63:0]	Yes	Yes	T6,T53,T29	Yes	T6,T53,T29	OUTPUT
syndrome_o[2:0]	Yes	Yes	T130,T122,T131	Yes	T130,T122,T131	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T130,*T122,*T131	Yes	T130,T122,T131	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.u_otp_ctrl_ecc_reg.gen_ecc_dec[0].u_prim_secded_inv_72_64_dec

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	292	280	95.89
Total Bits 0->1	146	140	95.89
Total Bits 1->0	146	140	95.89

Ports	4	2	50.00
Port Bits	292	280	95.89
Port Bits 0->1	146	140	95.89
Port Bits 1->0	146	140	95.89

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[71:0]	Yes	Yes	T6,T53,T54	Yes	T6,T53,T54	INPUT
data_o[63:0]	Yes	Yes	T6,T53,T54	Yes	T6,T53,T54	OUTPUT
syndrome_o[2:0]	Yes	Yes	T131,T123,T137	Yes	T131,T123,T137	OUTPUT
syndrome_o[7:3]	No	No		No		OUTPUT
err_o[0]	Yes	Yes	*T131,*T123,*T137	Yes	T131,T123,T137	OUTPUT
err_o[1]	No	No		No		OUTPUT

*Tests covering at least one bit in the range